JPH0587146B2 - - Google Patents
Info
- Publication number
- JPH0587146B2 JPH0587146B2 JP61138644A JP13864486A JPH0587146B2 JP H0587146 B2 JPH0587146 B2 JP H0587146B2 JP 61138644 A JP61138644 A JP 61138644A JP 13864486 A JP13864486 A JP 13864486A JP H0587146 B2 JPH0587146 B2 JP H0587146B2
- Authority
- JP
- Japan
- Prior art keywords
- interlayer insulating
- forming
- insulating film
- wiring layer
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010410 layer Substances 0.000 claims description 45
- 239000011229 interlayer Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 23
- 239000011521 glass Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000007740 vapor deposition Methods 0.000 claims description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 235000019353 potassium silicate Nutrition 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000035936 sexual power Effects 0.000 description 1
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、集積回路装置等において多層配線
を形成するための改良された方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improved method for forming multilayer wiring in integrated circuit devices and the like.
［発明の概要］
この発明は、１層目の配線層を覆つて第１の層
間絶縁膜、配線段差軽減用の塗布ガラス膜、第２
の層間絶縁膜及び２層目の配線層を順次に形成す
る場合において、１層目の配線層の上方で第１の
層間絶縁膜が露呈されるように塗布ガラス膜をエ
ツチバツクしてから第２の層間絶縁膜及び２層目
の配線層を形成することにより配線層間の接続孔
における導通不良の発生を防止したものである。[Summary of the Invention] The present invention covers a first wiring layer and includes a first interlayer insulating film, a coated glass film for reducing wiring steps, and a second layer.
When forming an interlayer insulating film and a second wiring layer sequentially, the coated glass film is etched back so that the first interlayer insulating film is exposed above the first wiring layer, and then the second wiring layer is etched back. By forming an interlayer insulating film and a second wiring layer, it is possible to prevent conduction failures in connection holes between wiring layers.
［従来の技術］
従来、多層配線形成法としては、第６図乃至第
８図に示すように平坦化技術を採用したものが知
られている。すなわち、第６図の工程では、半導
体基板１０の表面にシリコンオキサイド等の絶縁
膜１２を介して１層目の配線層１４を形成した
後、CVD（ケミカル・ベーパー・デポジシヨン）
法により配線層１４をおおつて第１のPSG（リン
ケイ酸ガラス）膜１６を形成する。そして、この
PSG膜１６上に回転塗布法等によりSOG（スピ
ン・オン・ガラス）を塗布して配線段差軽減用の
ガラス膜１８を形成し、さらにその上にCVD法
により第２のPSG膜２０を形成する。[Prior Art] Conventionally, as a multilayer wiring formation method, a method employing a planarization technique as shown in FIGS. 6 to 8 is known. That is, in the process shown in FIG. 6, after forming the first wiring layer 14 on the surface of the semiconductor substrate 10 via the insulating film 12 made of silicon oxide or the like, CVD (Chemical Vapor Deposition) is performed.
A first PSG (phosphosilicate glass) film 16 is formed covering the wiring layer 14 by a method. And this
SOG (spin-on glass) is applied on the PSG film 16 by a spin coating method or the like to form a glass film 18 for reducing wiring steps, and a second PSG film 20 is further formed thereon by a CVD method. .
次に、第７図の工程では、レジスト層２２をマ
スクとして選択的なドライエツチ処理を行なうこ
とにより、配線層１４の一部を露呈させるような
接続孔２４を形成する。 Next, in the step shown in FIG. 7, a selective dry etching process is performed using the resist layer 22 as a mask to form a contact hole 24 that exposes a portion of the wiring layer 14.
この後、第８図の工程では、接続孔２４を介し
て配線層１４に接続されるような２層目の配線層
２６を形成する。 Thereafter, in the step shown in FIG. 8, a second wiring layer 26 is formed to be connected to the wiring layer 14 through the connection hole 24.
上記の方法によると、ガラス膜１８を設けて配
線段差を軽減したので、段差部における配線切れ
や配線金属のエツチング残り等を防止することが
できる。 According to the above method, since the glass film 18 is provided to reduce the wiring level difference, it is possible to prevent wiring breakage and etching residue of the wiring metal at the level difference part.
［発明が解決しようとする問題点］
上記した第７図のドライエツチング工程では、
接続孔２４の底部でエツチングが不十分となり、
第８図のように配線層２６を形成したとき配線層
１４及び２６の接続部で導通不良が発生すること
があつた。[Problems to be solved by the invention] In the dry etching process shown in FIG. 7 described above,
Etching is insufficient at the bottom of the connection hole 24,
When the wiring layer 26 was formed as shown in FIG. 8, a conduction failure sometimes occurred at the connection between the wiring layers 14 and 26.
発明者の研究によれば、かような導通不良発生
は、SOGに起因するものであることが判明した。
すなわち、SOGは、シラノール（Si（OH）4）を
有機溶剤にとかしたものであり、膜形成後にも有
機成分を含んでいるため、ドライエツチングで気
化したSOG中の炭素（Ｃ）、水素（Ｈ）等の成分
がポリマーを形成してエツチングの進行を妨げて
いるものと考えられる。 According to the inventor's research, it has been found that the occurrence of such conduction failure is caused by SOG.
In other words, SOG is made by dissolving silanol (Si(OH) 4 ) in an organic solvent, and contains organic components even after film formation, so carbon (C) and hydrogen ( It is thought that components such as H) form a polymer and hinder the progress of etching.
［問題点を解決するための手段］
この発明の目的は、上記のような導通不良の発
生を防止することにある。[Means for Solving the Problems] An object of the present invention is to prevent the occurrence of conduction failures as described above.
この発明による多層配線形成法は、
(a) 基板上に１層目の配線層を覆つてベーパー・
デポジシヨン法により第１の層間絶縁膜を形成
する工程と、
(b) 前記第１の層間絶縁膜の上に液状ガラスを塗
布して配線段差軽減用のガラス膜を形成する工
程と、
(c) 前記ガラス膜をエツチバツクすることにより
前記第１の層間絶縁膜を前記１層目の配線層の
上面に対応する部分で露呈させ且つ前記ガラス
膜を前記１層目の配線層に基づく段差部にて残
存させる工程と、
(d) 前記第１の層間絶縁膜の露呈部及び前記ガラ
ス膜の残存部を覆うようにベーパー・デポジシ
ヨン法により第２の層間絶縁膜を形成する工程
と、
(e) 前記第１及び第２の層間絶縁膜において前記
１層目の配線層の上面の一部に対応し且つ前記
ガラス膜が介在しない部分を選択的にドライエ
ツチすることにより該部分に前記１層目の配線
層に達する接続孔を形成する工程と、
(f) 前記接続孔を介して前記１層目の配線層に接
続されるように前記第２の層間絶縁膜の上に２
層目の配線層を形成する工程と
を含むものである。 The method for forming multilayer wiring according to the present invention includes: (a) covering the first wiring layer on the substrate with vapor vapor;
a step of forming a first interlayer insulating film by a deposition method; (b) a step of applying liquid glass on the first interlayer insulating film to form a glass film for reducing wiring steps; By etching back the glass film, the first interlayer insulating film is exposed at a portion corresponding to the upper surface of the first wiring layer, and the glass film is etched back at a step portion based on the first wiring layer. (d) forming a second interlayer insulating film by a vapor deposition method so as to cover the exposed portion of the first interlayer insulating film and the remaining portion of the glass film; (e) the step of forming a second interlayer insulating film by a vapor deposition method; By selectively dry etching a portion of the first and second interlayer insulating films that corresponds to a part of the upper surface of the first layer wiring layer and that does not have the glass film interposed therebetween, the first layer wiring layer is formed in the first and second interlayer insulating films. (f) forming a second interlayer insulating film on the second interlayer insulating film so as to be connected to the first wiring layer through the contact hole;
The method includes a step of forming a third wiring layer.
［作用］
この発明の方法によれば、接続孔を形成すべき
部分にガラス膜が存在しないようにしたので、ド
ライエツチングの際にＣ，Ｈ等によるポリマー生
成がなされず、スムーズにエツチングが進行す
る。このため、接続孔の底部では十分にエツチン
グが行なわれ、上下の配線層の接続部において導
通不良が生ずるのを未然に防止することができ
る。[Function] According to the method of the present invention, since no glass film is present in the area where the connection hole is to be formed, no polymer formation due to C, H, etc. occurs during dry etching, and etching proceeds smoothly. do. Therefore, sufficient etching is performed at the bottom of the contact hole, and it is possible to prevent conduction failure from occurring at the connection portion between the upper and lower wiring layers.
［実施例］
第１図乃至第５図は、この発明の一実施例によ
る多層配線形成法を示すもので、各々の図番に対
応する工程(1)〜(5)を順次に説明する。[Embodiment] FIGS. 1 to 5 show a multilayer wiring forming method according to an embodiment of the present invention, and steps (1) to (5) corresponding to each figure number will be sequentially explained.
(1) まず、シリコン等の半導体基板１０の表面に
シリコンオキサイド等の絶縁膜１２を形成した
後、その上に例えばアルミニウムを蒸着法、ス
パツタ法等により被着して適宜パターニングす
ることにより１層目の配線層１４Ａ及び１４Ｂ
を形成する。そして、CVD法等のベーパー・
デポジシヨン法により配線層１４Ａ及び１４Ｂ
をおおつて第１のPSG膜１６を形成した後、
このPSG膜１６上に回転塗布法等によりSOG
のような液状ガラスを塗布して配線段差軽減用
のガラス膜１８を形成する。(1) First, an insulating film 12 made of silicon oxide or the like is formed on the surface of a semiconductor substrate 10 made of silicon or the like, and then, for example, aluminum is deposited on the insulating film 12 by a vapor deposition method, a sputtering method, etc., and patterned appropriately. Wiring layers 14A and 14B
form. And vapor, such as CVD method.
Wiring layers 14A and 14B are formed by the deposition method.
After forming the first PSG film 16 by covering
On this PSG film 16, SOG is applied by spin coating method etc.
A glass film 18 for reducing wiring steps is formed by applying liquid glass such as the following.
(2) 次に、ドライエツチングによりガラス膜１８
を全面的にエツチバツクする。このエツチング
はガラス膜１８が配線層１４Ａ及び１４Ｂに対
応する部分でなくなる（PSG膜１６が配線層
１４Ａ及び１４Ｂの上方で露呈する）程度に行
なう。(2) Next, the glass film 18 is etched by dry etching.
We will thoroughly work on this. This etching is performed to such an extent that the glass film 18 is removed from the portions corresponding to the wiring layers 14A and 14B (PSG film 16 is exposed above the wiring layers 14A and 14B).
(3) 次に、CVD法等のベーパー・デポジシヨン
法によりPSG膜１６の露呈部及び残存ガラス
膜１８をおおつて第２のPSG膜２０を形成す
る。(3) Next, a second PSG film 20 is formed by covering the exposed portion of the PSG film 16 and the remaining glass film 18 by a vapor deposition method such as a CVD method.
(4) 次に、レジスト層２２をマスクとして配線層
１４Ａ上のPSG膜１６及び２０を選択的にド
ライエツチして接続孔２４を形成する。このと
き、エツチされる部分にはガラス膜１８が存在
しないので、ポリマー生成の原料ガスが出な
い。従つて、接続孔２４の底部では、十分にエ
ツチングが行なわれる。(4) Next, using the resist layer 22 as a mask, the PSG films 16 and 20 on the wiring layer 14A are selectively dry-etched to form a connection hole 24. At this time, since the glass film 18 is not present in the portion to be etched, no raw material gas for polymer production is released. Therefore, the bottom of the connection hole 24 is sufficiently etched.
(5) この後、基板上面に例えばアルミニウムを被
着して適宜パターニングすることにより２層目
の配線層２６を形成する。この配線層２６は、
接続孔２４を介して配線層１４Ａと接続され、
この接続部における導通状態は良好である。(5) After this, a second wiring layer 26 is formed by depositing aluminum, for example, on the upper surface of the substrate and patterning it appropriately. This wiring layer 26 is
connected to the wiring layer 14A via the connection hole 24;
The conduction state at this connection is good.
上記のように、ガラス膜１８を形成した後エツ
チバツクを行なうことで平坦化効果を損うことな
く配線層１４Ａ及び２６間に良好な導通状態を確
保することができる。 As described above, by performing etchback after forming the glass film 18, it is possible to ensure good conduction between the wiring layers 14A and 26 without impairing the planarization effect.
なお、層間絶縁膜の材料としては、PSGに限
らず、シリコンオキサイド等の適宜のものを用い
ることができる。 Note that the material for the interlayer insulating film is not limited to PSG, and any suitable material such as silicon oxide can be used.
［発明の効果］
以上のように、この発明によれば、エツチバツ
ク工程を付加するだけの簡単な手段によつて上下
の配線層間に良好な導通状態を確保することがで
き、製造歩留及び信頼性を大幅に向上しうる効果
が得られるものである。[Effects of the Invention] As described above, according to the present invention, it is possible to ensure good conduction between upper and lower wiring layers by simply adding an etch-back process, thereby improving manufacturing yield and reliability. This has the effect of significantly improving sexual performance.
第１図乃至第５図は、この発明の一実施例によ
る多層配線形成法を示す基板断面図、第６図乃至
第８図は、従来の多層配線形成法を示す基板断面
図である。
１０……半導体基板、１２……絶縁膜、１４，
１４Ａ，１４Ｂ……１層目の配線層、１６……第
１のPSG膜、１８……ガラス膜、２０……第２
のPSG膜、２２……レジスト層、２４……接続
孔、２６……２層目の配線層。
1 to 5 are cross-sectional views of a substrate showing a method for forming multilayer wiring according to an embodiment of the present invention, and FIGS. 6 to 8 are cross-sectional views of a substrate showing a conventional method for forming multilayer wiring. 10... Semiconductor substrate, 12... Insulating film, 14,
14A, 14B...first wiring layer, 16...first PSG film, 18...glass film, 20...second
PSG film, 22...resist layer, 24...connection hole, 26...second wiring layer.
Claims (1)
ー・デポジシヨン法により第１の層間絶縁膜を
形成する工程と、 (b) 前記第１の層間絶縁膜の上に液状ガラスを塗
布して配線段差軽減用のガラス膜を形成する工
程と、 (c) 前記ガラス膜をエツチバツクすることにより
前記第１の層間絶縁膜を前記１層目の配線層の
上面に対応する部分で露呈させ且つ前記ガラス
膜を前記１層目の配線層に基づく段差部にて残
存させる工程と、 (d) 前記第１の層間絶縁膜の露呈部及び前記ガラ
ス膜の残存部を覆うようにベーパー・デポジシ
ヨン法により第２の層間絶縁膜を形成する工程
と、 (e) 前記第１及び第２の層間絶縁膜において前記
１層目の配線層の上面の一部に対応し且つ前記
ガラス膜が介在しない部分を選択的にドライエ
ツチすることにより該部分に前記１層目の配線
層に達する接続孔を形成する工程と、 (f) 前記接続孔を介して前記１層目の配線層に接
続されるように前記第２の層間絶縁膜の上に２
層目の配線層を形成する工程と を含む多層配線形成法。[Scope of Claims] 1(a) forming a first interlayer insulating film on the substrate by vapor deposition, covering the first wiring layer; (b) forming the first interlayer insulating film on the substrate; (c) forming the first interlayer insulating film on the upper surface of the first wiring layer by etching back the glass film; and (c) etching back the glass film. (d) exposing the exposed portion of the first interlayer insulating film and the remaining portion of the glass film; (e) forming a second interlayer insulating film by a vapor deposition method so as to cover a part of the upper surface of the first wiring layer in the first and second interlayer insulating films; (f) forming a connection hole reaching the first wiring layer in the portion by selectively dry etching the portion where the glass film does not exist; (f) connecting the first layer wiring through the connection hole; 2 on the second interlayer insulating film so as to be connected to the second interlayer insulating film.
A multilayer wiring forming method including a step of forming a second wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13864486A JPS62295437A (en) | 1986-06-14 | 1986-06-14 | Forming method for multilayer interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13864486A JPS62295437A (en) | 1986-06-14 | 1986-06-14 | Forming method for multilayer interconnection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62295437A JPS62295437A (en) | 1987-12-22 |
| JPH0587146B2 true JPH0587146B2 (en) | 1993-12-15 |
Family
ID=15226822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13864486A Granted JPS62295437A (en) | 1986-06-14 | 1986-06-14 | Forming method for multilayer interconnection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62295437A (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6386546A (en) * | 1986-09-30 | 1988-04-16 | Pioneer Electronic Corp | Manufacture of multilayer interconnection substrate |
| JPS6386547A (en) * | 1986-09-30 | 1988-04-16 | Pioneer Electronic Corp | Manufacture of multilayer interconnection substrate |
| JPS63164342A (en) * | 1986-12-26 | 1988-07-07 | Matsushita Electric Ind Co Ltd | Formation of insulating film |
| JPH01243553A (en) * | 1988-03-25 | 1989-09-28 | Seiko Epson Corp | Manufacture of semiconductor device |
| JP2850341B2 (en) * | 1988-11-22 | 1999-01-27 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| JPH02172261A (en) * | 1988-12-25 | 1990-07-03 | Nec Corp | Manufacture of semiconductor device |
| JPH02271630A (en) * | 1989-04-13 | 1990-11-06 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH0682662B2 (en) * | 1989-07-18 | 1994-10-19 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| JPH04174541A (en) * | 1990-03-28 | 1992-06-22 | Nec Corp | Semiconductor integrated circuit and its manufacture |
| JP2820070B2 (en) * | 1995-08-11 | 1998-11-05 | 日本電気株式会社 | Plasma chemical vapor deposition and its equipment. |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5897848A (en) * | 1981-12-08 | 1983-06-10 | Seiko Instr & Electronics Ltd | Smoothing method for surface |
| JPS607737A (en) * | 1983-06-27 | 1985-01-16 | Nec Corp | Manufacture of semiconductor device |
| JPS6035535A (en) * | 1983-08-08 | 1985-02-23 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS60173856A (en) * | 1984-02-10 | 1985-09-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6165454A (en) * | 1984-09-07 | 1986-04-04 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS61116858A (en) * | 1984-10-24 | 1986-06-04 | Fujitsu Ltd | Formation of interlaminar insulating film |
-
1986
- 1986-06-14 JP JP13864486A patent/JPS62295437A/en active Granted
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5897848A (en) * | 1981-12-08 | 1983-06-10 | Seiko Instr & Electronics Ltd | Smoothing method for surface |
| JPS607737A (en) * | 1983-06-27 | 1985-01-16 | Nec Corp | Manufacture of semiconductor device |
| JPS6035535A (en) * | 1983-08-08 | 1985-02-23 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS60173856A (en) * | 1984-02-10 | 1985-09-07 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6165454A (en) * | 1984-09-07 | 1986-04-04 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS61116858A (en) * | 1984-10-24 | 1986-06-04 | Fujitsu Ltd | Formation of interlaminar insulating film |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62295437A (en) | 1987-12-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2518435B2 (en) | Multilayer wiring formation method | |
| JPH0587146B2 (en) | ||
| JPH03244126A (en) | Manufacture of semiconductor device | |
| JP4068190B2 (en) | Multilayer wiring forming method for semiconductor device | |
| JPS6360539B2 (en) | ||
| JPS62155537A (en) | Manufacture of semiconductor device | |
| JPH04330768A (en) | Manufacture of semiconductor device | |
| JPH08139185A (en) | Manufacture of semiconductor device | |
| JPH0587973B2 (en) | ||
| JPH0570301B2 (en) | ||
| JPH05347360A (en) | Multilayer interconnection structure and manufacture thereof | |
| JPS61289649A (en) | Manufacture of semiconductor device | |
| JP2537994B2 (en) | Method of forming through-hole | |
| KR0127689B1 (en) | Forming method for multi layered metal line | |
| JPS63226041A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH04326553A (en) | Manufacture of semiconductor device | |
| JPH1126575A (en) | Semiconductor device and its manufacture | |
| JPH05160126A (en) | Formation of multilayer wiring | |
| JPH0684908A (en) | Semiconductor device and its manufacturing method | |
| JPS63166248A (en) | Semiconductor integrated circuit device and manufacture thereof | |
| KR19980058383A (en) | Metal wiring formation method of semiconductor device | |
| JPS62249451A (en) | Manufacture of multilayer interconnection structure | |
| JPS6197946A (en) | Manufacture of semiconductor device | |
| JPS61280636A (en) | Manufacture of semiconductor device | |
| JPS60175439A (en) | Method for forming multilayer interconnection |