JPH0583588A - Image processor - Google Patents
Image processorInfo
- Publication number
- JPH0583588A JPH0583588A JP27334091A JP27334091A JPH0583588A JP H0583588 A JPH0583588 A JP H0583588A JP 27334091 A JP27334091 A JP 27334091A JP 27334091 A JP27334091 A JP 27334091A JP H0583588 A JPH0583588 A JP H0583588A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- video signal
- image
- video
- controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、対象物を撮像して得
られた画像を処理して認識などを実行する画像処理装置
に関連し、殊にこの発明は、トリガ信号の任意の入力タ
イミングに合わせて映像信号を出力する撮像装置が用い
られた画像処理装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for processing an image obtained by picking up an image of an object to perform recognition, and more particularly, the present invention relates to an arbitrary input timing of a trigger signal. The present invention relates to an image processing device using an imaging device that outputs a video signal in accordance with the above.
【０００２】[0002]
【従来の技術】従来のその種画像処理装置は、図３に示
すように、対象物を撮像して映像信号を出力するテレビ
カメラ２０と、前記映像信号を入力して所定の画像処理
を行うコントローラ２１と、前記映像信号にかかる画像
を表示するビデオモニタ２２とから成る。前記コントロ
ーラ２１は、Ａ／Ｄ変換器２３，画像処理部２４，表示
制御部２５，Ｄ／Ａ変換器２６，ＣＰＵ２７，ＲＯＭ２
８，ＲＡＭ２９などの各構成を含む他、同期信号生成部
３０とトリガ生成部３１とを有する。2. Description of the Related Art As shown in FIG. 3, a conventional image processing apparatus of the related art performs a predetermined image processing by inputting the video signal and a television camera 20 which picks up an image of an object and outputs a video signal. It comprises a controller 21 and a video monitor 22 for displaying an image relating to the video signal. The controller 21 includes an A / D converter 23, an image processing unit 24, a display control unit 25, a D / A converter 26, a CPU 27, and a ROM 2.
8, a RAM 29, and the like, and a sync signal generator 30 and a trigger generator 31.
【０００３】この画像処理装置に対して任意のタイミン
グで外部入力が与えられると、トリガ生成部３１は図４
(1) に示すようなトリガ信号を生成してテレビカメラ２
０へ出力し、テレビカメラ２０はこのトリガ信号の入力
タイミングに合わせてフィールドｆ１が開始する映像信
号（図４(2) に示す）をＡ／Ｄ変換器２３および同期信
号生成部３０へ出力する。前記同期信号生成部３０は、
前記映像信号に同期した同期信号を生成して表示制御部
２５へ出力し、表示制御部２５は前記同期信号に同期し
てＡ／Ｄ変換器２３からの映像信号をＤ／Ａ変換器２６
を経てビデオモニタ２２へ出力し画像を表示させる。When an external input is given to this image processing apparatus at an arbitrary timing, the trigger generation unit 31 operates as shown in FIG.
The TV camera 2 generates a trigger signal as shown in (1).
0, and the TV camera 20 outputs the video signal (shown in FIG. 4 (2)) in which the field f1 is started to the A / D converter 23 and the synchronization signal generation unit 30 at the input timing of the trigger signal. .. The sync signal generator 30 includes
A synchronization signal synchronized with the video signal is generated and output to the display control unit 25, and the display control unit 25 synchronizes the video signal from the A / D converter 23 with the D / A converter 26 in synchronization with the synchronization signal.
And is output to the video monitor 22 to display an image.
【０００４】[0004]
【発明が解決しようとする問題点】上記構成の画像処理
装置では、テレビカメラ２０より出力される映像信号
は、トリガ信号の入力タイミングに合わせてフィールド
ｆ１が開始するから、その前のフィールドｆ０の周期Ｔ
２が通常の周期Ｔ１より短くなり、その結果、ビデオモ
ニタ２２に表示される画像が乱れるという問題がある。In the image processing apparatus having the above configuration, the field f1 of the video signal output from the television camera 20 starts at the input timing of the trigger signal. Cycle T
2 becomes shorter than the normal period T1, and as a result, the image displayed on the video monitor 22 is disturbed.
【０００５】この発明は、上記問題に着目してなされた
もので、たとえトリガ信号の任意の入力タイミングに合
わせて映像信号を出力する撮像装置を用いた場合でも、
画像の表示が乱れることのない画像処理装置を提供する
ことを目的とする。The present invention has been made in view of the above problems, and even if an image pickup apparatus which outputs a video signal in synchronization with an arbitrary input timing of a trigger signal is used,
An object of the present invention is to provide an image processing device in which display of an image is not disturbed.
【０００６】[0006]
【課題を解決するための手段】この発明にかかる画像処
理装置は、トリガ信号の任意の入力タイミングに合わせ
て映像信号が出力される撮像装置と、前記映像信号を入
力して所定の画像処理を行うコントローラと、前記映像
信号にかかる画像を表示する画像表示装置とを有するも
のである。前記コントローラは、前記撮像装置が出力す
る映像信号に同期した第１の同期信号を生成する第１の
同期信号生成部と、映像信号に同期しない固定周期の第
２の同期信号を生成する第２の同期信号生成部と、第１
の同期信号により映像信号が書き込まれる画像記憶部と
を備えており、第２の同期信号により前記画像記憶部よ
り記憶画像を読み出して前記画像表示装置へ出力させる
ようになっている。SUMMARY OF THE INVENTION An image processing apparatus according to the present invention includes an image pickup apparatus which outputs a video signal at an arbitrary input timing of a trigger signal, and a predetermined image processing which receives the video signal. It has a controller for performing and an image display device for displaying an image related to the video signal. The controller includes a first synchronization signal generation unit that generates a first synchronization signal that is synchronized with a video signal output by the imaging device, and a second synchronization signal that is a second synchronization signal that has a fixed cycle and that is not synchronized with the video signal. A synchronization signal generator of the first
And an image storage unit in which a video signal is written by the synchronization signal of 1., and a stored image is read from the image storage unit by the second synchronization signal and output to the image display device.
【０００７】[0007]
【作用】画像記憶部には第１の同期信号により映像信号
がトリガ信号の入力タイミングに応じてフィールド途中
まで書き込まれるが、この画像記憶部からは第２の同期
信号により１フィールド分の映像信号が読み出される。
この読出出力は前半がフィールド途中までの映像信号に
対応し、後半はその前のフィルードにかかる映像信号に
対応するもので、この合成された映像信号間には殆ど差
異がないため、画像表示装置に表示される画像は乱れる
ことがない。According to the first synchronization signal, the video signal is written in the image storage section in the middle of the field in accordance with the input timing of the trigger signal. From the image storage section, the video signal for one field is written by the second synchronization signal. Is read.
In the read output, the first half corresponds to a video signal halfway through the field, and the second half corresponds to a video signal related to the preceding field. Since there is almost no difference between the combined video signals, the image display device The image displayed on is not disturbed.
【０００８】[0008]
【実施例】図１は、この発明の一実施例にかかる画像処
理装置の全体構成を示すもので、対象物を撮像して映像
信号を出力するテレビカメラ１と、前記映像信号を入力
して所定の画像処理を行うコントローラ２と、前記映像
信号にかかる画像を表示するビデオモニタ３とから成
る。FIG. 1 shows the overall construction of an image processing apparatus according to an embodiment of the present invention. A television camera 1 for picking up an image of an object and outputting a video signal, and an input of the video signal. It is composed of a controller 2 that performs predetermined image processing and a video monitor 3 that displays an image related to the video signal.
【０００９】前記テレビカメラ１は受光素子としてＣＣ
Ｄを内蔵したＣＣＤカメラであって、コントローラ２よ
り任意のタイミングでトリガ信号が与えられたとき、そ
のトリガ信号の入力タイミングに合わせて映像信号を出
力するものである。The television camera 1 uses CC as a light receiving element.
A CCD camera with a built-in D, which outputs a video signal in synchronization with the input timing of the trigger signal when the trigger signal is given from the controller 2 at an arbitrary timing.
【００１０】前記コントローラ２は、Ａ／Ｄ変換器４，
デュアルポートＲＡＭ（以下「ＤＰＲＡＭ」という）
５，画像処理部６，表示制御部７，Ｄ／Ａ変換器８，コ
ンピュータ制御部９，第１，第２の同期信号生成部１
０，１１，トリガ生成部１２などを構成として含んでい
る。The controller 2 includes an A / D converter 4,
Dual port RAM (hereinafter referred to as "DPRAM")
5, image processing unit 6, display control unit 7, D / A converter 8, computer control unit 9, first and second synchronization signal generation unit 1
0, 11, a trigger generation unit 12 and the like are included as components.
【００１１】前記Ａ／Ｄ変換器４は、テレビカメラ１か
らのアナログ量の映像信号をディジルタ量に変換する。
ＤＰＲＡＭ５は書込みおよび読出しのための２個のポー
トＰ１，Ｐ２をもち、１フィールド分の映像信号が記憶
される。表示制御部７は前記ＤＰＲＡＭ５より読み出さ
れた映像信号にかかる画像をビデオモニタ４に表示させ
るための制御を行う。Ｄ／Ａ変換器８は表示制御部７か
らのディジタル量の映像信号をアナログ量に変換してビ
デオモニタ４へ出力する。The A / D converter 4 converts an analog image signal from the television camera 1 into a digital amount.
The DPRAM 5 has two ports P1 and P2 for writing and reading and stores a video signal for one field. The display control unit 7 controls the video monitor 4 to display an image of the video signal read from the DPRAM 5. The D / A converter 8 converts the digital video signal from the display controller 7 into an analog video signal and outputs the analog video signal to the video monitor 4.
【００１２】コンピュータ制御部９は、制御・演算の主
体であるＣＰＵ１３を含み、このＣＰＵ１３にバス１６
を介してＲＯＭ１４およびＲＡＭ１５が接続される。Ｒ
ＯＭ９は画像処理のためのプログラムが格納され、また
ＲＡＭ８は各種データの読み書きに供される。The computer control unit 9 includes a CPU 13 which is a main body of control and calculation, and a bus 16 is connected to the CPU 13.
The ROM 14 and the RAM 15 are connected via the. R
The OM 9 stores a program for image processing, and the RAM 8 is used for reading and writing various data.
【００１３】第１の同期信号生成部１０は前記テレビカ
メラ１が出力する映像信号に同期した第１の同期信号を
生成するもので、この第１の同期信号とＡ／Ｄ変換器４
からの映像信号とをＤＰＲＡＭ５のポートＰ１へ入力
し、第１の同期信号を用いて前記映像信号がポートＰ１
よりＤＰＲＡＭ５に書き込まれる。The first sync signal generator 10 is for generating a first sync signal in synchronization with the video signal output from the television camera 1, and the first sync signal and the A / D converter 4 are used.
From the port P1 of the DPRAM 5 is input to the port P1 of the DPRAM 5 by using the first synchronizing signal.
Is written in DPRAM5.
【００１４】また第２の同期信号生成部１１は映像信号
に同期しない固定周期の第２の同期信号を生成するもの
で、この第２の同期信号をＤＰＲＡＭ５のポートＰ２へ
入力し、第２の同期信号を用いてＤＰＲＡＭ５より映像
信号がポートＰ２より読み出される。トリガ生成部１２
は、任意のタイミングの外部入力に対しトリガ信号を生
成してテレビカメラ１へ出力する。The second sync signal generator 11 is for generating a second sync signal having a fixed cycle which is not synchronized with the video signal. The second sync signal is input to the port P2 of the DPRAM 5 to generate the second sync signal. A video signal is read from the DPRAM 5 from the port P2 using the synchronization signal. Trigger generator 12
Generates a trigger signal for an external input at an arbitrary timing and outputs it to the television camera 1.
【００１５】図２は、上記画像処理装置のタイムチャー
トであって、図２（１）はトリガ生成部１２が出力する
トリガ信号を、図２（２）はテレビカメラ１が出力する
映像信号（ＤＰＲＡＭ５の入力）を、図２（３）はＤＰ
ＲＡＭ５の出力を、それぞれ示す。以下、図２のタイム
チャートに従って上記画像処理装置の動作を説明する。FIG. 2 is a time chart of the image processing apparatus. FIG. 2 (1) shows a trigger signal output from the trigger generator 12, and FIG. 2 (2) shows a video signal output from the television camera 1 ( DPRAM5 input)
The outputs of the RAM 5 are shown respectively. The operation of the image processing apparatus will be described below with reference to the time chart of FIG.
【００１６】テレビカメラ１からの映像信号は、Ａ／Ｄ
変換器４および第１の同期信号生成部１０へ出力され
る。Ａ／Ｄ変換器４はディジタル量の映像信号を、また
第１の同期信号生成部１０は映像信号に同期した第１の
同期信号を、それぞれＤＰＲＡＭ５のポートＰ１へ出力
する。ＤＰＲＡＭ５には第１の同期信号を用いて１フィ
ールド分の映像信号、例えば図２（２）におけるフィー
ルドｆ１の映像信号がＤＰＲＡＭ５に書き込まれる。こ
のフィールドｆ１の周期はＴ１である。The video signal from the TV camera 1 is A / D
It is output to the converter 4 and the first synchronization signal generator 10. The A / D converter 4 outputs the digital video signal, and the first sync signal generator 10 outputs the first sync signal synchronized with the video signal to the port P1 of the DPRAM 5, respectively. A video signal for one field, for example, a video signal for the field f1 in FIG. 2B is written in the DPRAM 5 in the DPRAM 5 by using the first synchronization signal. The cycle of this field f1 is T1.
【００１７】一方、第２の同期信号生成部１２は、映像
信号に同期しない固定周期の第２の同期信号を生成して
ＤＰＲＡＭ５のポートＰ２へ出力しており、ＤＰＲＡＭ
５からはこの第２の同期信号により前記フィールドｆ１
に対応するフィールドＦ１の映像信号が読み出される。
このフィールドＦ１の周期もＴ１である。On the other hand, the second synchronizing signal generator 12 generates a second synchronizing signal having a fixed cycle which is not synchronized with the video signal and outputs the second synchronizing signal to the port P2 of the DPRAM 5.
From the No. 5, the field f1 is generated by the second synchronization signal.
The video signal of the field F1 corresponding to is read.
The cycle of this field F1 is also T1.
【００１８】いまつぎのフィールドｆ２の映像信号を出
力する途中のタイミングでトリガ信号（図２（１）参
照）を入力したとき、テレビカメラ１は前記トリガ信号
の入力タイミングに合わせて新たなフィールドｆ３の映
像信号を出力する。このためフィールドｆ２については
ＤＰＲＡＭ５への映像信号の書込みはフィールド途中ま
でとなり、その周期Ｔ２は通常の周期Ｔ１より短いもの
となる。When a trigger signal (see FIG. 2 (1)) is input at the timing when the video signal of the next field f2 is being output, the television camera 1 newly adds a field f3 in accordance with the input timing of the trigger signal. The video signal of is output. For the field f2, therefore, the video signal is written to the DPRAM 5 halfway through the field, and the cycle T2 is shorter than the normal cycle T1.
【００１９】一方、ＤＰＲＡＭ５からの映像信号の読出
しは、映像信号に同期しない固定周期の第２の同期信号
を用いて行われるもので、このときのＤＰＲＡＭ５から
のフィールドＦ２の出力は、前半が前記フィールドｆ２
の映像信号に対応し、後半がその前のフィルードｆ１の
映像信号に対応する。このフィールドＦ２の周期はＴ１
であり、この合成された映像信号は表示制御部１７へ出
力される。この場合前記フィールドｆ２の映像信号とフ
ィルードｆ１の映像信号との間には殆ど差異がないた
め、ビデオモニタ３に表示されるフィールドＦ２にかか
る表示画像は乱れることがない。On the other hand, the reading of the video signal from the DPRAM 5 is carried out by using the second synchronizing signal having a fixed cycle which is not synchronized with the video signal. Field f2
, And the latter half corresponds to the preceding video signal of the field f1. The cycle of this field F2 is T1
The combined video signal is output to the display control unit 17. In this case, since there is almost no difference between the video signal of the field f2 and the video signal of the field f1, the display image on the field F2 displayed on the video monitor 3 is not disturbed.
【００２０】[0020]
【発明の効果】この発明は上記の如く、第１の同期信号
生成部により撮像装置が出力する映像信号に同期した第
１の同期信号を生成し、また第２の同期信号生成部によ
り映像信号に同期しない固定周期の第２の同期信号を内
部生成して、第１の同期信号により映像信号を画像記憶
部へ書き込むとともに、第２の同期信号により前記画像
記憶部より記憶画像を読み出して前記画像表示装置へ出
力させるから、たとえトリガ信号の任意の入力タイミン
グに合わせて映像信号を出力する撮像装置を用いた場合
でも、画像の表示が乱れることがなく、常に見やすい画
面が得られるという顕著な効果を奏する。As described above, according to the present invention, the first synchronizing signal generating section generates the first synchronizing signal synchronized with the video signal output from the image pickup apparatus, and the second synchronizing signal generating section generates the video signal. A second synchronizing signal having a fixed cycle which is not synchronized with the above, and a video signal is written to the image storage unit by the first synchronizing signal, and a stored image is read from the image storing unit by the second synchronizing signal, Since the image is output to the image display device, even if an image pickup device that outputs a video signal at an arbitrary input timing of a trigger signal is used, the display of the image is not disturbed and a screen that is easy to see is always obtained. Produce an effect.
【図１】この発明の一実施例にかかる画像処理装置の構
成を示すブロック図である。FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention.
【図２】図１の画像処理装置の動作を示すタイムチャー
トである。FIG. 2 is a time chart showing the operation of the image processing apparatus of FIG.
【図３】従来の画像処理装置の構成を示すブロック図で
ある。FIG. 3 is a block diagram showing a configuration of a conventional image processing apparatus.
【図４】従来の画像処理装置の動作を示すタイムチャー
トである。FIG. 4 is a time chart showing the operation of the conventional image processing apparatus.
１ テレビカメラ ２ コントローラ ３ ビデオモニタ ５ ＤＰＲＡＭ １０ 第１の同期信号生成部 １１ 第２の同期信号生成部 １２ トリガ生成部 DESCRIPTION OF SYMBOLS 1 TV camera 2 Controller 3 Video monitor 5 DPRAM 10 First synchronization signal generation unit 11 Second synchronization signal generation unit 12 Trigger generation unit
Claims (1)
わせて映像信号が出力される撮像装置と、前記映像信号
を入力して所定の画像処理を行うコントローラと、前記
映像信号にかかる画像を表示する画像表示装置とから成
る画像処理装置において、 前記コントローラは、前記撮像装置が出力する映像信号
に同期した第１の同期信号を生成する第１の同期信号生
成部と、映像信号に同期しない固定周期の第２の同期信
号を生成する第２の同期信号生成部と、第１の同期信号
により映像信号が書き込まれる画像記憶部とを備え、 第２の同期信号により前記画像記憶部より記憶画像を読
み出して前記画像表示装置へ出力させる画像処理装置。1. An image pickup apparatus which outputs a video signal at an arbitrary input timing of a trigger signal, a controller which inputs the video signal to perform a predetermined image processing, and displays an image related to the video signal. In an image processing device including an image display device, the controller includes a first synchronization signal generation unit that generates a first synchronization signal that is synchronized with a video signal output from the imaging device, and a fixed cycle that is not synchronized with the video signal. A second synchronization signal generation unit for generating a second synchronization signal and an image storage unit in which a video signal is written by the first synchronization signal, and a stored image is stored in the image storage unit by the second synchronization signal. An image processing device for reading and outputting to the image display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27334091A JPH0583588A (en) | 1991-09-24 | 1991-09-24 | Image processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27334091A JPH0583588A (en) | 1991-09-24 | 1991-09-24 | Image processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0583588A true JPH0583588A (en) | 1993-04-02 |
Family
ID=17526531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27334091A Pending JPH0583588A (en) | 1991-09-24 | 1991-09-24 | Image processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0583588A (en) |
Cited By (83)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0726498A1 (en) | 1995-02-10 | 1996-08-14 | Fuji Photo Film Co., Ltd. | Photopolymerizable composition |
| EP1577090A2 (en) | 2004-03-19 | 2005-09-21 | Fuji Photo Film Co., Ltd. | Lithographic printing plate precursor |
| EP1614537A1 (en) | 2004-07-07 | 2006-01-11 | Fuji Photo Film Co., Ltd. | Lithographic printing plate precursor and lithographic printing method |
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1991
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