JPH0577185B2 - - Google Patents
Info
- Publication number
- JPH0577185B2 JPH0577185B2 JP61037791A JP3779186A JPH0577185B2 JP H0577185 B2 JPH0577185 B2 JP H0577185B2 JP 61037791 A JP61037791 A JP 61037791A JP 3779186 A JP3779186 A JP 3779186A JP H0577185 B2 JPH0577185 B2 JP H0577185B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- film
- hole
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052782 aluminium Inorganic materials 0.000 claims description 39
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 39
- 239000004065 semiconductor Substances 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 238000002844 melting Methods 0.000 claims description 17
- 230000008018 melting Effects 0.000 claims description 16
- 239000011810 insulating material Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 9
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 239000004642 Polyimide Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 91
- 238000000034 method Methods 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000012530 fluid Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は金属多層配線構造を有する半導体装
置に関し、特に第１層目配線層のためのコンタク
ト孔と第２層目配線層を第１層目配線層に電気的
に接続するためのコンタクト孔とが同一領域に形
成される構成を有する半導体装置の配線構造に関
する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a semiconductor device having a metal multilayer wiring structure, and in particular, the present invention relates to a semiconductor device having a metal multilayer wiring structure, and in particular, contact holes for a first wiring layer and a second wiring layer are formed in a first layer. The present invention relates to a wiring structure of a semiconductor device in which a contact hole for electrically connecting to a wiring layer is formed in the same region.
［従来の技術］
近年半導体装置の高集積化が進むにつれて半導
体チツプ上に形成される素子数が増大し、応じて
配線本数も増加し、この配線が占める面積が増大
して集積度向上に対する障害となつてきている。
この障害を除去するために、配線を多層構造にし
かつ第１層配線と半導体基板表面とを電気的に接
続するためのコンタクト孔と第１層配線と第２層
配線とを電気的に接続するためのコンタクト孔と
を同一の領域に形成し配線面積の低減化を図り、
集精度を向上させる方法が行なわれてきている。[Prior Art] In recent years, as semiconductor devices have become more highly integrated, the number of elements formed on a semiconductor chip has increased, and the number of wires has also increased accordingly, and the area occupied by these wires has increased, creating an obstacle to increasing the degree of integration. It's becoming more and more common.
In order to eliminate this obstacle, the wiring is made into a multilayer structure, and a contact hole for electrically connecting the first layer wiring and the surface of the semiconductor substrate is used to electrically connect the first layer wiring and the second layer wiring. The contact hole for the wiring is formed in the same area to reduce the wiring area.
Methods have been developed to improve the collection accuracy.
第３Ａ図ないし第３Ｃ図は従来の多層配線構造
を有する半導体装置の配線形成工程を概略的に示
す断面図である。以下、第３Ａ図ないし第３Ｃ図
を参照して従来の半導体装置における配線形成工
程について説明する。 FIGS. 3A to 3C are cross-sectional views schematically showing the process of forming interconnects in a semiconductor device having a conventional multilayer interconnect structure. Hereinafter, a wiring forming process in a conventional semiconductor device will be described with reference to FIGS. 3A to 3C.
第３Ａ図について説明する。半導体回路素子
（図示せず）が形成されたシリコン半導体基板１
上にたとえばCVD法を用いてシリコ酸化膜２を
形成した後、写真製版およびエツチング技法を用
いてシリコン酸化膜２の予め定められた領域に貫
通孔（コンタクト孔）１０を形成する。次に蒸着
法あるいはスパツタリング法を用いて第１層目の
アルミニウム配線膜３を形成し、その後、第１層
目アルミニウム配線膜３を予め定められた形状に
パターニングする。このとき、第１層目アルミニ
ウム配線膜３のコンタクト孔１０領域において
は、絶縁膜であるシリコン酸化膜２の段差によ
り、段差が形成される。 FIG. 3A will be explained. Silicon semiconductor substrate 1 on which semiconductor circuit elements (not shown) are formed
After a silicon oxide film 2 is formed on the silicon oxide film 2 using, for example, the CVD method, a through hole (contact hole) 10 is formed in a predetermined region of the silicon oxide film 2 using photolithography and etching techniques. Next, a first layer aluminum wiring film 3 is formed using a vapor deposition method or a sputtering method, and then the first layer aluminum wiring film 3 is patterned into a predetermined shape. At this time, in the contact hole 10 region of the first layer aluminum wiring film 3, a step is formed due to the step of the silicon oxide film 2, which is an insulating film.
第３Ｂ図について説明する。バターニングされ
た第１層目アルミニウム配線膜３上および絶縁膜
であるシリコン酸化膜２上にたとえばCVD法を
用いてたとえばシリコン窒化膜からなる層間絶縁
膜４を形成する。次にこの層間絶縁膜４を写真製
版およびエツチング法を用いてパターニングし
て、第１層目アルミニウム配線膜３のためのコン
タクト孔１０と同一の領域に貫通孔（コンタクト
孔）１１を形成する。 FIG. 3B will be explained. An interlayer insulating film 4 made of, for example, a silicon nitride film is formed on the patterned first-layer aluminum wiring film 3 and on the silicon oxide film 2, which is an insulating film, by using, for example, a CVD method. Next, this interlayer insulating film 4 is patterned using photolithography and etching to form a through hole (contact hole) 11 in the same region as the contact hole 10 for the first layer aluminum wiring film 3.
第３Ｃ図について説明する。層間絶縁膜４およ
び貫通孔１１上の予め定められた領域に第２層目
のアルミニウム配線膜５を形成し、貫通孔１１を
介して第２層目アルミニウム配線膜５を第１層目
アルミニウム配線膜３に電気的に接続する。 FIG. 3C will be explained. A second layer aluminum wiring film 5 is formed in a predetermined area on the interlayer insulating film 4 and the through hole 11, and the second layer aluminum wiring film 5 is connected to the first layer aluminum wiring through the through hole 11. electrically connected to membrane 3;
［発明が解決しようとする問題点］
第１層配線膜と半導体基板表面とを電気的に接
続するための第１の貫通孔（コンタクト孔）と第
２配線膜を第１配線膜に電気的に接続するための
第２の貫通孔と同一の領域に設けることにより集
積度の向上を図る半導体装置においては、第１の
貫通孔領域において第１層配線膜に段差が形成さ
れるために、第２配線膜に対する第２の貫通孔の
実効的な段差が大きくなり、第２層配線膜の第２
の貫通孔領域におけるステツプカバレツジ（段差
被覆性）が悪化し、この領域において第１層アル
ミ配線膜と第２層配線膜との接触不良や第２層配
線膜のエレクトロマイグレーシヨンを通じた発
熱、断線が生じることにより半導体装置の信頼性
が損われるという問題点があつた。[Problems to be Solved by the Invention] The first through hole (contact hole) for electrically connecting the first layer wiring film and the surface of the semiconductor substrate and the second wiring film are electrically connected to the first wiring film. In a semiconductor device that aims to improve the degree of integration by providing a second through hole in the same area as the second through hole for connection to the second through hole, since a step is formed in the first layer wiring film in the first through hole area, The effective step difference of the second through hole with respect to the second wiring film becomes large, and the second
The step coverage in the through-hole region deteriorates, and in this region, heat generation occurs due to poor contact between the first layer aluminum wiring film and the second layer wiring film and electromigration of the second layer wiring film. There is a problem in that the reliability of the semiconductor device is impaired due to the occurrence of wire breakage.
それゆえ、この発明の目的は上述の問題点を除
去し、第１層配線膜と第２層配線膜との良好な電
気的接続を実現することのできる半導体装置の製
造方法を提供することである。 Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the above-mentioned problems and realize good electrical connection between a first layer wiring film and a second layer wiring film. be.
［問題点を解決するための手段］
この発明における半導体装置は、第１層配線膜
のコンタクト領域に形成される段差部を絶縁材を
用いて充填するとともにこの充填用絶縁材と配線
層との間に高融点金属層を設けたものである。[Means for Solving the Problems] In the semiconductor device of the present invention, the stepped portion formed in the contact region of the first layer wiring film is filled with an insulating material, and the filling insulating material and the wiring layer are connected to each other. A high melting point metal layer is provided in between.
［作用］
この発明における回転塗布可能な流動性絶縁物
は第１層配線膜の第１の貫通孔領域における段差
を容易に平坦化し、それにより第２層配線膜の第
２の貫通孔領域における段差被膜性を向上させ、
第１層配線膜と第２層配線膜との良好な電気的接
続を可能にする。また、充填用絶縁材と第１層配
線膜との間に形成される高融点金属膜はこの充填
材と第１層配線膜との相互作用を防止し、第１層
配線の信頼性を保証する。[Function] The spin-coatable fluid insulator of the present invention easily flattens the step in the first through-hole region of the first-layer wiring film, thereby flattening the step in the second through-hole region of the second-layer wiring film. Improved step coating properties,
This enables good electrical connection between the first layer wiring film and the second layer wiring film. In addition, the high melting point metal film formed between the filling insulating material and the first layer wiring film prevents interaction between the filling material and the first layer wiring film, ensuring the reliability of the first layer wiring. do.
［発明の実施例］
以下、この発明の一実施例を図について説明す
る。[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
第１図はこの発明の一実施例である半導体装置
のコンタクト孔領域における断面構造を概略的に
示す図である。第１図において、この発明に従う
半導体装置の第１層配線層は、シリコ酸化膜から
なる絶縁膜２上の予め定められた領域に形成さ
れ、かつ第１の貫通孔１０を介してシリコン半導
体基板１表面に電気的に接続される第１層アルミ
配線下層３ａと、第１層アルミニウム配線下層３
ａの段差部を平坦化するために充填される回転塗
布可能な流動性酸化物であるSOG（スピン・オ
ン・ガラス）膜７と、第１層アルミニウム配線下
層３ａおよびSOG膜７上に形成される平坦な第
１層アルミニウム配線上層３ｂと、SOG膜７と
アルミニウム配線層３ａ，３ｂとの間に形成さ
れ、SOG膜７とアルミニウム配線層３ａ，３ｂ
との反応を防止するための分離用高融点金属層６
とから構成される。第１層アルミニウム配線膜上
には、第１層アルミニウム配線層３ａ，３ｂおよ
び絶縁膜２上に形成され、かつ第１の貫通孔１０
上に第２の貫通孔１１を有する層間絶縁膜４と、
層間絶縁膜４上の予め定められた領域に形成さ
れ、かつ第２の貫通孔１１を介して第１層アルミ
配線上層３ｂと電気的に接続される第２層アルミ
ニウム配線層５とが設けられる。ここで、第１層
アルミニウム配線下層３ａは、通常の多層配線構
造において必要とされる膜厚の少なくとも２分の
１以上の膜厚を有し、これにより半導体基板１表
面とのコンタクト領域における配線抵抗の上昇の
防止を図つている。第１層アルミニウム配線上層
３ｂはSOG膜７上を平坦化するとともに第１層
目アルミニウム配線膜を通常の膜厚と同程度に
し、予め定められた配線抵抗を実現するために設
けられる。高融点金属層６は、SOG膜７に含ま
れるシリコン等の不純物が第１層アルミニウム配
線層３ａ，３ｂへ拡散し、第１層アルミニウム配
線層３ａ，３ｂにエレクトロマイグレーシヨンを
通じた発熱、断線などが生じないようにするため
に設けられる。 FIG. 1 is a diagram schematically showing a cross-sectional structure in a contact hole region of a semiconductor device according to an embodiment of the present invention. In FIG. 1, a first wiring layer of a semiconductor device according to the present invention is formed in a predetermined region on an insulating film 2 made of a silicon oxide film, and is connected to a silicon semiconductor substrate through a first through hole 10. a first-layer aluminum wiring lower layer 3a electrically connected to one surface; and a first-layer aluminum wiring lower layer 3
An SOG (spin-on glass) film 7, which is a fluid oxide that can be spin-coated, is filled in order to flatten the stepped portion of the first layer aluminum interconnection lower layer 3a and the SOG film 7. It is formed between the flat first layer aluminum wiring upper layer 3b, the SOG film 7 and the aluminum wiring layers 3a, 3b, and the SOG film 7 and the aluminum wiring layers 3a, 3b.
Refractory metal layer 6 for separation to prevent reaction with
It consists of On the first layer aluminum wiring film, a first through hole 10 is formed on the first layer aluminum wiring layers 3a, 3b and the insulating film 2.
an interlayer insulating film 4 having a second through hole 11 thereon;
A second aluminum wiring layer 5 is formed in a predetermined area on the interlayer insulating film 4 and is electrically connected to the first aluminum wiring upper layer 3b via the second through hole 11. . Here, the first aluminum wiring lower layer 3a has a thickness that is at least one-half or more of the film thickness required in a normal multilayer wiring structure, so that the wiring in the contact region with the surface of the semiconductor substrate 1 is This is intended to prevent resistance from increasing. The first layer aluminum wiring upper layer 3b is provided to flatten the top of the SOG film 7, make the first layer aluminum wiring film as thick as a normal film, and realize a predetermined wiring resistance. In the high melting point metal layer 6, impurities such as silicon contained in the SOG film 7 diffuse into the first aluminum wiring layers 3a and 3b, causing heat generation and disconnection in the first aluminum wiring layers 3a and 3b through electromigration. This is provided to prevent this from occurring.
第２Ａ図ないし第２Ｇ図はこの発明の一実施例
である半導体装置の製造工程を工程順に示す断面
図である。以下、第２Ａ図ないし第２Ｇ図を参照
してこの発明の一実施例である半導体装置の製造
方法について説明する。 FIGS. 2A to 2G are cross-sectional views sequentially showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2G.
第２Ａ図において、たとえばシリコンからなる
半導体基板１表面上にCVD法等を用いてシリコ
ン酸化膜などからなる絶縁膜２を形成し、次に絶
縁膜２の予め定められた領域に写真製版およびエ
ツチング法を用いて第１の貫通孔１０を形成す
る。その後、絶縁膜２および第１の貫通孔１０上
に蒸着法またはスパツタリング法を用いて第１ア
ルミニウム配線下層３ａを形成する。ここで、第
１の貫通孔１０領域における配線抵抗の上昇を防
ぐため、第１アルミニウム配線下層３ａの膜厚は
従来の第１層目アルミニウム配線膜に必要とされ
る膜厚の1/2以上にするのが望ましい。 In FIG. 2A, for example, an insulating film 2 made of a silicon oxide film or the like is formed on the surface of a semiconductor substrate 1 made of silicon using a CVD method or the like, and then photolithography and etching are performed on predetermined areas of the insulating film 2. The first through hole 10 is formed using the method. Thereafter, a first aluminum wiring lower layer 3a is formed on the insulating film 2 and the first through hole 10 using a vapor deposition method or a sputtering method. Here, in order to prevent an increase in wiring resistance in the first through hole 10 region, the film thickness of the first aluminum wiring lower layer 3a is set to be at least 1/2 of the film thickness required for the conventional first layer aluminum wiring film. It is desirable to do so.
第２Ｂ図において、第１アルミニウム配線下層
３ａ上に第１アルミニウム配線下層３ａと次に形
成されるSOG膜７とを分離するために高融点金
属層６ａをスパツタリング法またはCVD法を用
いて形成する。 In FIG. 2B, a high melting point metal layer 6a is formed on the first aluminum wiring lower layer 3a by sputtering or CVD in order to separate the first aluminum wiring lower layer 3a from the SOG film 7 to be formed next. .
第２Ｃ図において、高融点金属層６ａ上に回転
塗布法を用いて膜厚1000Å以上のSOG膜７を塗
布し、次にSOG膜７をベークして固化させる。 In FIG. 2C, an SOG film 7 having a thickness of 1000 Å or more is coated on the high melting point metal layer 6a using a spin coating method, and then the SOG film 7 is baked and solidified.
第２Ｄ図において、SOG膜７を異方性エツチ
ング法を用いてエツチバツクして第１の貫通孔１
０領域にのみ残し、第１層アルミニウム配線下層
３ａの段差を補償して平坦化する。 In FIG. 2D, the SOG film 7 is etched back using an anisotropic etching method to form the first through hole 1.
It is left only in the 0 region, and the step of the first layer aluminum wiring lower layer 3a is compensated for and flattened.
第２Ｅ図において、SOG膜７上および高融点
金属層６ａ上に再びスパツタリング法または
CVD法を用いて高融点金属膜６ｂを形成する。
この高融点金属膜６ｂはSOG膜７と次に形成さ
れる第１アルミニウム配線上層３ｂとの反応を防
止するための分離膜として設けられる。 In FIG. 2E, the SOG film 7 and the high melting point metal layer 6a are again coated by sputtering or
A high melting point metal film 6b is formed using the CVD method.
This high melting point metal film 6b is provided as a separation film to prevent reaction between the SOG film 7 and the first aluminum wiring upper layer 3b to be formed next.
第２Ｆ図において、高融点金属層６（高融点金
属膜６ａおよび６ｂ）上に第１層目アルミニウム
配線上層３ｂを蒸着法またはスパツタリング法を
用いて形成する。これにより第１層配線層は、そ
の表面が平坦化されるとともに従来の第１層目の
アルミニウム配線層との同程度の膜厚にされる。
また従来の第１層アルミニウム配線層と同一の配
線抵抗が実現される。 In FIG. 2F, a first aluminum wiring upper layer 3b is formed on the high melting point metal layer 6 (high melting point metal films 6a and 6b) using a vapor deposition method or a sputtering method. As a result, the surface of the first wiring layer is flattened, and the thickness of the first wiring layer is approximately the same as that of the conventional first aluminum wiring layer.
Furthermore, the same wiring resistance as the conventional first-layer aluminum wiring layer is achieved.
第２Ｇ図において、第１層目アルミニウム配線
下層３ａ、高融点金属層６および第１層目アルミ
ニウム配線上層３ｂを予め定められた形状にパタ
ーニングした後、たとえばCVD法を用いて層間
絶縁膜４を形成する。その後、層間絶縁膜４の予
め定められた領域、すなわち第１のコンタクト孔
１０と平面的に見て重なり合う領域に第２の貫通
孔１１を写真製版およびエツチング法を用いて形
成する。この絶縁膜４および第２の貫通孔１１上
に第２層目アルミニウム配線膜を形成することに
より、第１図に示される多層配線構造を有する半
導体装置が得られる。 In FIG. 2G, after patterning the first aluminum wiring lower layer 3a, the refractory metal layer 6, and the first aluminum wiring upper layer 3b into a predetermined shape, the interlayer insulating film 4 is formed using, for example, a CVD method. Form. Thereafter, a second through hole 11 is formed in a predetermined region of the interlayer insulating film 4, that is, a region overlapping the first contact hole 10 in plan view, using photolithography and etching. By forming a second layer aluminum wiring film on the insulating film 4 and the second through hole 11, a semiconductor device having the multilayer wiring structure shown in FIG. 1 is obtained.
なお、上記実施例において配線材料をアルミニ
ウムとした場合について説明しているが、これに
限定されずたとえばアルミニウム合金を用いた場
合においても同様の効果を得ることができる。 In the above embodiments, a case where aluminum is used as the wiring material is described, but the present invention is not limited to this, and similar effects can be obtained even when an aluminum alloy is used, for example.
また第１層目配線膜の段差を充填するための絶
縁性材料としてSOG膜を用いた場合について説
明しているが、ポリイミドなどの流動性絶縁物を
用いて充填しても上記実施例と同様の効果を得る
ことができる。 In addition, although the case where an SOG film is used as an insulating material to fill the steps of the first layer wiring film is described, the filling using a fluid insulating material such as polyimide is similar to the above embodiment. effect can be obtained.
［発明の効果］
以上のように、この発明によれば、第１層目配
線膜に形成される段差を絶縁物を用いて充填する
ことにより平坦化しているので、第２層目配線膜
を第１層目配線膜に接続するための第２の貫通孔
領域における段差被覆性が向上し、第１層目配線
膜と第２層目配線膜との確実な電気的接続を実現
することができ、信頼度の高い半導体装置を得る
ことができる。さらに、充填用絶縁物を第１層目
配線膜との間には高融点金属層が設けられている
ため、この絶縁材と第１層目配線膜との間の相互
作用が確実に防止され、第１層目配線膜の信頼性
が保証される。[Effects of the Invention] As described above, according to the present invention, the steps formed in the first layer wiring film are flattened by filling them with an insulating material, so that the second layer wiring film is flattened. The step coverage in the second through-hole region for connection to the first layer wiring film is improved, and a reliable electrical connection between the first layer wiring film and the second layer wiring film can be realized. Therefore, a highly reliable semiconductor device can be obtained. Furthermore, since a high melting point metal layer is provided between the filling insulator and the first layer wiring film, interaction between this insulating material and the first layer wiring film is reliably prevented. , the reliability of the first layer wiring film is guaranteed.
第１図はこの発明の一実施例である多層配線構
造を有する半導体装置のコンタクト孔（貫通孔）
領域における概略断面構造を示す図である。第２
Ａ図ないし第２Ｇ図はこの発明の一実施例である
多層配線構造を有する半導体装置の製造工程を工
程順に示した概略断面図である。第３Ａ図ないし
第３Ｃ図は従来の多層配線構造を有する半導体装
置の製造工程を工程順に示す断面図である。
図において、１は半導体基板、２は絶縁膜、
３，３ａ，３ｂは第１層目配線膜、４は層間絶縁
膜、５は第２層目配線膜、６，６ａ，６ｂは高融
点金属膜、７は回転塗布可能な流動性絶縁物層、
１０は第１の貫通孔、１１は第２の導通孔であ
る。なお、図中、同一符号は同一または相当部分
を示す。
FIG. 1 shows a contact hole (through hole) of a semiconductor device having a multilayer wiring structure, which is an embodiment of the present invention.
FIG. 3 is a diagram showing a schematic cross-sectional structure in a region. Second
FIGS. A to 2G are schematic cross-sectional views sequentially showing the manufacturing process of a semiconductor device having a multilayer wiring structure according to an embodiment of the present invention. FIGS. 3A to 3C are cross-sectional views sequentially showing the manufacturing process of a conventional semiconductor device having a multilayer wiring structure. In the figure, 1 is a semiconductor substrate, 2 is an insulating film,
3, 3a, and 3b are first-layer wiring films, 4 is an interlayer insulating film, 5 is a second-layer wiring film, 6, 6a, and 6b are high-melting point metal films, and 7 is a fluid insulating layer that can be spin-coated. ,
10 is a first through hole, and 11 is a second through hole. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
体基板表面上に達する第１の貫通孔を有する第１
の絶縁膜、 前記第１の絶縁膜上および前記第１の貫通孔部
に形成される第１の配線層、 少なくとも前記第１の貫通孔部において前記第
１の配線層上に形成される第１の高融点金属層、 前記第１の貫通孔部において前記第１の高融点
金属層上に前記第１の貫通孔の段差を充填するよ
うに形成される絶縁物質、 前記第１の高融点金属層および前記絶縁物質上
に形成される第２の高融点金属層、 前記第２高融点金属層上に形成される第２の配
線層、 前記第１の配線層および前記第２の配線層上に
形成され、かつ前記第１の貫通孔と平面図的に見
て重なり合う領域上に前記第２配線層に達する第
２の貫通孔を有する第２の絶縁層、および 前記第２の絶縁層上および前記第２の貫通孔部
に形成される第３の配線層を備える、半導体装
置。 ２ 前記絶縁物質は、回転塗布可能な絶縁物質に
より構成される、特許請求の範囲第１項記載の半
導体装置。 ３ 前記回転塗布可能な絶縁物質はスピン・オ
ン・ガラスである、特許請求の範囲第２項記載の
半導体装置。 ４ 前記第１、第２および第３の配線層はアルミ
ニウムまたはアルミニウム合金層により構成され
る、特許請求の範囲第１項ないし第３項のいずれ
かに記載の半導体装置。 ５ 前記絶縁物質はポリイミドである、特許請求
の範囲第１項、第２項、および第４項のいずれか
に記載の半導体装置。[Scope of Claims] 1. A first through hole formed on a surface of a semiconductor substrate and having a first through hole reaching the surface of the semiconductor substrate.
an insulating film, a first wiring layer formed on the first insulating film and in the first through hole, and a first wiring layer formed on the first wiring layer at least in the first through hole. 1 high melting point metal layer; an insulating material formed on the first high melting point metal layer in the first through hole portion so as to fill the step of the first through hole; the first high melting point metal layer; a second high melting point metal layer formed on the metal layer and the insulating material; a second wiring layer formed on the second high melting point metal layer; the first wiring layer and the second wiring layer. a second insulating layer formed thereon and having a second through hole reaching the second wiring layer on a region overlapping with the first through hole in plan view; and the second insulating layer. A semiconductor device comprising a third wiring layer formed above and in the second through-hole section. 2. The semiconductor device according to claim 1, wherein the insulating material is comprised of an insulating material that can be spin coated. 3. The semiconductor device according to claim 2, wherein the spin-coatable insulating material is spin-on glass. 4. The semiconductor device according to any one of claims 1 to 3, wherein the first, second, and third wiring layers are made of aluminum or an aluminum alloy layer. 5. The semiconductor device according to any one of claims 1, 2, and 4, wherein the insulating material is polyimide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3779186A JPS62194647A (en) | 1986-02-20 | 1986-02-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3779186A JPS62194647A (en) | 1986-02-20 | 1986-02-20 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62194647A JPS62194647A (en) | 1987-08-27 |
| JPH0577185B2 true JPH0577185B2 (en) | 1993-10-26 |
Family
ID=12507314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3779186A Granted JPS62194647A (en) | 1986-02-20 | 1986-02-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62194647A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62281451A (en) * | 1986-05-30 | 1987-12-07 | Fujitsu Ltd | Semiconductor device |
| JPH0279447A (en) * | 1988-09-14 | 1990-03-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0373531A (en) * | 1989-08-14 | 1991-03-28 | Nec Corp | Manufacture of semiconductor device provided with multilayer wiring structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6213050A (en) * | 1985-07-10 | 1987-01-21 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1986
- 1986-02-20 JP JP3779186A patent/JPS62194647A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6213050A (en) * | 1985-07-10 | 1987-01-21 | Matsushita Electronics Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62194647A (en) | 1987-08-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5707894A (en) | Bonding pad structure and method thereof | |
| US5703408A (en) | Bonding pad structure and method thereof | |
| US5756396A (en) | Method of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect | |
| KR100342897B1 (en) | Semiconductor device and method for manufacturing the same | |
| USRE39932E1 (en) | Semiconductor interconnect formed over an insulation and having moisture resistant material | |
| JP4125485B2 (en) | Novel passivation structure and manufacturing method thereof | |
| JPH08330505A (en) | Integrated circuit interconnection part | |
| TWI344685B (en) | An integrated circuit device and a process for forming the same | |
| JPH0577185B2 (en) | ||
| US6703286B1 (en) | Metal bond pad for low-k inter metal dielectric | |
| JPH04355951A (en) | Semiconductor device and manufacture thereof | |
| JP2988943B2 (en) | Method of forming wiring connection holes | |
| KR100211956B1 (en) | Multi- metal wiring structure & method for manufacturing the same | |
| JPH02183536A (en) | Semiconductor device | |
| JP3391447B2 (en) | Method for manufacturing semiconductor device | |
| JP2779186B2 (en) | Method for manufacturing semiconductor device | |
| JPH10173051A (en) | Wiring forming method | |
| JP3210462B2 (en) | Method for manufacturing semiconductor device | |
| JP2001244268A (en) | Integrated circuit | |
| KR19990061060A (en) | Contact formation method of semiconductor device | |
| JPH04255247A (en) | Manufacture of semiconductor device | |
| JPH08274164A (en) | Semiconductor device | |
| JPH05259293A (en) | Semiconductor device and manufacture thereof | |
| JPH01241845A (en) | Manufacture of semiconductor device | |
| JPS60180143A (en) | Semiconductor device |