JPH0574951A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0574951A JPH0574951A JP23754591A JP23754591A JPH0574951A JP H0574951 A JPH0574951 A JP H0574951A JP 23754591 A JP23754591 A JP 23754591A JP 23754591 A JP23754591 A JP 23754591A JP H0574951 A JPH0574951 A JP H0574951A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- wiring
- film
- via hole
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に下部配線層と上部配線層とを接続するビアホ
ールの形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a via hole connecting a lower wiring layer and an upper wiring layer.
【０００２】[0002]
【従来の技術】従来の多層配線構造の形成方法を、図２
に示す断面図を用いて説明する。2. Description of the Related Art A conventional method for forming a multilayer wiring structure is shown in FIG.
This will be described with reference to the sectional view shown in FIG.
【０００３】まず、半導体基板２１上にフィールド酸化
膜２２，ゲート酸化膜２３，ゲート配線２４等を形成
し、これらを覆う第１の層間絶縁膜２５を形成する。ス
パッタ法により、第１の層間絶縁膜２５上に第１のＡｌ
膜を被着した後、ホトレジスト２８をマスクにして第１
のＡｌ膜をパターニングし、第１のＡｌ配線２６を形成
する〔図２（ａ）〕。次に、ホトレジスト２８を除去
し、全面に第２の層間絶縁膜２９を被着した後、ビアホ
ール形成のためにホトレジストを塗布し、露光，現像を
行ない、所望のパターンを有するホトレジスト３０を形
成する〔図２（ｂ）〕。次に、ホトレジスト３０をマス
クとして、等方性エッチング，および異方性エッチング
を行ない、ビアホール３１の形成する〔図２（ｃ）〕。
ホトレジスト３０を除去した後、ビアホール３１を含む
第２の層間絶縁膜２９上に第２のＡｌ配線３２を形成
し、ビアホール３１を介して第１のＡｌ配線２６の第２
のＡｌ配線３２とを接続する〔図２（ｄ）〕。First, a field oxide film 22, a gate oxide film 23, a gate wiring 24, etc. are formed on a semiconductor substrate 21, and a first interlayer insulating film 25 covering them is formed. The first Al is formed on the first interlayer insulating film 25 by the sputtering method.
After depositing the film, the photoresist 28 is used as a mask for the first
The Al film is patterned to form the first Al wiring 26 [FIG. 2 (a)]. Next, after removing the photoresist 28 and depositing a second interlayer insulating film 29 on the entire surface, a photoresist is applied for forming a via hole, and exposure and development are performed to form a photoresist 30 having a desired pattern. [FIG. 2 (b)]. Next, using the photoresist 30 as a mask, isotropic etching and anisotropic etching are performed to form a via hole 31 [FIG. 2 (c)].
After removing the photoresist 30, a second Al wiring 32 is formed on the second interlayer insulating film 29 including the via hole 31, and the second Al wiring 26 of the first Al wiring 26 is formed through the via hole 31.
To the Al wiring 32 of FIG. 2 (FIG. 2 (d)).
【０００４】[0004]
【発明が解決しようとする課題】上述した従来の多層配
線の形成方法では、Ａｌ金属表面の光の反射率が約８０
％と大きいため、ホトレジストが反射光により感光し、
図２（ａ）に示した工程においても、第１のＡｌ配線２
６を設計寸法どうりに形成することが困難である。と同
時に、下地が段差部になっている上にビアホール３１を
形成する場合、図２（ｂ）に示すように、ホトレジスト
３０に第１のＡｌ配線２６からの反射光により感光した
ホトレジスト３０ａが形成される。ホトレジスト３０ａ
は現像段階では多少除去されても完全に除去されない。
しかし、ホトレジスト３０ａは、層間絶縁膜２９のエッ
チング段階で除去される。その結果、図２（ｃ）に示す
ように、ビアホール３１の出来上り寸法ｄ2 は設計寸法
ｄ1 に比べて非常に大きくなる。第１のＡｌ配線２６と
ビアホール３１との設計上のマージンをｄ3 とすると、
ｄ1 ＋ｄ3 ＜ｄ2 の場合には、図示したようにビアホー
ル３１が第１のＡｌ配線２６からはみだしてしまいとい
う欠点がある。In the above-mentioned conventional method for forming a multi-layer wiring, the light reflectance of the Al metal surface is about 80.
%, So the photoresist is exposed to reflected light,
Also in the process shown in FIG. 2A, the first Al wiring 2
It is difficult to form 6 in the designed size. At the same time, when the via hole 31 is formed on the underlying layer having a stepped portion, as shown in FIG. 2B, the photoresist 30a is formed on the photoresist 30 by being exposed to the reflected light from the first Al wiring 26. To be done. Photoresist 30a
Is not completely removed in the developing stage even if it is removed to some extent.
However, the photoresist 30a is removed in the step of etching the interlayer insulating film 29. As a result, as shown in FIG. 2C, the finished dimension d 2 of the via hole 31 becomes much larger than the design dimension d 1 . If the design margin between the first Al wiring 26 and the via hole 31 is d 3 ,
When d 1 + d 3 <d 2 , there is a drawback that the via hole 31 protrudes from the first Al wiring 26 as shown in the figure.
【０００５】よって、従来の製造方法では、下地段差部
上に設計寸法どうりのビアホール３１を開口することは
困難であり、ホトレジスト３０の形成工程における露光
時の反射の影響の少ない下地平坦部上にビアホール３１
を開口するか、もしくはビアホール３１が設計寸法ｄ1
より大きく開口しても第１のＡｌ配線２６からビアホー
ル３１がはずれないようにマージンｄ3 を充分大きくす
る（ｄ1 ＋ｄ3 ＞ｄ2 ）等設計基準に制約を設ける必要
があり、集積化，微細化が困難になるという問題点があ
った。Therefore, according to the conventional manufacturing method, it is difficult to open the via hole 31 having the designed size on the underlying step portion, and the underlying flat portion is less affected by the reflection during the exposure in the process of forming the photoresist 30. Beer hole 31
Or the via hole 31 has a design dimension d 1
In order to prevent the via hole 31 from coming off the first Al wiring 26 even if the opening is made larger, it is necessary to limit the design criteria such as sufficiently increasing the margin d 3 (d 1 + d 3 > d 2 ). There is a problem in that miniaturization becomes difficult.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体装置の多層配線構造の形成工程におい
て、半導体基板上に、絶縁膜を介して導電体膜を被着す
る工程と、導電体膜上に、窒化チタン膜を被着する工程
と、窒化チタン膜上に第１のホトレジストを塗布し、該
ホトレジストを所望のパターンに露光，現像する工程
と、第１のホトレジストをマスクとして、窒化チタン
膜，および導電体膜をエッチングし、下部配線層を形成
する工程と、下部配線層上に、層間絶縁膜を形成する工
程と、層間絶縁膜上に、第２のホトレジストを塗布し、
該ホトレジストを所望のパターンに露光，現像する工程
と、第２のホトレジストをマスクとして、層間絶縁膜を
エッチングし、下部配線層に達するビアホールを形成す
る工程と、ビアホールを含む層間絶縁膜上に上部配線層
を形成し、該ビアホールを介して上部配線層と下部配線
層とを接続する工程と、を含んでいる。According to a method of manufacturing a semiconductor device of the present invention, in a step of forming a multilayer wiring structure of a semiconductor device, a step of depositing a conductor film on a semiconductor substrate via an insulating film, A step of depositing a titanium nitride film on the conductor film, a step of applying a first photoresist on the titanium nitride film, exposing and developing the photoresist to a desired pattern, and using the first photoresist as a mask. Etching the titanium nitride film and the conductor film to form a lower wiring layer, forming an interlayer insulating film on the lower wiring layer, and applying a second photoresist on the interlayer insulating film. ,
A step of exposing and developing the photoresist to a desired pattern; a step of etching the interlayer insulating film using the second photoresist as a mask to form a via hole reaching the lower wiring layer; and an upper step on the interlayer insulating film including the via hole. Forming a wiring layer, and connecting the upper wiring layer and the lower wiring layer through the via hole.
【０００７】[0007]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の第１の実施例の工程順の断面図であ
る。The present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views in the order of steps of a first embodiment of the present invention.
【０００８】まず、半導体基板１上にフィールド酸化膜
２，ゲート酸化膜３，ゲート配線４等を形成し、これら
を覆う第１の層間絶縁膜５を形成する。スパッタ法によ
り、第１の層間絶縁膜５上に第１のＡｌ膜，および３０
ｎｍ程度の膜厚の反射防止用の窒化チタン膜を被着した
後、ホトレジスト８をマスクにして窒化チタン膜，第１
のＡｌ膜をパターニングし、第１のＡｌ配線６，窒化チ
タン膜７を形成する〔図１（ａ）〕。ここでは、窒化チ
タン膜の存在により、第１のＡｌ配線６は設計寸法どう
りにパターニングされる。本実施例における露光はＧ線
（波長４３５．８ｎｍ）により行なったが、Ｇ線に対す
る窒化チタン膜の反射率は５％未満である。First, a field oxide film 2, a gate oxide film 3, a gate wiring 4, etc. are formed on a semiconductor substrate 1, and a first interlayer insulating film 5 covering them is formed. The first Al film, and 30 are formed on the first interlayer insulating film 5 by the sputtering method.
After depositing an antireflection titanium nitride film having a film thickness of about nm, the photoresist 8 is used as a mask to form the titanium nitride film,
The Al film is patterned to form the first Al wiring 6 and the titanium nitride film 7 [FIG. 1 (a)]. Here, the presence of the titanium nitride film causes the first Al wiring 6 to be patterned according to the design dimension. Although the exposure in this embodiment was performed by G line (wavelength 435.8 nm), the reflectance of the titanium nitride film with respect to G line is less than 5%.
【０００９】次に、ホトレジスト８を除去し、第１のＡ
ｌ配線６および窒化チタン膜７を含む第１の層間絶縁膜
５上に第２の層間絶縁膜９を被着する。０．８μｍ□程
度のビアホール形成のためにホトレジストを塗布し、露
光，現像を行ない、所望のパターンを有するホトレジス
ト１０を形成する〔図１（ｂ）〕。この露光時の光は前
述のＧ線を用いるため、窒化チタン膜７の存在により第
１のＡｌ配線６からの反射光の影響は無く、設計値どう
りのビアホールパターンを有するホトレジスト１０が得
られる。Next, the photoresist 8 is removed, and the first A
A second interlayer insulating film 9 is deposited on the first interlayer insulating film 5 including the 1 wiring 6 and the titanium nitride film 7. A photoresist is applied to form a via hole of about 0.8 μm □, exposed and developed to form a photoresist 10 having a desired pattern [FIG. 1 (b)]. Since the light at the time of this exposure uses the above-mentioned G line, there is no influence of the reflected light from the first Al wiring 6 due to the presence of the titanium nitride film 7, and the photoresist 10 having the via hole pattern of the designed value can be obtained. ..
【００１０】次に、ホトレジスト１０をマスクにして、
第２の層間絶縁膜９の等方性エッチング，および異方性
エッチングを行ない、ビアホール１１を形成する。この
エッチング工程における異方性エッチングのオーバーエ
ッチングにより、窒化チタン膜７はビアホール部のみエ
ッチング除去される〔図１（ｃ）〕。Next, using the photoresist 10 as a mask,
The via hole 11 is formed by performing isotropic etching and anisotropic etching of the second interlayer insulating film 9. By the overetching of the anisotropic etching in this etching step, the titanium nitride film 7 is etched and removed only in the via hole portion [FIG. 1 (c)].
【００１１】次に、ホトレジスト１０を除去した後、ビ
アホール１１を含む第２の層間絶縁膜９上に第２のＡｌ
配線１２を形成し、ビアホール１１を介して第１のＡｌ
配線６の第２のＡｌ配線１２とを接続する〔図１
（ｄ）〕。Next, after removing the photoresist 10, a second Al is formed on the second interlayer insulating film 9 including the via hole 11.
The wiring 12 is formed, and the first Al is formed through the via hole 11.
Connect the second Al wiring 12 of the wiring 6 [FIG.
(D)].
【００１２】次に、本発明の第２の実施例について説明
する。本実施例では、下層配線としてＡｌ金属膜の代り
にタングステンシリサイド膜を用いる。反射防止膜とし
て窒化チタン膜を採用することを含めて、下層配線材料
以外は構成材料および製造方法が第１の実施例と同じで
ある。Next, a second embodiment of the present invention will be described. In this embodiment, a tungsten silicide film is used as the lower wiring instead of the Al metal film. Except for the lower layer wiring material, the constituent materials and manufacturing method are the same as in the first embodiment, including the use of a titanium nitride film as the antireflection film.
【００１３】この場合、タングステンシリサイドのＧ線
に対する反射率はＡｌの反射率（８０％）に比較して５
０％と低い。そこで、タングステンシリサイド膜から配
線パターンを形成するに際し、従来と同様にタングステ
ン膜上に直接ホトレジストパターンを設けて行なうと、
フィールド酸化膜段差上やゲート配線段差上で配線パタ
ーンが細くなる。微細配線構造が採用されている昨今で
は、少しの細りでも配線の断線につながる。In this case, the reflectance of the tungsten silicide with respect to the G line is 5 as compared with the reflectance of Al (80%).
It is as low as 0%. Therefore, when forming a wiring pattern from a tungsten silicide film, if a photoresist pattern is directly provided on the tungsten film as in the conventional case,
The wiring pattern becomes thin on the step of the field oxide film and the step of the gate wiring. In recent years, where fine wiring structures have been adopted, even a small amount of wiring leads to disconnection of wiring.
【００１４】本実施例では、タングステンシリサイド膜
上に窒化チタン膜を形成しておくことにより、タングス
テンシリサイドからなる下層配線の形成加工工程におい
て、下地段差部の形状に起因する露光時の反射光の影響
を無くし、設計寸法どうりの下層配線が得られる。ま
た、タングステンシリサイドからなる下層配線と上層配
線（Ａｌ膜からなる）とを接続するビアホール形成のた
めのホトリソグラフィ工程においても、タングステンシ
リサイド配線表面からの反射光の影響は抑制され、設計
寸法どうりのビアホールパターンが得られる。In this embodiment, by forming a titanium nitride film on the tungsten silicide film, the reflected light at the time of exposure due to the shape of the underlying step portion is formed in the process of forming the lower wiring made of tungsten silicide. The influence can be eliminated, and the lower layer wiring according to the design size can be obtained. Also, in the photolithography process for forming the via hole that connects the lower layer wiring made of tungsten silicide and the upper layer wiring (made of Al film), the influence of the reflected light from the surface of the tungsten silicide wiring is suppressed, and the design size is changed. A via hole pattern is obtained.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、設計寸法
どうりの配線を形成できるとともに、ビアホール形成時
のホトリソグラフィ工程における露光時の反射光を下層
配線表面に形成した窒化チタン膜により防止するため、
下地段差部上にある下層配線の部分にビアホールを開口
しても設計寸法どうりのビアホールが得られ、下層配線
とビアホールとのマージン（図１（ｃ）におけるｄ）も
従来の値より小さくすることが可能となり、集積化，微
細化が容易になるという効果がある。As described above, according to the present invention, a wiring having a design dimension can be formed, and the reflected light at the time of exposure in the photolithography process at the time of forming a via hole is prevented by the titanium nitride film formed on the surface of the lower wiring. In order to
Even if a via hole is opened in the lower layer wiring on the underlying step, a via hole having a design size can be obtained, and the margin between the lower layer wiring and the via hole (d in FIG. 1C) is also made smaller than the conventional value. Therefore, there is an effect that integration and miniaturization are facilitated.
【図１】本発明の第１の実施例の工程順断面図である。1A to 1D are cross-sectional views in order of the processes of a first embodiment of the present invention.
【図２】従来の半導体装置の製造方法を示す工程順断面
図である。2A to 2D are cross-sectional views in order of the steps, showing a conventional method for manufacturing a semiconductor device.
１，２１ 半導体基板 ２，２２ フィールド酸化膜 ３，２３ ゲート酸化膜 ４，２４ ゲート配線 ５，２５ 第１の層間絶縁膜 ６，２６ 第１のＡｌ配線 ７ 窒化チタン膜 ８，１０，２８，３０，３０ａ ホトレジスト ９，２９ 第２の層間絶縁膜 １１，３１ ビアホール １２，３２ 第２のＡｌ配線 1, 21 Semiconductor substrate 2, 22 Field oxide film 3, 23 Gate oxide film 4, 24 Gate wiring 5, 25 First interlayer insulating film 6, 26 First Al wiring 7 Titanium nitride film 8, 10, 28, 30 , 30a Photoresist 9,29 Second interlayer insulating film 11,31 Via hole 12,32 Second Al wiring
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 // Ｈ０１Ｌ 21/28 ３０１ Ｌ 7738−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location // H01L 21/28 301 L 7738-4M
Claims (2)
おいて、 半導体基板上に、絶縁膜を介して導電体膜を被着する工
程と、 前記導電体膜上に、窒化チタン膜を被着する工程と、 前記窒化チタン膜上に第１のホトレジストを塗布し、該
ホトレジストを所望のパターンに露光，現像する工程
と、 前記第１のホトレジストをマスクとして、前記窒化チタ
ン膜，および前記導電体膜をエッチングし、下部配線層
を形成する工程と、 前記下部配線層上に、層間絶縁膜を形成する工程と、 前記層間絶縁膜上に、第２のホトレジストを塗布し、該
ホトレジストを所望のパターンに露光，現像する工程
と、 前記第２のホトレジストをマスクとして、前記層間絶縁
膜をエッチングし、前記下部配線層に達するビアホール
を形成する工程と、 前記ビアホールを含む前記層間絶縁膜上に上部配線層を
形成し、該ビアホールを介して前記上部配線層と前記下
部配線層とを接続する工程と、 を含むことを特徴とする半導体装置の製造方法。1. A step of forming a multilayer wiring structure of a semiconductor device, a step of depositing a conductor film on a semiconductor substrate via an insulating film, and a step of depositing a titanium nitride film on the conductor film. A step of applying a first photoresist on the titanium nitride film, exposing and developing the photoresist to a desired pattern, and using the first photoresist as a mask, the titanium nitride film and the conductor film To form a lower wiring layer, a step of forming an interlayer insulating film on the lower wiring layer, a second photoresist is applied on the interlayer insulating film, and the photoresist is formed into a desired pattern. Exposing and developing the photoresist, and using the second photoresist as a mask to etch the interlayer insulating film to form a via hole reaching the lower wiring layer. The interlayer insulating the upper wiring layer is formed on the film, a method of manufacturing a semiconductor device characterized by comprising the a step of connecting the lower wiring layer and the upper wiring layer through the via hole including.
露光が、Ｇ線により行なわれることを特徴とする請求項
１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the exposure of the first and second photoresists is performed by G line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23754591A JPH0574951A (en) | 1991-09-18 | 1991-09-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23754591A JPH0574951A (en) | 1991-09-18 | 1991-09-18 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0574951A true JPH0574951A (en) | 1993-03-26 |
Family
ID=17016919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23754591A Pending JPH0574951A (en) | 1991-09-18 | 1991-09-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0574951A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102011003933A1 (en) | 2010-02-12 | 2012-01-19 | Suzuki Motor Corporation | Fuel gas supply device for a vehicle engine |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01255250A (en) * | 1988-04-05 | 1989-10-12 | Fujitsu Ltd | Forming method for multilayer interconnection |
| JPH02271631A (en) * | 1989-04-13 | 1990-11-06 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH02312235A (en) * | 1989-05-26 | 1990-12-27 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1991
- 1991-09-18 JP JP23754591A patent/JPH0574951A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01255250A (en) * | 1988-04-05 | 1989-10-12 | Fujitsu Ltd | Forming method for multilayer interconnection |
| JPH02271631A (en) * | 1989-04-13 | 1990-11-06 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH02312235A (en) * | 1989-05-26 | 1990-12-27 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102011003933A1 (en) | 2010-02-12 | 2012-01-19 | Suzuki Motor Corporation | Fuel gas supply device for a vehicle engine |
| DE102011003933B4 (en) | 2010-02-12 | 2019-06-19 | Suzuki Motor Corporation | Fuel gas supply device for a vehicle engine |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6136679A (en) | Gate micro-patterning process | |
| JPH09251988A (en) | Intermediate layer lithography method for removing part of intermediate layer | |
| JPH08255752A (en) | Semiconductor element with low reflectance coating and its preparation | |
| JPH03156927A (en) | Pattern formation of alumina metallization | |
| KR100434133B1 (en) | Texas instruments incorporated | |
| US6051369A (en) | Lithography process using one or more anti-reflective coating films and fabrication process using the lithography process | |
| JP2002093904A (en) | Method for forming dual damascene wiring | |
| JPH07201986A (en) | Manufacture of semiconductor device | |
| US6017816A (en) | Method of fabricating A1N anti-reflection coating on metal layer | |
| JPH0574951A (en) | Manufacture of semiconductor device | |
| JPH08279488A (en) | Fabrication of semiconductor device | |
| JPH07307333A (en) | Pattern forming method | |
| JPH07201990A (en) | Pattern forming method | |
| JP3032089B2 (en) | Photomask forming method | |
| US5897376A (en) | Method of manufacturing a semiconductor device having a reflection reducing film | |
| JPH08330249A (en) | Manufacture of semiconductor device | |
| US6451706B1 (en) | Attenuation of reflecting lights by surface treatment | |
| JP2569709B2 (en) | Wiring formation method | |
| JPH04144230A (en) | Semiconductor device and its manufacture | |
| JPH0555130A (en) | Production of semiconductor device | |
| JPH07130741A (en) | Production of semiconductor device | |
| KR100309133B1 (en) | Method for manufacturing metal interconnection of semiconductor device | |
| JPH09232233A (en) | Intermediate layer lithography method for contracting upper layer | |
| KR20010003687A (en) | Improved dual damascene process in semiconductor device | |
| JP2000040739A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980224 |