JPH0574767A - Wiring pattern structure - Google Patents

Wiring pattern structure

Info

Publication number
JPH0574767A
JPH0574767A JP23632791A JP23632791A JPH0574767A JP H0574767 A JPH0574767 A JP H0574767A JP 23632791 A JP23632791 A JP 23632791A JP 23632791 A JP23632791 A JP 23632791A JP H0574767 A JPH0574767 A JP H0574767A
Authority
JP
Japan
Prior art keywords
wiring pattern
resin
substrate
metal
metal particles
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23632791A
Other languages
Japanese (ja)
Inventor
Yasuo Yamazaki
康男 山▲崎▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP23632791A priority Critical patent/JPH0574767A/en
Publication of JPH0574767A publication Critical patent/JPH0574767A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable a wiring pattern which is arranged in fine pitch on a substrate or a semiconductor element to be provided at a low cost. CONSTITUTION:A resin 2 where metal particles 3 are uniformly dispersed is patterned, the patterned resin 2 is plated, and a metal film 4 is made to grow making metal particles to serve as nucleuses to cover the resin 2 for the formation of a wiring pattern. By this setup, a wiring pattern can be formed even on a rugged surface or a curved surface, and furthermore a wiring pattern can be formed on a flexible board which is used as it is kept bent.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は基板あるいは半導体素子
上に形成した配線パターンの構造に係わり、更に詳しく
は安価であり微細なピッチに好適な配線パターンの構造
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring pattern structure formed on a substrate or a semiconductor element, and more particularly to a wiring pattern structure which is inexpensive and suitable for a fine pitch.

【0002】[0002]

【従来の技術】図4は、ガラス基板上に配線パターンを
形成した従来例を示す断面図であり、101はガラス基
板、102は基板101上に形成された透明導電膜、1
03は透明導電膜102上に形成された金属膜である。
また図5はガラスエポキシ基板上に銅箔により配線パタ
ーンを形成した従来例を示す断面図であり、104はガ
ラスエポキシ基板、105は接着剤、106はCu箔で
ある。
2. Description of the Related Art FIG. 4 is a sectional view showing a conventional example in which a wiring pattern is formed on a glass substrate, 101 is a glass substrate, 102 is a transparent conductive film formed on the substrate 101, and 1 is a transparent conductive film.
Reference numeral 03 is a metal film formed on the transparent conductive film 102.
FIG. 5 is a cross-sectional view showing a conventional example in which a wiring pattern is formed on a glass epoxy substrate with a copper foil, 104 is a glass epoxy substrate, 105 is an adhesive, and 106 is a Cu foil.

【0003】図4に示したガラス基板上への配線パター
ンの形成方法は以下の通りである。まず、酸化イリジュ
ウム等で形成される透明導電膜102を真空スパッタ装
置等を用いてガラス基板101の一面全体に0.1μm
程度成長させる。この透明導電膜102上にレジスト等
を用いて配線パターンを描画し、基板101をエッチン
グ液に浸しレジストの覆っていない部分の透明導電膜1
02を溶解除去する。レジストをレジスト除去のエッチ
ング液で除去し、さらに必要に応じて透明導電膜102
上にNi、Au等の金属膜103を無電解メッキ法等に
より0.1〜0.5μm程度形成する。
The method of forming the wiring pattern on the glass substrate shown in FIG. 4 is as follows. First, the transparent conductive film 102 made of iridium oxide or the like is formed on the entire surface of the glass substrate 101 by 0.1 μm by using a vacuum sputtering apparatus or the like.
Grow to a degree. A wiring pattern is drawn on the transparent conductive film 102 by using a resist or the like, and the substrate 101 is dipped in an etching solution so that the transparent conductive film 1 is not covered with the resist.
02 is dissolved and removed. The resist is removed with an etching solution for removing the resist, and if necessary, the transparent conductive film 102.
A metal film 103 made of Ni, Au, or the like is formed on the upper surface by electroless plating to have a thickness of about 0.1 to 0.5 μm.

【0004】図5に示したガラスエポキシ基板上への配
線パターンの形成方法は以下の通りである。まず、ガラ
スエポキシ基板104の片面全面に35μm程度の厚み
を持つCu箔106を接着剤105を用いて接着する。
次にCu箔106上にレジスト等を用いて配線パターン
を描画し、Cuのエッチング液にガラスエポキシ基板1
04を浸漬しレジストの覆っていない部分のCu箔10
6を溶解除去し、さらにレジストをエッチング除去する
ことで配線パターンを形成する。
The method of forming the wiring pattern on the glass epoxy substrate shown in FIG. 5 is as follows. First, a Cu foil 106 having a thickness of about 35 μm is bonded to the entire surface of one surface of the glass epoxy substrate 104 using an adhesive agent 105.
Next, a wiring pattern is drawn on the Cu foil 106 using a resist or the like, and the glass epoxy substrate 1 is applied to the Cu etching solution.
Cu foil 10 in a portion not covered with resist by immersing 04
6 is dissolved and removed, and the resist is removed by etching to form a wiring pattern.

【0005】[0005]

【発明が解決しようとする課題】上記従来技術では、例
えばガラス基板上に配線パターンを形成する前述の方法
においては、真空スパッタリング方法等のコストの高い
工程を用いるため、配線パターンの製造単価が高くな
る。さらに、真空スパッタリング方法で形成される薄膜
は、膜厚を厚くする事が物理的にも経済的にも困難なた
め、形成された配線パターンの抵抗が大きくならざるを
得ない。抵抗を下げるために金属膜をメッキするとさら
にコストの増加を招く。また、前述のガラスエポキシ基
板上への配線パターンの形成方法においては、配線パタ
ーンがCuの厚膜で構成されているため抵抗は小さく抑
えることが出来るが、Cu箔のエッチング時にサイドエ
ッチ等の現象が生じるため、配線パターンのピッチを細
密にすることが出来なかった。本発明は、上記の課題を
解決すべくなされたもので、安価な工程により配線パタ
ーンを形成し、なおかつ微細ピッチの配線パターンを形
成することを目的としたものである。
In the above-mentioned prior art, for example, in the above-described method of forming a wiring pattern on a glass substrate, a costly process such as a vacuum sputtering method is used, so that the manufacturing cost of the wiring pattern is high. Become. Further, it is difficult to increase the thickness of the thin film formed by the vacuum sputtering method physically and economically, so that the resistance of the formed wiring pattern must be increased. If a metal film is plated to reduce the resistance, the cost will be further increased. Further, in the above-described method of forming a wiring pattern on the glass epoxy substrate, since the wiring pattern is made of a thick film of Cu, the resistance can be suppressed to a small value, but when etching the Cu foil, a phenomenon such as side etching occurs. Therefore, the pitch of the wiring pattern could not be made fine. The present invention has been made to solve the above problems, and an object of the present invention is to form a wiring pattern by an inexpensive process and to form a wiring pattern with a fine pitch.

【0006】[0006]

【課題を解決するための手段】上記目的は、基板あるい
は半導体素子上に金属粒子を一様に分散させた樹脂によ
るパターンを形成し、無電解メッキ浴中で金属粒子を核
として成長させた金属膜により配線パターンを形成する
ことにより達成される。
Means for Solving the Problems The above-mentioned object is to form a pattern of a resin in which metal particles are uniformly dispersed on a substrate or a semiconductor element, and grow the metal particles as nuclei in an electroless plating bath. This is achieved by forming a wiring pattern with a film.

【0007】[0007]

【作用】基板あるいは半導体素子上に金属粒子を含有し
た樹脂の層を形成し、樹脂を選択的に硬化させ未硬化部
分を取り除いた後、無電解メッキ浴に浸漬し、金属粒子
を核として成長した金属膜が樹脂上を覆うことにより配
線パターンが形成される。
[Function] A resin layer containing metal particles is formed on a substrate or a semiconductor element, the resin is selectively cured to remove the uncured portion, and then the resin is immersed in an electroless plating bath to grow using the metal particles as nuclei. A wiring pattern is formed by covering the resin with the formed metal film.

【0008】[0008]

【実施例】以下、実施例により本発明の詳細を説明す
る。
The present invention will be described in detail below with reference to examples.

【0009】図1は、本発明の一実施例を示す配線パタ
ーンの断面図であり、図2(A)〜図2(C)は、図1
に示した配線パターンを形成する工程を示した断面図で
あり、図3は本発明の一応用例を示した斜視図である。
1は基板、2は樹脂、3は金属性の粒子、3aは樹脂2
より突出した金属粒子、4は金属膜、2aは樹脂2の硬
化した領域、2bは樹脂2の未硬化領域、5はマスク、
6は紫外線の照射方向を示す矢印、7は金属配線、8は
電極、9は半導体素子、10は本発明による配線パター
ン、11は金属線、12は半導体素子9上の保護膜であ
る。
FIG. 1 is a sectional view of a wiring pattern showing an embodiment of the present invention, and FIGS. 2 (A) to 2 (C) are shown in FIG.
4 is a cross-sectional view showing a step of forming the wiring pattern shown in FIG. 3, and FIG. 3 is a perspective view showing an application example of the present invention.
1 is a substrate, 2 is resin, 3 is metallic particles, and 3a is resin 2.
More protruding metal particles, 4 is a metal film, 2a is a cured region of resin 2, 2b is an uncured region of resin 2, 5 is a mask,
6 is an arrow indicating the direction of irradiation of ultraviolet rays, 7 is a metal wiring, 8 is an electrode, 9 is a semiconductor element, 10 is a wiring pattern according to the present invention, 11 is a metal wire, and 12 is a protective film on the semiconductor element 9.

【0010】まず、ガラス性の基板1上に0.1〜1μ
mの粒径を持つAg−Pd粒子3を5〜20%含有する
樹脂2を適量滴下する。このガラス基板1をスピンコー
ターにより3000rpmの回転速度で20秒間回転さ
せ、ガラス基板1上に樹脂2を約2μmの厚みとなるよ
う形成した。このとき樹脂2の厚みは、樹脂2の粘度お
よびスピンコーターの回転速度を変化させることにより
0.2〜150μmの範囲内の任意の値に設定すること
が可能であり、また樹脂2の塗布方法を凹版印刷あるい
は、スキージによるレベリング等を用いることにより2
0μm〜数mmの範囲の値にすることも可能である。樹
脂2として、紫外線硬化型のポリイミド系樹脂を用いて
いる。このようにして図2(A)に示した構造を得る。
First, 0.1 to 1 μm is formed on the glass substrate 1.
An appropriate amount of resin 2 containing 5 to 20% of Ag-Pd particles 3 having a particle diameter of m is dropped. The glass substrate 1 was rotated by a spin coater at a rotation speed of 3000 rpm for 20 seconds to form the resin 2 on the glass substrate 1 so as to have a thickness of about 2 μm. At this time, the thickness of the resin 2 can be set to an arbitrary value within the range of 0.2 to 150 μm by changing the viscosity of the resin 2 and the rotation speed of the spin coater. 2 by using intaglio printing or squeegee leveling
It is also possible to set the value in the range of 0 μm to several mm. As the resin 2, an ultraviolet curable polyimide resin is used. In this way, the structure shown in FIG. 2A is obtained.

【0011】次に、図2(B)に示すように樹脂2上に
マスク5を位置合わせし、紫外線を30mJ/cm2
照度で30秒間矢印6の方向に照射し、樹脂2を選択的
に硬化させ、硬化領域2aおよび未硬化領域2bを得
る。このガラス基板1を樹脂2の溶解液に2分間浸漬
し、未硬化領域2bを除去することで図2(C)に示し
た構造を得る。この時、樹脂2の硬化領域2aの樹脂表
面も0.05〜0.1μm溶解するため金属粒子3aの
様に樹脂2の表面近傍にある金属粒子3は樹脂2の表面
より突出することになる。このガラス基板1を70℃に
加温したNi無電解メッキ浴中に約10分浸漬する。メ
ッキ浴中のNiは樹脂2より突出した金属粒子3aを核
として成長をはじめ樹脂2の表面を覆い図1に示すよう
にNi金属膜4が約1μm成長し配線パターンが形成さ
れる。Niメッキの厚みは、メッキ液の種類およびメッ
キ時間により0.05μmから30μm程度まで任意の
厚みに設定可能であるが、通常用いられるような配線パ
ターンの場合は1〜5μmの厚みで十分である。また、
金属粒子3aのアンカー効果により金属膜4と樹脂2と
の密着力を大幅に向上させている。
Next, as shown in FIG. 2B, a mask 5 is aligned on the resin 2 and ultraviolet rays are irradiated in the direction of arrow 6 for 30 seconds at an illuminance of 30 mJ / cm 2 to selectively coat the resin 2. Then, the cured region 2a and the uncured region 2b are obtained. The glass substrate 1 is dipped in a solution of the resin 2 for 2 minutes to remove the uncured region 2b to obtain the structure shown in FIG. 2 (C). At this time, the resin surface of the cured region 2a of the resin 2 is also melted by 0.05 to 0.1 μm, so that the metal particles 3 near the surface of the resin 2 like the metal particles 3a project from the surface of the resin 2. .. The glass substrate 1 is immersed in a Ni electroless plating bath heated to 70 ° C. for about 10 minutes. Ni in the plating bath begins to grow with the metal particles 3a protruding from the resin 2 as a nucleus and covers the surface of the resin 2, and the Ni metal film 4 grows by about 1 μm to form a wiring pattern as shown in FIG. The thickness of the Ni plating can be set to any thickness from 0.05 μm to 30 μm depending on the type of plating solution and the plating time, but in the case of a wiring pattern that is usually used, a thickness of 1 to 5 μm is sufficient. .. Also,
The adhesion effect between the metal film 4 and the resin 2 is greatly improved by the anchor effect of the metal particles 3a.

【0012】このようにして形成された配線パターン
は、真空スパッタ装置の如き高価で巨大な製造設備を必
要とせず、また紫外線感光樹脂をパターンの形成に用い
ていることから微細なピッチの配線が容易である。また
配線パターンの高さ及び面積を任意の大きさにする事が
可能であり、例えば図3に示したように他の金属配線7
や電極8を有するような半導体素子9上に本発明による
配線パターン10を形成し、更に配線パターン10同
士、あるいは配線パターン10と他の電極8や金属配線
7等を金属線11を用いて立体的に接続することが容易
に行え、また樹脂の特性から凹凸を有する基板、あるい
は柔軟性を有する基板上にも対応することが出来る。
The wiring pattern formed in this manner does not require expensive and huge manufacturing equipment such as a vacuum sputtering apparatus, and since the ultraviolet photosensitive resin is used for forming the pattern, wiring with a fine pitch can be formed. It's easy. Further, the height and area of the wiring pattern can be arbitrarily set. For example, as shown in FIG.
The wiring pattern 10 according to the present invention is formed on the semiconductor element 9 having the electrodes 8 and the electrodes 8, and the wiring patterns 10 or the wiring pattern 10 and other electrodes 8 and the metal wiring 7 are three-dimensionally formed by using the metal wire 11. Can be easily connected electrically, and it can be applied to a substrate having irregularities or a substrate having flexibility due to the characteristics of the resin.

【0013】[0013]

【発明の効果】以上の説明から明らかなように、本発明
は基板あるいは半導体素子上に金属粒子含有する樹脂を
配置し、前記樹脂上に金属膜を製膜する事により、低コ
ストで微細なピッチの配線パターンを提供できる。ま
た、凹凸や曲面を有する表面上にも配線パターンを形成
でき、さらに柔軟性を有し折り曲げて使用するような基
板上にも配線パターンを形成することが可能となる。
As is apparent from the above description, according to the present invention, a resin containing metal particles is arranged on a substrate or a semiconductor element, and a metal film is formed on the resin, whereby a fine pattern can be produced at low cost. A pitch wiring pattern can be provided. In addition, the wiring pattern can be formed on the surface having the unevenness or the curved surface, and the wiring pattern can be formed on the substrate which is flexible and can be bent and used.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による配線パターンの一実施例を示した
断面図である。
FIG. 1 is a sectional view showing an embodiment of a wiring pattern according to the present invention.

【図2】本発明による配線パターンの製造工程を示した
断面図である。
FIG. 2 is a cross-sectional view showing a manufacturing process of a wiring pattern according to the present invention.

【図3】本発明による配線パターンの一応用例を示した
斜視図である。
FIG. 3 is a perspective view showing an application example of a wiring pattern according to the present invention.

【図4】従来例による配線パターンを示した断面図であ
る。
FIG. 4 is a cross-sectional view showing a wiring pattern according to a conventional example.

【図5】従来例による配線パターンを示した断面図であ
る。
FIG. 5 is a sectional view showing a wiring pattern according to a conventional example.

【符号の説明】[Explanation of symbols]

1 基板 2 樹脂 2a 樹脂2の硬化領域 2b 樹脂2の未硬化領域 3 金属粒子 3a 樹脂2より突出した金属粒子 4 金属膜 5 マスク 6 紫外線の照射方向を示す矢印 7 金属配線 8 電極 9 半導体素子 10 本発明による配線パターン 11 金属線 12 保護膜 101 ガラス基板 102 透明導電膜 103 金属膜 104 ガラスエポキシ基板 105 接着剤 106 Cu箔 DESCRIPTION OF SYMBOLS 1 Substrate 2 Resin 2a Cured region 2 of resin 2 Uncured region of resin 2 3 Metal particles 3a Metal particles protruding from resin 2 4 Metal film 5 Mask 6 Arrows indicating the irradiation direction of ultraviolet rays 7 Metal wiring 8 Electrode 9 Semiconductor element 10 Wiring pattern according to the present invention 11 Metal line 12 Protective film 101 Glass substrate 102 Transparent conductive film 103 Metal film 104 Glass epoxy substrate 105 Adhesive 106 Cu foil

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 電気信号の伝達を目的とし、基板あるい
は半導体素子上に形成する配線パターンにおいて、前記
基板あるいは前記半導体素子上に、金属粒子を含有した
樹脂を配置し、前記樹脂上に金属被覆を施すことにより
形成したことを特徴とする配線パターンの構造。
1. In a wiring pattern formed on a substrate or a semiconductor element for the purpose of transmitting an electric signal, a resin containing metal particles is arranged on the substrate or the semiconductor element, and the resin is metal-coated. A wiring pattern structure characterized by being formed by applying
【請求項2】 上記樹脂として、可視光、紫外線、赤外
線、電子線、等の空間における直進性を有するエネルギ
ー伝送体により選択的に硬化し、かつまた未硬化領域を
選択的に溶解、あるいは分解、あるいは溶融除去するこ
とが可能な樹脂を用いた請求項1記載の配線パターンの
構造。
2. The resin as described above is selectively cured by an energy transfer material having a linear property in a space such as visible light, ultraviolet ray, infrared ray, electron beam, etc., and an uncured region is selectively dissolved or decomposed. The structure of the wiring pattern according to claim 1, wherein a resin capable of being melted and removed is used.
【請求項3】 上記金属粒子として、Ni、Co、P
d、Cu、Zn、Sn、Ag、等の無電解メッキ可能な
金属、あるいは前記金属の合金による金属粒子を用いた
請求項1記載の配線パターンの構造。
3. The metal particles include Ni, Co and P.
The structure of a wiring pattern according to claim 1, wherein a metal capable of electroless plating such as d, Cu, Zn, Sn, Ag, or metal particles of an alloy of the metal is used.
JP23632791A 1991-09-17 1991-09-17 Wiring pattern structure Pending JPH0574767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23632791A JPH0574767A (en) 1991-09-17 1991-09-17 Wiring pattern structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23632791A JPH0574767A (en) 1991-09-17 1991-09-17 Wiring pattern structure

Publications (1)

Publication Number Publication Date
JPH0574767A true JPH0574767A (en) 1993-03-26

Family

ID=16999165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23632791A Pending JPH0574767A (en) 1991-09-17 1991-09-17 Wiring pattern structure

Country Status (1)

Country Link
JP (1) JPH0574767A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007000833A1 (en) * 2005-06-29 2007-01-04 Harima Chemicals, Inc. Method for electrically conductive circuit formation
JP2014011281A (en) * 2012-06-29 2014-01-20 Shinwa Industry Co Ltd Conductive pattern forming method and electric wiring circuit board manufactured using the same
JP2016058545A (en) * 2014-09-09 2016-04-21 住友電気工業株式会社 Substrate for printed wiring board, printed wiring board and method of manufacturing printed wiring board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007000833A1 (en) * 2005-06-29 2007-01-04 Harima Chemicals, Inc. Method for electrically conductive circuit formation
JPWO2007000833A1 (en) * 2005-06-29 2009-01-22 ハリマ化成株式会社 Method for forming conductive circuit
KR100957737B1 (en) * 2005-06-29 2010-05-12 하리마 카세이 가부시키가이샤 Method for electrically conductive circuit formation
JP4599403B2 (en) * 2005-06-29 2010-12-15 ハリマ化成株式会社 Method for forming conductive circuit
JP2014011281A (en) * 2012-06-29 2014-01-20 Shinwa Industry Co Ltd Conductive pattern forming method and electric wiring circuit board manufactured using the same
JP2016058545A (en) * 2014-09-09 2016-04-21 住友電気工業株式会社 Substrate for printed wiring board, printed wiring board and method of manufacturing printed wiring board

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