JPH0567683A - Identification circuit - Google Patents
Identification circuitInfo
- Publication number
- JPH0567683A JPH0567683A JP3230311A JP23031191A JPH0567683A JP H0567683 A JPH0567683 A JP H0567683A JP 3230311 A JP3230311 A JP 3230311A JP 23031191 A JP23031191 A JP 23031191A JP H0567683 A JPH0567683 A JP H0567683A
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- output
- switch circuit
- output pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
- H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体集積回路の入出
力パッドを利用して特定の識別情報を設定するための識
別回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an identification circuit for setting specific identification information using input / output pads of a semiconductor integrated circuit.
【０００２】半導体集積回路では例えば同一チップで多
品種を構成する場合の品種情報やメモリ等の予備ライン
の使用の有無等の情報を入出力パッドを介して外部から
識別可能とすることが要求されている。In a semiconductor integrated circuit, for example, it is required that the product type information in the case where a plurality of product types are formed by the same chip and the information such as whether or not a spare line such as a memory is used can be identified from the outside through an input / output pad. ing.
【０００３】[0003]
【従来の技術】従来の半導体集積回路に設けられた識別
回路では一つの入出力パッドに一つのヒューズが接続さ
れ、そのヒューズを切断するか否かによって当該入出力
パッドに例えば予備ラインを使用しているか否かを示す
「１」若しくは「０」の識別情報を出力可能としてい
る。2. Description of the Related Art In a conventional identification circuit provided in a semiconductor integrated circuit, one fuse is connected to one input / output pad, and a spare line is used for the input / output pad depending on whether the fuse is cut or not. It is possible to output the identification information of "1" or "0" indicating whether or not it is present.
【０００４】また、半導体集積回路を形成したチップが
ウェハ上のどの位置で形成されたものかを示す情報はバ
ルク工程中におけるパターニング工程でその位置情報が
チップ上に形成され、その情報は各チップで目視により
読み取るように構成されている。Further, the information indicating at which position on the wafer the chip on which the semiconductor integrated circuit is formed is formed is the position information formed on the chip in the patterning process during the bulk process. It is configured to be visually read at.
【０００５】[0005]
【発明が解決しようとする課題】ところが、上記のよう
に一つの入出力パッドに一つのヒューズが接続された識
別回路では一つの入出力パッドで一つの識別情報しか読
み出すことができないため、多数の識別情報が必要な場
合には多数の入出力パッドと同入出力パッドに接続され
る多数の識別回路が必要となるという問題点がある。従
って、上記のようなチップの位置情報は入出力パッドか
ら電気的に読み出す識別情報ではなく、目視による識別
情報が採用されている。However, in the identification circuit in which one fuse is connected to one input / output pad as described above, only one piece of identification information can be read out by one input / output pad, so that a large number of When the identification information is required, there is a problem that a large number of input / output pads and a large number of identification circuits connected to the same input / output pads are required. Therefore, the position information of the chip as described above is not the identification information that is electrically read from the input / output pad, but the visual identification information is used.
【０００６】この発明の目的は、少数の入出力パッドか
ら多数の識別情報を読出し可能とする識別回路を提供す
ることにある。An object of the present invention is to provide an identification circuit capable of reading a large number of identification information from a small number of input / output pads.
【０００７】[0007]
【課題を解決するための手段】図１は本発明の原理説明
図である。すなわち、図１（ａ）は一対の入出力パッド
１ａ，１ｂ間にスイッチ回路４を介して複数のヒューズ
３が並列に接続されている。FIG. 1 illustrates the principle of the present invention. That is, in FIG. 1A, a plurality of fuses 3 are connected in parallel between the pair of input / output pads 1a and 1b via the switch circuit 4.
【０００８】また、図１（ｂ）は一つの基準入出力パッ
ド５に対し他の複数の入出力パッド８がそれぞれスイッ
チ回路６とヒューズ７を介して並列に接続されている。Further, in FIG. 1B, a plurality of other input / output pads 8 are connected to one reference input / output pad 5 in parallel via a switch circuit 6 and a fuse 7, respectively.
【０００９】[0009]
【作用】図１（ａ）に示す回路ではスイッチ回路４を閉
路すれば並列に接続されたヒューズ３の切断本数に応じ
た抵抗値による多数の識別情報が入出力パッド１ａ，１
ｂから読出し可能となる。In the circuit shown in FIG. 1A, if the switch circuit 4 is closed, a large number of pieces of identification information based on the resistance value corresponding to the number of cut fuses 3 connected in parallel will be input / output pads 1a, 1.
It becomes possible to read from b.
【００１０】図１（ｂ）に示す回路では各スイッチ回路
６を閉路すれば各ヒューズ７の切断状況に応じた多ビッ
トのデジタル信号による識別情報が各入出力パッド８か
ら読出し可能となる。In the circuit shown in FIG. 1B, if each switch circuit 6 is closed, the identification information by a multi-bit digital signal according to the cutting state of each fuse 7 can be read from each input / output pad 8.
【００１１】[0011]
【実施例】以下、この発明を具体化した第一の実施例を
図２に従って説明する。一対の入出力パッド１ａ，１ｂ
は配線２でそれぞれ内部回路（図示しない）に接続さ
れ、同内部回路に対し信号を入出力可能となっている。
両入出力パッド１ａ，１ｂ間には例えば６本のヒューズ
３がスイッチ回路４を介して並列に接続されて識別回路
が構成され、同スイッチ回路４はテストモード時には一
括して閉路され、通常動作時には一括して開路される構
成となっている。そして、各ヒューズ３はレーザーによ
りそれぞれ切断可能となっている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment embodying the present invention will be described below with reference to FIG. A pair of input / output pads 1a, 1b
Are connected to internal circuits (not shown) by wirings 2 and signals can be input to and output from the internal circuits.
Between the two input / output pads 1a and 1b, for example, six fuses 3 are connected in parallel via a switch circuit 4 to form an identification circuit. The switch circuit 4 is closed at once in the test mode, and the normal operation is performed. Sometimes it is configured to open all at once. Each fuse 3 can be cut by a laser.
【００１２】このような識別回路ではあらかじめ任意本
数のヒューズ３を切断した状態でテストモード時には各
スイッチ回路４を閉路し、この状態で両入出力パッド１
ａ，１ｂ間の抵抗値を測定すると、全ヒューズ３を切断
した場合から全ヒューズ３を切断しない場合までの７通
りの抵抗値が検出可能である。従って、一対の入出力パ
ッド１ａ，１ｂにより７種類の識別情報を読み出すこと
が可能となる。In such an identification circuit, each switch circuit 4 is closed in the test mode with an arbitrary number of fuses 3 blown in advance, and both input / output pads 1 in this state.
When the resistance value between a and 1b is measured, seven resistance values can be detected from the case where all the fuses 3 are cut to the case where all the fuses 3 are not cut. Therefore, seven types of identification information can be read by the pair of input / output pads 1a and 1b.
【００１３】また、テストモード時以外ではスイッチ回
路４を開路すれば両入出力パッド１ａ，１ｂは内部回路
に対しそれぞれ独立したパッドとして作用し、配線２を
介して内部回路に対し信号を入出力可能となる。When the switch circuit 4 is opened except in the test mode, both the input / output pads 1a and 1b act as independent pads for the internal circuit, and input / output signals to / from the internal circuit via the wiring 2. It will be possible.
【００１４】次に、この発明を具体化した第二の実施例
を図３に従って説明する。基準入出力パッド５には多数
のスイッチ回路６が直列に接続され、各スイッチ回路６
間にはそれぞれヒューズ７及びスイッチ回路１１を介し
て各入出力パッド８が接続されている。そして、各ヒュ
ーズ７は前記実施例と同様にレーザーでそれぞれ切断可
能であり、各スイッチ回路６はテストモード時には一括
して閉路され、テストモード時以外では一括して開路さ
れる。また、各スイッチ回路１１はテストモード時には
一括して開路され、テストモード時以外では一括して閉
路される。また、前記基準入出力パッド５は配線９を介
して内部回路と接続され、入出力パッド８はそれぞれヒ
ューズ７、スイッチ回路１１及び配線１０を介して内部
回路に接続されている。Next, a second embodiment embodying the present invention will be described with reference to FIG. A large number of switch circuits 6 are connected in series to the reference input / output pad 5, and each switch circuit 6
Each input / output pad 8 is connected between them via a fuse 7 and a switch circuit 11, respectively. Each fuse 7 can be cut by a laser similarly to the above-described embodiment, and each switch circuit 6 is collectively closed in the test mode and is collectively opened except in the test mode. Further, the switch circuits 11 are collectively opened in the test mode, and are collectively closed except in the test mode. The reference input / output pad 5 is connected to an internal circuit via a wiring 9, and the input / output pad 8 is connected to the internal circuit via a fuse 7, a switch circuit 11 and a wiring 10.
【００１５】このような識別回路ではあらかじめ任意の
ヒューズ７を切断した状態でテストモード時には各スイ
ッチ回路６を閉路し、スイッチ回路１１を開路するとと
もに基準入出力パッド５に所定の電源電圧を供給し、こ
の状態で各入出力パッド８の電圧を検出すれば、ヒュー
ズ７の切断の有無に基づいて各入出力パッド８でＨレベ
ルあるいはＬレベルの２値信号が検出される。従って、
この識別回路では任意のヒューズ７を切断することによ
り例えば６つの入出力パッド８で６ビットのデジタル信
号を出力可能となり、少数の入出力パッドを使用して極
めて多数の識別信号を設定することが可能となる。In such an identification circuit, each switch circuit 6 is closed, the switch circuit 11 is opened, and a predetermined power supply voltage is supplied to the reference input / output pad 5 in the test mode with an arbitrary fuse 7 blown in advance. When the voltage of each input / output pad 8 is detected in this state, a binary signal of H level or L level is detected by each input / output pad 8 based on whether or not the fuse 7 is cut. Therefore,
In this discriminating circuit, by cutting an arbitrary fuse 7, for example, a 6-bit digital signal can be output from 6 input / output pads 8, and an extremely large number of discriminating signals can be set using a small number of input / output pads. It will be possible.
【００１６】また、テストモード時以外ではスイッチ回
路６を開路し、スイッチ回路１１を閉路すれば基準入出
力パッド５及び各入出力パッド８は内部回路に対しそれ
ぞれ独立したパッドとして作用し、配線９，１０を介し
て内部回路に対し信号を入出力可能となる。When the switch circuit 6 is opened and the switch circuit 11 is closed except in the test mode, the reference input / output pad 5 and each input / output pad 8 act as independent pads for the internal circuit, and the wiring 9 , 10 can input / output a signal to / from an internal circuit.
【００１７】[0017]
【発明の効果】以上詳述したように、この発明は少数の
入出力パッドから多数の識別情報を読出し得る識別回路
を提供することができる優れた効果を発揮する。As described above in detail, the present invention exerts an excellent effect of providing an identification circuit capable of reading a large number of identification information from a small number of input / output pads.
【図１】本発明の原理説明図である。FIG. 1 is a diagram illustrating the principle of the present invention.
【図２】第一の実施例を示す回路図である。FIG. 2 is a circuit diagram showing a first embodiment.
【図３】第二の実施例を示す回路図である。FIG. 3 is a circuit diagram showing a second embodiment.
１ａ，１ｂ，８ 入出力パッド ３，７ ヒューズ ４，６ スイッチ回路 ５ 基準入出力パッド 1a, 1b, 8 Input / output pad 3,7 Fuse 4,6 Switch circuit 5 Reference input / output pad
Claims (2)
スイッチ回路（４）を介して複数のヒューズ（３）を並
列に接続したことを特徴とする識別回路。1. An identification circuit comprising a plurality of fuses (3) connected in parallel between a pair of input / output pads (1a, 1b) via a switch circuit (4).
の複数の入出力パッド（８）をそれぞれスイッチ回路
（６）とヒューズ（７）を介して並列に接続したことを
特徴とする識別回路。2. A plurality of other input / output pads (8) are connected in parallel to one reference input / output pad (5) via a switch circuit (6) and a fuse (7), respectively. Identification circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3230311A JPH0567683A (en) | 1991-09-10 | 1991-09-10 | Identification circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3230311A JPH0567683A (en) | 1991-09-10 | 1991-09-10 | Identification circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0567683A true JPH0567683A (en) | 1993-03-19 |
Family
ID=16905848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3230311A Withdrawn JPH0567683A (en) | 1991-09-10 | 1991-09-10 | Identification circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0567683A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002045139A1 (en) * | 2000-12-01 | 2002-06-06 | Hitachi, Ltd | Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip |
| US9390812B2 (en) | 2014-07-01 | 2016-07-12 | Samsung Electronics Co., Ltd. | E-fuse test device and semiconductor device including the same |
-
1991
- 1991-09-10 JP JP3230311A patent/JPH0567683A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002045139A1 (en) * | 2000-12-01 | 2002-06-06 | Hitachi, Ltd | Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip |
| WO2002050910A1 (en) * | 2000-12-01 | 2002-06-27 | Hitachi, Ltd | Semiconductor integrated circuit device identifying method, semiconductor integrated circuit device producing method, and semiconductor integrated circuit device |
| US6941536B2 (en) | 2000-12-01 | 2005-09-06 | Hitachi, Ltd. | Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip |
| US7282377B2 (en) | 2000-12-01 | 2007-10-16 | Hitachi, Ltd. | Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip |
| KR100812850B1 (en) * | 2000-12-01 | 2008-03-11 | 가부시키가이샤 히타치세이사쿠쇼 | Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip |
| US7665049B2 (en) | 2000-12-01 | 2010-02-16 | Hitachi, Ltd. | Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip |
| US9390812B2 (en) | 2014-07-01 | 2016-07-12 | Samsung Electronics Co., Ltd. | E-fuse test device and semiconductor device including the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981203 |