JPH0558287B2 - - Google Patents
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- Publication number
- JPH0558287B2 JPH0558287B2 JP59157918A JP15791884A JPH0558287B2 JP H0558287 B2 JPH0558287 B2 JP H0558287B2 JP 59157918 A JP59157918 A JP 59157918A JP 15791884 A JP15791884 A JP 15791884A JP H0558287 B2 JPH0558287 B2 JP H0558287B2
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- Japan
- Prior art keywords
- power
- power supply
- current source
- transistor
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000003990 capacitor Substances 0.000 claims description 41
- 238000001514 detection method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000010354 integration Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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Description
【発明の詳細な説明】
〔発明の分野〕
本発明は光電スイツチや近接スイツチ等の無接
点スイツチに用いられ、電源投入時に誤動作を防
止するため所定時間出力を停止させる電源リセツ
ト回路に関するものである。[Detailed Description of the Invention] [Field of the Invention] The present invention relates to a power supply reset circuit used in non-contact switches such as photoelectric switches and proximity switches, which stops output for a predetermined period of time to prevent malfunctions when the power is turned on. .
無接点スイツチは電源投入の直後は回路電圧が
安定せず動作が不安定となる。特に高周波発振型
近接スイツチ等においては発振回路が正常に発振
を開始した以後でないと物体を検知することがで
きないので、電源投入後の所定時間は出力動作を
停止する必要がある。そこで無接点スイツチには
電源リセツト回路が設けられ、電源が投入されて
電圧が所定電圧に達した後、所定時間経過して始
めて外部に無接点スイツチ出力を出すようにして
いる。このような電源リセツト回路には積分用の
コンデンサを微小電流で充電し、その電圧が所定
電圧に達するまでの時間によつて出力を遅延させ
るリセツト回路が知られている。このようにリセ
ツト回路によれば、遅延時間は積分コンデンサの
容量によつて決定されることとなる。
Immediately after the power is turned on, the circuit voltage of a non-contact switch becomes unstable and its operation becomes unstable. In particular, in a high frequency oscillation type proximity switch etc., an object cannot be detected until after the oscillation circuit has started oscillation normally, so it is necessary to stop the output operation for a predetermined period of time after the power is turned on. Therefore, the non-contact switch is provided with a power reset circuit so that the non-contact switch outputs to the outside only after a predetermined period of time has passed after the power is turned on and the voltage reaches a predetermined voltage. Among such power supply reset circuits, there is known a reset circuit that charges an integrating capacitor with a minute current and delays the output depending on the time it takes for the voltage to reach a predetermined voltage. In this way, according to the reset circuit, the delay time is determined by the capacity of the integrating capacitor.
しかるに小型化が要求される無接点スイツチで
は形状が大きくなるコンデンサを使用することは
困難であり、例えば数10pF以下の容量のコンデ
ンサしか使用することができない。従つて遅延時
間を長くするためにダーリントン接続を用いたミ
ラー積分回路によつてコンデンサを積分するよう
にしていた。第４図及び第５図はこれらの従来の
ミラー積分による電源リセツト回路を示す図であ
つて、例えば数μA程度の定電流源１を用い、二
つのNPNトランジスタ２，３をダーリントン接
続としてトランジスタ２のコレクタ・ベース間に
積分コンデンサＣを挿入し、等価的にコンデンサ
Ｃの容量を二つのトランジスタの電流増幅率
（hfe）を乗じたものとしてその端子電圧をコンパ
レータ４によつて検知し、遅延時間を得るように
していた。第５図も同様にNPN型トランジスタ
５とPNP型トランジスタ６を用いたダーリント
ン接続によつてミラー積分回路を構成したもので
ある。 However, in non-contact switches that require miniaturization, it is difficult to use capacitors that have a large shape, and for example, only capacitors with a capacity of several tens of pF or less can be used. Therefore, in order to lengthen the delay time, a Miller integration circuit using a Darlington connection is used to integrate the capacitor. 4 and 5 are diagrams showing these conventional power supply reset circuits using Miller integration. For example, a constant current source 1 of about several μA is used, two NPN transistors 2 and 3 are connected in a Darlington connection, and the transistor 2 is connected. An integrating capacitor C is inserted between the collector and base of the capacitor C, and the terminal voltage is detected by the comparator 4, which is equivalently the capacitance of the capacitor C multiplied by the current amplification factor (hfe) of the two transistors, and the delay time is I was trying to get it. Similarly, in FIG. 5, a Miller integration circuit is constructed using a Darlington connection using an NPN type transistor 5 and a PNP type transistor 6.
ところで無接点スイツチに印加される電源が頻
繁に断続される制御方式があるが、ここで用いら
れている積分コンデンサに電荷が保持された状態
で再び電源が投入された場合、電源リセツト回路
が働かずそのまま動作を開始し誤つたスイツチ出
力を与えてしまう可能性がある。従来の電源リセ
ツト回路では電源投入時に誤動作なく無接点スイ
ツチを動作させるための対策が施されておらず、
頻繁に電源を断続する用途に使用する際に誤動作
が生ずる恐れがあつた。 By the way, there is a control method in which the power applied to a non-contact switch is frequently interrupted and disconnected, but if the power is turned on again with the integrating capacitor used here holding charge, the power reset circuit will not work. There is a possibility that the switch will start operating immediately and give an erroneous switch output. Conventional power reset circuits do not take measures to ensure that the non-contact switch operates without malfunction when the power is turned on.
There was a risk of malfunctions when used in applications where the power supply was frequently interrupted.
本発明はこのような従来の無接点スイツチの電
源リセツト回路の問題点に鑑みてなされたもので
あつて、頻繁に電源が断続される場合にも電源投
入の毎に所定時間確実に電源リセツト動作を行う
ことができる電源リセツト回路を提供することを
目的とする。
The present invention was made in view of the problems with the power reset circuit of the conventional non-contact switch, and is capable of reliably resetting the power for a predetermined period of time each time the power is turned on, even when the power is frequently interrupted. The purpose of the present invention is to provide a power supply reset circuit that can perform the following steps.
本願の第１の発明は、電源投入後の所定時間出
力を停止させる電源リセツト回路であつて、電源
電圧が所定値に達したときに駆動される電流源
と、電流源によつて充電される積分用コンデンサ
と、積分用コンデンサの両端にエミツタ・コレク
タ間が接続され、ベースとエミツタが電源に対し
て逆バイアスに接続されて電源投入時には不導通
となるトランジスタと、積分用コンデンサの電圧
を所定レベルと比較し充電電圧が所定値に達した
ときにリセツトを解除する比較手段と、を具備す
ることを特徴とするものである。
The first invention of the present application is a power supply reset circuit that stops output for a predetermined time after power is turned on, and includes a current source that is driven when the power supply voltage reaches a predetermined value, and a current source that is charged by the current source. An integrating capacitor, a transistor whose emitter and collector are connected to both ends of the integrating capacitor, and whose base and emitter are connected with a reverse bias to the power supply so that they are non-conducting when the power is turned on, and a transistor that is non-conductive when the power is turned on. The present invention is characterized by comprising comparison means that compares the charging voltage with the charging voltage level and cancels the reset when the charging voltage reaches a predetermined value.
本願の第２の発明は、電源投入後の所定時間出
力を停止させる電源リセツト回路であつて、電源
電圧が所定値に達したときに駆動される電流源
と、電流源によつて充電される積分用コンデンサ
と、積分用コンデンサの両端にコレクタ及びエミ
ツタ端が接続され、ベースが電源に対して逆バイ
アスに接続されて電源投入時には不導通となるト
ランジスタと、積分用コンデンサの電圧の上昇に
よつてリセツト解除信号を出力する比較回路と、
接地端と電流源との間に接続され、電流源によつ
て充電されて電源の遮断時にはトランジスタを導
通させる補助用コンデンサと、を具備することを
特徴とするものである。 A second invention of the present application is a power supply reset circuit that stops output for a predetermined time after power is turned on, and includes a current source that is driven when the power supply voltage reaches a predetermined value, and a current source that is charged by the current source. An integrating capacitor, a transistor whose collector and emitter terminals are connected to both ends of the integrating capacitor, and whose base is connected with a reverse bias to the power supply so that it becomes non-conducting when the power is turned on, a comparator circuit that outputs a reset release signal when
The device is characterized in that it includes an auxiliary capacitor connected between the ground terminal and the current source, charged by the current source, and making the transistor conductive when the power is cut off.
このような特徴を有する本発明によれば、短時
間で電源の断続が行われる用途に無接点スイツチ
が使用される場合にも電源を遮断する度に電源リ
セツト回路の積分用コンデンサが直ちに放電され
るため、次の電源投入に備えることができる。従
つて頻繁に電源が断続される場合にも確実に電源
リセツト動作を行わせることが可能となる。 According to the present invention having such characteristics, even when a non-contact switch is used in an application where the power is turned on and off in a short period of time, the integrating capacitor of the power reset circuit is immediately discharged every time the power is cut off. This allows you to prepare for the next power-on. Therefore, even if the power supply is frequently interrupted, the power supply reset operation can be performed reliably.
〔実施例の説明〕
第１図は本発明による電源リセツト回路の第１
実施例を示す回路図である。本図において電源の
両端間に電圧検知回路１０が設けられている。電
圧検知回路１０は電源電圧が動作可能な所定値を
越えるかどうかを検知する検知回路であつて、電
源電圧が所定値を越えれば出力を定電流源１１に
与える。定電流源１１は電圧検知回路１０から出
力が与えられたときに例えば数μAの一定電流を
トランジスタ１２のエミツタに与えるものであ
る。トランジスタ１２のコレクタはトランジスタ
１３，１４から成る電流ミラー回路CM１に接続
されており、そのベースは積分コンデンサＣ１を
介して接地されている。そして積分コンデンサＣ
１の両端にエミツタ・コレクタが接続された放電
用のトランジスタ１５が設けられ、そのベースは
電源に接続される。トランジスタ１３，１４のエ
ミツタ面積は1S対nS、即ちトランジスタ１４の
エミツタがｎ倍となるようにICチツプ上に形成
されているものとする。電流ミラー回路CM１の
トランジスタ１４のコレクタはトランジスタ１２
のエミツタと共に定電流源１１に共通接続され、
更にコンパレータ１６に与えられている。コンパ
レータ１６はこの電源リセツト回路の電圧が所定
値に達すれば無接点スイツチを動作可能とする出
力を与えるものである。[Description of Embodiments] FIG. 1 shows a first example of a power supply reset circuit according to the present invention.
FIG. 2 is a circuit diagram showing an example. In this figure, a voltage detection circuit 10 is provided between both ends of the power supply. The voltage detection circuit 10 is a detection circuit that detects whether the power supply voltage exceeds a predetermined value that allows operation, and provides an output to the constant current source 11 if the power supply voltage exceeds the predetermined value. The constant current source 11 supplies a constant current of, for example, several microamperes to the emitter of the transistor 12 when an output is given from the voltage detection circuit 10. The collector of the transistor 12 is connected to a current mirror circuit CM1 made up of transistors 13 and 14, and its base is grounded via an integrating capacitor C1. and integrating capacitor C
A discharge transistor 15 having an emitter and collector connected to both ends of the transistor 1 is provided, and its base is connected to a power supply. It is assumed that the emitter areas of the transistors 13 and 14 are 1S to nS, that is, the emitter area of the transistor 14 is formed on the IC chip so that it is n times larger. The collector of the transistor 14 of the current mirror circuit CM1 is the transistor 12
are commonly connected to the constant current source 11 together with the emitters of
Furthermore, it is provided to a comparator 16. The comparator 16 provides an output that enables the non-contact switch to operate when the voltage of the power supply reset circuit reaches a predetermined value.
次に上述した第１実施例の動作について説明す
る。第２図はこの無接点スイツチの各部の波形を
示す波形図である。本図において第２図ａに示す
ように時刻toに電源が投入されたとすると、以後
電源電圧が上昇する。そして電源電圧が所定値に
達すれば電圧検知回路１０より定電流源１１に電
圧検知出力が与えられる。そうすれば定電流源１
１より一定の電流が流出し、トランジスタ１２と
電流ミラー回路CM１のトランジスタ１４及び積
分コンデンサＣ１に電流が流れ込む。トランジス
タ１２のコレクタ電流はコンデンサＣ１に流れ込
む電流のhfe倍であり、前述したようにトランジ
スタ１３，１４のエミツタ面積が1S対nSとなつ
ているため、電流ミラー回路CM１によつてコレ
クタ電流がｎ倍に増幅される。従つてコンデンサ
Ｃ１に流れ込む電流の１＋（ｎ＋１）×hfe倍がト
ランジスタ１２とトランジスタ１４に流れ込むこ
ととなる。このときトランジスタ１５はベースが
電源に接続されているため逆バイアスされており
オフ状態となつている。従つて第２図ｂに示すよ
うにコンデンサＣ１の端子電圧は徐々に上昇し、
それに伴つてトランジスタ１４のコレクタ電圧も
上昇する。そしてその電圧が時刻t1に所定レベル
に達すればコンパレータ１６は第２図ｃに示すよ
うに出力を出し、以後無接点スイツチの動作を可
能とする。 Next, the operation of the first embodiment described above will be explained. FIG. 2 is a waveform diagram showing the waveforms of each part of this non-contact switch. In this figure, if the power is turned on at time to as shown in FIG. 2a, the power supply voltage will rise thereafter. When the power supply voltage reaches a predetermined value, the voltage detection circuit 10 provides a voltage detection output to the constant current source 11. Then constant current source 1
A constant current flows out from the transistor 1, and flows into the transistor 12, the transistor 14 of the current mirror circuit CM1, and the integrating capacitor C1. The collector current of the transistor 12 is hfe times the current flowing into the capacitor C1, and as mentioned above, since the emitter areas of the transistors 13 and 14 are 1S to nS, the collector current is multiplied by n by the current mirror circuit CM1. is amplified. Therefore, 1+(n+1)×hfe times the current flowing into the capacitor C1 flows into the transistors 12 and 14. At this time, the base of the transistor 15 is connected to the power supply, so it is reverse biased and is in an off state. Therefore, as shown in FIG. 2b, the terminal voltage of capacitor C1 gradually increases,
Correspondingly, the collector voltage of the transistor 14 also increases. When the voltage reaches a predetermined level at time t1, the comparator 16 outputs an output as shown in FIG. 2c, thereby enabling the non-contact switch to operate thereafter.
さて時刻t2に電源スイツチがオフとなつたとす
ると電源電圧が低下しトランジスタ１５のベース
電位も低下する。そうすればトランジスタ１５の
エミツタは積分コンデンサＣ１の電荷によつてベ
ース電位以上となるためトランジスタ１５が導通
し、そのため積分コンデンサＣ１は第２図ｂに示
すように急速に放電する。従つて時刻t3に再び電
源スイツチが投入されても同様の動作によつて電
源リセツト回路を確実に動作させることが可能と
なる。 Now, if the power switch is turned off at time t2, the power supply voltage decreases and the base potential of transistor 15 also decreases. Then, the emitter of the transistor 15 becomes higher than the base potential due to the charge of the integrating capacitor C1, so that the transistor 15 becomes conductive, so that the integrating capacitor C1 is rapidly discharged as shown in FIG. 2b. Therefore, even if the power switch is turned on again at time t3, the power reset circuit can be reliably operated by the same operation.
第３図は本発明による電源リセツト回路の他の
実施例を示す回路図である。本実施例において第
１図と同一部分は同一符号を用いて示している。
本実施例では定電流源１１に補助用コンデンサＣ
２と積分コンデンサＣ３が接続されており、積分
コンデンサＣ３の両端には放電用トランジスタ２
０のエミツタ・コレクタが接続されそのベースが
電源端に接続される。そして積分コンデンサＣ３
の他端はトランジスタ２１，２２から成る電源ミ
ラー回路CM２に接続されており、電流ミラー回
路CM２は第１実施例と同様にエミツタ面積を異
ならせて電流増幅を行つている。そしてトランジ
スタ２２のコレクタは電流増幅用のトランジスタ
２３のベースに接続されている。トランジスタ２
３はエミツタが積分コンデンサＣ３と共に定電流
源１１に共通接続され、又コンパレータ１６に接
続されている。 FIG. 3 is a circuit diagram showing another embodiment of the power supply reset circuit according to the present invention. In this embodiment, the same parts as in FIG. 1 are indicated using the same reference numerals.
In this embodiment, the constant current source 11 has an auxiliary capacitor C.
2 is connected to an integrating capacitor C3, and a discharging transistor 2 is connected to both ends of the integrating capacitor C3.
0 emitter-collector is connected and its base is connected to the power supply terminal. and integrating capacitor C3
The other end is connected to a power supply mirror circuit CM2 made up of transistors 21 and 22, and the current mirror circuit CM2 amplifies current by changing the emitter area as in the first embodiment. The collector of the transistor 22 is connected to the base of a current amplifying transistor 23. transistor 2
The emitter 3 is commonly connected to the constant current source 11 together with the integrating capacitor C3, and is also connected to the comparator 16.
本実施例においても電源が投入され電圧検知回
路１０より定電流源１１に検知出力が与えられる
と、定電流源１１よりコンデンサＣ２，Ｃ３に電
流が供給される。ここでコンデンサＣ３を流れる
電流は電流ミラー回路CM２及びトランジスタ２
３によつて電流増幅され、コンデンサＣ３の端子
電圧が所定値に達するまでコンパレータ１６の出
力によつて電源投入時のリセツト動作を停止す
る。そして電源がオフとなるとコンデンサＣ２の
電荷がトランジスタ２０のエミツタ・ベースを通
じて放電し、トランジスタ２０が導通する。従つ
て積分コンデンサＣ３が短絡された状態となつて
急速に放電される。そのため次に続けて電源が投
入されても電源リセツト回路を再び動作させるこ
とが可能である。 In this embodiment as well, when the power is turned on and the voltage detection circuit 10 provides a detection output to the constant current source 11, the constant current source 11 supplies current to the capacitors C2 and C3. Here, the current flowing through capacitor C3 is connected to current mirror circuit CM2 and transistor 2.
3, and the reset operation at power-on is stopped by the output of the comparator 16 until the terminal voltage of the capacitor C3 reaches a predetermined value. When the power is turned off, the charge in the capacitor C2 is discharged through the emitter and base of the transistor 20, and the transistor 20 becomes conductive. Integrating capacitor C3 is therefore short-circuited and rapidly discharged. Therefore, it is possible to operate the power supply reset circuit again even if the power is turned on next time.
第１図は本発明による無接点スイツチの電源リ
セツト回路の一実施例を示す回路図、第２図は第
１実施例による電源リセツト回路の動作を示す波
形図、第３図は本発明による電源リセツト回路の
他の実施例を示す回路図、第４図及び第５図は従
来の電源リセツト回路の一例を示す回路図であ
る。
１，１１……定電流源、２，３，５，６，１２
〜１５，２０〜２３……トランジスタ、１０……
電圧検知回路、４，１６……コンパレータ、Ｃ
１，Ｃ２，Ｃ３……コンデンサ、CM１，CM２
……電流ミラー回路。
FIG. 1 is a circuit diagram showing an embodiment of a power reset circuit for a non-contact switch according to the present invention, FIG. 2 is a waveform diagram showing the operation of the power reset circuit according to the first embodiment, and FIG. 3 is a power supply reset circuit according to the present invention. FIGS. 4 and 5 are circuit diagrams showing other embodiments of the reset circuit. FIGS. 4 and 5 are circuit diagrams showing an example of a conventional power supply reset circuit. 1, 11...constant current source, 2, 3, 5, 6, 12
~15, 20~23...transistor, 10...
Voltage detection circuit, 4, 16... comparator, C
1, C2, C3...Capacitor, CM1, CM2
...Current mirror circuit.
Claims (1)
リセツト回路において、 電源電圧が所定値に達したときに駆動される電
流源と、 前記電流源によつて充電される積分用コンデン
サと、 前記積分用コンデンサの両端にエミツタ・コレ
クタ間が接続され、ベースとエミツタが電源に対
して逆バイアスに接続されて電源投入時には不導
通となるトランジスタと、 前記積分用コンデンサの電圧を所定レベルと比
較し充電電圧が所定値に達したときにリセツトを
解除する比較手段と、を具備することを特徴とす
る電源リセツト回路。 ２ 電源投入後の所定時間出力を停止させる電源
リセツト回路において、 電源電圧が所定値に達したときに駆動される電
流源と、 前記電流源によつて充電される積分用コンデン
サと、 前記積分用コンデンサの両端にコレクタ及びエ
ミツタ端が接続され、ベースが電源に対して逆バ
イアスに接続されて電源投入時には不導通となる
トランジスタと、 前記積分用コンデンサの電圧の上昇によつてリ
セツト解除信号を出力する比較回路と、 接地端と前記電流源との間に接続され、電流源
によつて充電されて電源の遮断時には前記トラン
ジスタを導通させる補助用コンデンサと、を具備
することを特徴とする電源リセツト回路。[Scope of Claims] 1. A power supply reset circuit that stops output for a predetermined period of time after power is turned on, comprising: a current source that is driven when the power supply voltage reaches a predetermined value; and an integral circuit that is charged by the current source. a capacitor; a transistor whose emitter and collector are connected to both ends of the integrating capacitor, and whose base and emitter are connected in reverse bias to the power supply so that the transistor becomes non-conducting when the power is turned on; 1. A power supply reset circuit comprising: comparison means for comparing the charging voltage with a charging voltage level and canceling the reset when the charging voltage reaches a predetermined value. 2. A power supply reset circuit that stops output for a predetermined time after power is turned on, comprising: a current source that is driven when the power supply voltage reaches a predetermined value; an integrating capacitor that is charged by the current source; and an integrating capacitor that is charged by the current source. The collector and emitter terminals are connected to both ends of the capacitor, and the base is connected with a reverse bias to the power supply so that the transistor becomes non-conductive when the power is turned on, and a reset release signal is output by the voltage rise of the integrating capacitor. and an auxiliary capacitor connected between a ground terminal and the current source, charged by the current source, and making the transistor conductive when the power is cut off. circuit.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15791884A JPS6135615A (en) | 1984-07-27 | 1984-07-27 | Power supply reset circuit of contactless switch |
| AT85109521T ATE63019T1 (en) | 1984-07-27 | 1985-07-29 | POWER ON RESET CIRCUIT FOR A CONTACTLESS SWITCH. |
| EP85109521A EP0169583B2 (en) | 1984-07-27 | 1985-07-29 | Power-on reset circuit for contactless switch |
| US06/759,989 US4748352A (en) | 1984-07-27 | 1985-07-29 | Power source reset circuit for contactless switch |
| DE8585109521T DE3582620D1 (en) | 1984-07-27 | 1985-07-29 | SWITCH-ON RESET FOR A CONTACTLESS SWITCH. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15791884A JPS6135615A (en) | 1984-07-27 | 1984-07-27 | Power supply reset circuit of contactless switch |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35460392A Division JPH05335914A (en) | 1992-12-15 | 1992-12-15 | Power supply resetting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6135615A JPS6135615A (en) | 1986-02-20 |
| JPH0558287B2 true JPH0558287B2 (en) | 1993-08-26 |
Family
ID=15660301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15791884A Granted JPS6135615A (en) | 1984-07-27 | 1984-07-27 | Power supply reset circuit of contactless switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6135615A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54159838A (en) * | 1978-06-07 | 1979-12-18 | Mitsubishi Electric Corp | Protection unit for control unit using micro computer |
| JPS5743396U (en) * | 1980-08-25 | 1982-03-09 | ||
| JPS58133035A (en) * | 1982-02-02 | 1983-08-08 | Nec Corp | Power-on resetting circuit |
| JPS5958917A (en) * | 1982-09-29 | 1984-04-04 | Nec Corp | Power-on reset circuit |
| JPS59104816A (en) * | 1982-12-08 | 1984-06-16 | Hitachi Ltd | Starting circuit |
| JPS59163916A (en) * | 1983-03-08 | 1984-09-17 | Matsushita Electric Ind Co Ltd | Reset pulse generating device |
-
1984
- 1984-07-27 JP JP15791884A patent/JPS6135615A/en active Granted
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54159838A (en) * | 1978-06-07 | 1979-12-18 | Mitsubishi Electric Corp | Protection unit for control unit using micro computer |
| JPS5743396U (en) * | 1980-08-25 | 1982-03-09 | ||
| JPS58133035A (en) * | 1982-02-02 | 1983-08-08 | Nec Corp | Power-on resetting circuit |
| JPS5958917A (en) * | 1982-09-29 | 1984-04-04 | Nec Corp | Power-on reset circuit |
| JPS59104816A (en) * | 1982-12-08 | 1984-06-16 | Hitachi Ltd | Starting circuit |
| JPS59163916A (en) * | 1983-03-08 | 1984-09-17 | Matsushita Electric Ind Co Ltd | Reset pulse generating device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6135615A (en) | 1986-02-20 |
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