JPH0547920A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0547920A JPH0547920A JP20773491A JP20773491A JPH0547920A JP H0547920 A JPH0547920 A JP H0547920A JP 20773491 A JP20773491 A JP 20773491A JP 20773491 A JP20773491 A JP 20773491A JP H0547920 A JPH0547920 A JP H0547920A
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置及びその製造
方法、特にトレンチ状素子間分離領域の構造及びその形
成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a trench-shaped element isolation region and a method of forming the same.
【０００２】半導体装置の高集積化に伴い、素子間分離
領域の幅が縮小でき、且つ素子間分離領域の幅を縮小し
た際にも、リークの少ない素子間分離を行うことが可能
なトレンチを用いた素子間分離が多用されるようになっ
てきている。Along with the high integration of semiconductor devices, the width of the element isolation region can be reduced, and even when the width of the element isolation region is reduced, a trench capable of performing element isolation with less leakage can be formed. The isolation between the elements used is becoming popular.
【０００３】[0003]
【従来の技術】トレンチ状素子間分離領域は従来、以下
に図３の工程断面図を参照して説明する方法で形成され
ていた。2. Description of the Related Art Conventionally, a trench-shaped element isolation region has been formed by a method described below with reference to process sectional views of FIG.
【０００４】図３(a) 参照 即ち、半導体基板51上に窒化シリコン(Si3N4) 膜52と第
１の酸化シリコン(SiO 2)膜53を積層形成した後、フォト
リソグラフィにより上記第１のSiO2膜53及びSi 3N4 膜52
に、それらを貫通し、トレンチ形成領域を表出する開孔
54を形成する。Referring to FIG. 3A, that is, silicon nitride (Si3NFour) Membrane 52 and the
1 silicon oxide (SiO 2) After forming the film 53,
The first SiO by lithography2Membrane 53 and Si 3NFourMembrane 52
A hole that penetrates them and exposes the trench formation area
Forming 54.
【０００５】図３(b) 参照 次いで、上記第１のSiO2膜53をマスクにしリアクティブ
イオンエッチング（ＲＩＥ）手段により半導体基板51に
トレンチ56を形成する。Next, referring to FIG. 3B, a trench 56 is formed in the semiconductor substrate 51 by a reactive ion etching (RIE) method using the first SiO 2 film 53 as a mask.
【０００６】図３(c) 参照 次いで、第１のSiO2膜53を除去した後、Si3N4膜52をマ
スクにして選択酸化を行ってトレンチ56の内面に第２の
SiO2膜57を形成する。Next, as shown in FIG. 3C, after removing the first SiO 2 film 53, selective oxidation is performed using the Si 3 N 4 film 52 as a mask to form a second oxide film on the inner surface of the trench 56.
The SiO 2 film 57 is formed.
【０００７】図３(d) 参照 次いで、この基板上にトレンチ56内を完全に埋める厚さ
のポリシリコン層58を気相成長させる。Next, referring to FIG. 3 (d), a polysilicon layer 58 having a thickness to completely fill the trench 56 is vapor-deposited on the substrate.
【０００８】図３(e) 参照 次いで、Si3N4 膜52をストッパとしポリッシング手段に
より、Si3N4 膜52上のポリシリコン層58を選択的に除去
し、トレンチ56内のみをポリシリコン層58で埋める。[0008] FIG. 3 (e) see Then, Si 3 by N 4 film 52 as a stopper polishing means, Si 3 N 4 and polysilicon layer 58 on the film 52 is selectively removed, the polysilicon only in the trench 56 Fill with layer 58.
【０００９】図３(f) 参照 次いで、Si3N4 膜52をマスクにし選択酸化手段により、
前記トレンチ56内に埋め込まれたポリシリコン層58の表
面に第３のSiO2膜59を形成する方法である。Then, referring to FIG. 3 (f), the Si 3 N 4 film 52 is used as a mask to perform selective oxidation.
This is a method of forming a third SiO 2 film 59 on the surface of the polysilicon layer 58 buried in the trench 56.
【００１０】[0010]
【発明が解決しようとする課題】しかし上記従来の方法
によると、図からも明らかなようにトレンチ56が開口す
る半導体基板51の角部60がほぼ直角に形成されるため
に、このトレンチ状素子間分離領域上を基板51と高電位
差を有する配線が横切った際には上記角部60に電界集中
が起こって配線−基板間に電流リークが生じ易く、ま
た、トレンチ幅が極度に狭くなり且つトレンチの両側の
領域が高電位差を有する場合には素子間リークを生ずる
という問題があった。更にまた、トレンチ56内に埋め込
まれるポリシリコン層57の表面に熱酸化により形成され
る第３のSiO2膜58がトレンチ56の開口面全面に形成され
るので、その際、トレンチ56が開口する半導体基板51の
ほぼ直角に形成された角部60に強い圧縮応力を及ぼし、
この角部内に欠陥を生じ、この欠陥を介して素子内リー
クを生ずるという問題もあった。However, according to the above-mentioned conventional method, since the corner portion 60 of the semiconductor substrate 51 in which the trench 56 is opened is formed substantially at a right angle as is clear from the figure, this trench-shaped element is formed. When a wiring having a high potential difference with the substrate 51 crosses over the inter-isolation region, electric field concentration occurs in the corner portion 60 to easily cause current leakage between the wiring and the substrate, and the trench width becomes extremely narrow and If the regions on both sides of the trench have a high potential difference, there is a problem that leakage occurs between elements. Furthermore, since the third SiO 2 film 58 formed by thermal oxidation is formed on the entire surface of the opening surface of the trench 56 on the surface of the polysilicon layer 57 embedded in the trench 56, the trench 56 is opened at that time. A strong compressive stress is exerted on the corners 60 formed at substantially right angles of the semiconductor substrate 51,
There is also a problem that a defect is generated in this corner portion and an element leak is generated through this defect.
【００１１】そこで本発明は、トレンチ状素子間分離領
域を有する半導体装置において素子間分離領域及びその
近傍で発生する基板配線間リーク、素子間リーク、素子
内リーク等を防止することを目的とする。Therefore, it is an object of the present invention to prevent substrate wiring leakage, element leakage, element leakage, etc., which occur in the element isolation region and its vicinity in a semiconductor device having a trench-shaped element isolation region. ..
【００１２】[0012]
【課題を解決するための手段】上記課題の解決は、開口
部にテーパ状の拡大部を備えたトレンチ状素子間分離領
域を有する本発明による半導体装置、若しくは、開口部
にテーパ状の拡大部を有するトレンチ状素子間分離領域
を形成するに際して、半導体基板上に窒化シリコン膜と
第１の酸化シリコン膜を順次積層する工程、該第１の酸
化シリコン膜と窒化シリコン膜を貫通してトレンチ形成
領域を表出する開孔を形成する工程、該開孔を介する等
方性エッチング手段により、該半導体基板に、テーパ状
のアンダカット部を該窒化シリコン膜の下部に有する凹
部を形成する工程、該開孔を介し異方性ドライエッチン
グ手段により、該凹部の下部にトレンチを形成する工
程、該窒化シリコン膜をマスクにし選択酸化手段により
該凹部及びトレンチの内面に第２の酸化シリコン膜を形
成する工程、該基板上に該凹部及びトレンチ内を完全に
埋める厚さにシリコン層を気相成長させる工程、該第１
の酸化シリコン膜上にある該シリコン層、該第１の酸化
シリコン膜、該開孔内の窒化シリコン膜より上部にある
シリコン層を順次除去する工程、該窒化シリコン膜をマ
スクにし選択酸化手段により、該シリコン層の表面に第
３の酸化シリコン膜を形成する工程を有する本発明によ
る半導体装置の製造方法によって達成される。To solve the above problems, a semiconductor device according to the present invention having a trench-shaped element isolation region having a tapered enlarged portion in the opening, or a tapered enlarged portion in the opening is provided. Forming a trench-shaped element isolation region having a step of sequentially stacking a silicon nitride film and a first silicon oxide film on a semiconductor substrate, and forming a trench through the first silicon oxide film and the silicon nitride film. A step of forming an opening exposing a region, a step of forming a concave portion having a tapered undercut portion in the lower portion of the silicon nitride film in the semiconductor substrate by an isotropic etching means through the opening, A step of forming a trench below the recess by anisotropic dry etching means through the opening, and the recess and trench by the selective oxidation means using the silicon nitride film as a mask. Forming a second silicon oxide film on the inner surface, the step of the silicon layer is vapor-phase grown to a thickness which completely fills the recess and the trench on a substrate, said first
The step of sequentially removing the silicon layer on the silicon oxide film, the first silicon oxide film, and the silicon layer above the silicon nitride film in the opening, using the silicon nitride film as a mask by selective oxidation means. This is achieved by the method for manufacturing a semiconductor device according to the present invention, which has a step of forming a third silicon oxide film on the surface of the silicon layer.
【００１３】[0013]
【作用】即ち本発明の方法により形成されたトレンチ状
素子間分離領域は、その開口部にテーパ状に拡大した部
分を有し、上記開口部の周囲の基板の角部は鈍角状に形
成される。従ってこの基板角部の電界集中は緩和され、
その部分を介して生ずる配線−基板間、素子間のリーク
は防止される。またトレンチ内に埋め込まれたポリシリ
コン層表面に形成される熱酸化膜（従来方法における第
３のSiO2膜58に対応）は周辺部にポリシリコン層を残し
てその中央領域のみに形成されるので、この熱酸化膜に
よって分離領域周辺の半導体基板面に及ぼす圧縮応力は
大幅に緩和され、その部分に欠陥が生じなくなるため
に、素子内リークも防止される。That is, the trench-shaped element isolation region formed by the method of the present invention has a tapered enlarged portion in its opening, and the corners of the substrate around the opening are formed in obtuse angles. It Therefore, the electric field concentration at the corners of the substrate is relaxed,
Leakage between the wiring and the substrate and between the elements that occurs through the portion is prevented. Further, the thermal oxide film (corresponding to the third SiO 2 film 58 in the conventional method) formed on the surface of the polysilicon layer buried in the trench is formed only in the central region of the polysilicon layer while leaving the polysilicon layer in the peripheral portion. Therefore, the thermal oxide film relieves the compressive stress exerted on the semiconductor substrate surface in the vicinity of the isolation region to a great extent, and defects are not generated in that portion, so that leakage in the element is also prevented.
【００１４】[0014]
【実施例】以下本発明を、図を参照し、実施例により具
体的に説明する。図１は本発明に係る半導体装置の一実
施例の模式断面図、図２は本発明の方法の一実施例の工
程断面図である。全図を通じ同一対象物は同一符合で示
す。The present invention will be described in detail below with reference to the drawings and examples. 1 is a schematic sectional view of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a process sectional view of an embodiment of a method of the present invention. The same object is denoted by the same reference numeral throughout the drawings.
【００１５】図１は本発明に係るトレンチ状素子間分離
領域を用いた例えばＭＯＳ型半導体装置の模式断面図
で、図中、１はシリコン基板、２は Si3N4膜、５はテー
パ状拡大部、６はトレンチ、７は第２のSiO2膜、８はポ
リシリコン層、９は第３のSiO2膜、10はトレンチ開口の
角部、11は本発明に係るトレンチ状素子間分離領域、12
はゲート酸化膜、13はゲート電極、14はソース領域、1
4′は隣接素子のソース領域、15はドレイン領域、15′
は隣接素子のドレイン領域、16は層間絶縁膜、17はコン
タクト窓、18はソース配線、19はドレイン配線を示す。FIG. 1 is a schematic cross-sectional view of, for example, a MOS semiconductor device using a trench-shaped element isolation region according to the present invention. In the figure, 1 is a silicon substrate, 2 is a Si 3 N 4 film, and 5 is a tapered shape. Enlarged portion, 6 is a trench, 7 is a second SiO 2 film, 8 is a polysilicon layer, 9 is a third SiO 2 film, 10 is a corner portion of a trench opening, 11 is isolation between trench-like elements according to the present invention. Area, 12
Is a gate oxide film, 13 is a gate electrode, 14 is a source region, 1
4'is the source region of the adjacent element, 15 is the drain region, 15 '
Is a drain region of an adjacent element, 16 is an interlayer insulating film, 17 is a contact window, 18 is a source wiring, and 19 is a drain wiring.
【００１６】上記実施例に示されるような本発明に係る
トレンチ状素子間分離領域は、例えば以下の実施例に示
す本発明に係る製造方法によって形成される。 図２(a) 参照 即ち、所望の導電型を有するシリコン基板１上に、気相
成長法により厚さ 500Å程度の Si3N4膜２及び厚さ 0.8
〜１μｍの第１のSiO2膜３を順次堆積し、通常のフォト
リソグラフィにより上記第１のSiO2膜３及び Si3N4膜２
に、それらを貫通し、該シリコン基板１の例えば幅 0.5
〜１μｍ程度のトレンチ形成領域TAを表出する開孔４を
形成する。The trench-like element isolation regions according to the present invention as shown in the above embodiments are formed by, for example, the manufacturing method according to the present invention shown in the following embodiments. See FIG. 2 (a) That is, a Si 3 N 4 film 2 having a thickness of about 500 Å and a thickness of 0.8
The first SiO 2 film 3 having a thickness of 1 μm is sequentially deposited, and the first SiO 2 film 3 and the Si 3 N 4 film 2 are formed by ordinary photolithography.
And penetrate them, for example, the width of the silicon substrate 1 is 0.5
An opening 4 is formed to expose the trench formation area TA of about 1 μm.
【００１７】図２(b) 参照 そして先ず、上記第１のSiO2膜３及び Si3N4膜２をマス
クにしその開孔４を介し等方性エッチング手段である例
えばウェットエッチング処理により、シリコン基板１面
に深さ 0.5μｍ程度の凹部5Pを形成する。この等方性エ
ッチングによりSi3N4膜２の下部には図示のようなテー
パ状を有するアンダカットによるテーパ状拡大部５が形
成される。なおここで、等方性エッチング手段にはハロ
ゲン系ガスによるダウンフローエッチング等のドライエ
ッチング処理を用いてもよい。Referring to FIG. 2B, first, the first SiO 2 film 3 and the Si 3 N 4 film 2 are used as masks to form silicon through the openings 4 by isotropic etching, which is an isotropic etching means. A recess 5P having a depth of about 0.5 μm is formed on the surface of the substrate 1. By this isotropic etching, a tapered enlarged portion 5 by undercut having a tapered shape as shown in the figure is formed in the lower portion of the Si 3 N 4 film 2. Here, as the isotropic etching means, dry etching treatment such as downflow etching using a halogen-based gas may be used.
【００１８】図２(c) 参照 次いで、上記第１のSiO2膜３及び Si3N4膜２をマスクに
しその開孔４を介し異方性ドライエッチング手段である
例えばＲＩＥ処理により、前記凹部5Pの下部のシリコン
基板１に前記開孔４に整合する例えば 0.5〜１μｍ程度
の幅を有する深さ４〜５μｍ程度のトレンチ６を形成す
る。ここでＲＩＥ処理には通常のハロゲン系ガスが用い
られる。Referring to FIG. 2 (c), the recesses are formed by anisotropic dry etching means such as RIE through the openings 4 using the first SiO 2 film 3 and Si 3 N 4 film 2 as a mask. A trench 6 having a width of about 0.5 to 1 μm and a depth of about 4 to 5 μm, which is aligned with the opening 4, is formed in the silicon substrate 1 below the 5P. Here, a normal halogen-based gas is used for the RIE process.
【００１９】図２(d) 参照 次いで、前記 Si3N4膜２をマスクにし、例えばドライ酸
素中で選択酸化を行い、前記テーパ状拡大部５及びトレ
ンチ６の内面に厚さ 500〜2000Å程度の第２のSiO2膜７
を形成する。Next, referring to FIG. 2D, using the Si 3 N 4 film 2 as a mask, selective oxidation is performed in, for example, dry oxygen, and the thickness of the inner surface of the tapered enlarged portion 5 and the trench 6 is about 500 to 2000 Å. Second SiO 2 film 7
To form.
【００２０】図２(e) 参照 次いで、通常の気相成長手段により、上記基板上に、前
記トレンチ６及びテーパ状拡大部５の内部が完全に埋め
られるような 0.5〜１μｍ程度厚さのポリシリコン層８
を堆積する。Then, referring to FIG. 2 (e), a poly-silicon film having a thickness of about 0.5 to 1 μm is formed on the substrate by ordinary vapor phase growth means so as to completely fill the inside of the trench 6 and the tapered enlarged portion 5. Silicon layer 8
Deposit.
【００２１】図２(f) 参照 次いで、第１のSiO2膜３上のポリシリコン層８をハロゲ
ン系ガスによるエッチバックにより除去し、次いで第１
のSiO2膜３を弗酸系の液によるウェットエッチングによ
り除去する。Next, as shown in FIG. 2F, the polysilicon layer 8 on the first SiO 2 film 3 is removed by etching back with a halogen-based gas, and then the first SiO 2 film 3 is removed.
The SiO 2 film 3 is removed by wet etching with a hydrofluoric acid-based solution.
【００２２】図２(g) 参照 次いでポリッシングにより、前記開孔４部における Si3
N4膜２のよりも上部にあるポリシリコン層８を除去す
る。Referring to FIG. 2 (g), the Si 3 in the opening 4 is then polished by polishing.
The polysilicon layer 8 above the N 4 film 2 is removed.
【００２３】図２(h) 参照 次いで、 Si3N4膜２をマスクにし選択酸化を行い、トレ
ンチ６の上部のポリシリコン層８露出面に厚さ1000〜20
00Å程度の第３のSiO2膜９を形成し、本発明に係るトレ
ンチ状素子間分離領域11は完成する。Next, referring to FIG. 2 (h), selective oxidation is performed by using the Si 3 N 4 film 2 as a mask, and the exposed surface of the polysilicon layer 8 above the trench 6 has a thickness of 1000 to 20.
A third SiO 2 film 9 of about 00Å is formed, and the trench-shaped element isolation region 11 according to the present invention is completed.
【００２４】以上の実施例に示されるように、本発明に
係るトレンチ状素子間分離領域11は、トレンチ６の開口
部にはテーパ状拡大部５を有し、トレンチ開口部を囲む
シリコン基板１の角部10はなだらかな鈍角状を有する。
従ってこの基板１の角部10の電界集中は緩和されるの
で、この部分を介しての基板と高電位差を有する配線と
基板間の電流リークや、素子間のリークは防止される。
また、上記のようにトレンチ開口部周辺のシリコン基板
１の角部10がなだらかな鈍角状を有すると同時に、トレ
ンチ６開口部のテーパ状拡大部５上は Si3N4膜２で覆わ
れて絶縁され、トレンチ5B上に露出するポリシリコン層
６を覆って絶縁するために選択酸化によって形成される
第３のSiO2膜８は、前記基板１の角部10から離れたトレ
ンチ開口部中央のトレンチ６の直上部のみであるため、
選択酸化によって第３のSiO2膜８が形成される際、第３
のSiO2膜８によって基板１の角部10に及ぼされる圧縮応
力は大幅に緩和されるのる。従って上記角部及びその近
傍のシリコン基板内に発生する欠陥は大幅に減少し、該
欠陥に起因する素子内の電流リークも防止される。As shown in the above embodiments, the trench-shaped element isolation region 11 according to the present invention has the tapered enlarged portion 5 in the opening of the trench 6 and surrounds the trench opening. The corner portion 10 has a gentle obtuse shape.
Therefore, the electric field concentration at the corner portion 10 of the substrate 1 is relaxed, so that the current leakage between the wiring and the substrate having a high potential difference with the substrate and the leakage between the elements through this portion are prevented.
Further, as described above, the corner portion 10 of the silicon substrate 1 around the trench opening has a gentle obtuse shape, and at the same time, the tapered enlarged portion 5 of the trench 6 opening is covered with the Si 3 N 4 film 2. The third SiO 2 film 8 that is insulated and formed by selective oxidation to cover and insulate the polysilicon layer 6 exposed on the trench 5B is formed in the center of the trench opening away from the corner 10 of the substrate 1. Since it is just above the trench 6,
When the third SiO 2 film 8 is formed by selective oxidation,
The SiO 2 film 8 significantly relaxes the compressive stress exerted on the corner portion 10 of the substrate 1. Therefore, the number of defects generated in the above-mentioned corners and the silicon substrate in the vicinity thereof is significantly reduced, and the current leakage in the element due to the defects is also prevented.
【００２５】なお本発明に係る素子間分離は、上記実施
例に示したＭＯＳ型半導体装置に限らず、アイソプレー
ナー方式のバイポーラ半導体装置にも適用される。The element isolation according to the present invention is applicable not only to the MOS type semiconductor device shown in the above embodiment but also to an isoplanar type bipolar semiconductor device.
【００２６】[0026]
【発明の効果】以上説明のように本発明によれば、トレ
ンチを用いて狭い幅で素子間の分離を行って半導体装置
の高集積化を図る際に、トレンチの開口部近傍におけ
る、基板と配線間、素子間、素子内でリーク電流が発生
するのが防止される。As described above, according to the present invention, when a semiconductor device is highly integrated by separating elements with a narrow width by using a trench, a substrate near the opening of the trench is formed. Leak current is prevented from occurring between wirings, between elements, and within the element.
【００２７】従って本発明は、高集積化される半導体装
置の性能、信頼性等の向上に寄与するところが大きい。Therefore, the present invention largely contributes to the improvement of the performance and reliability of the highly integrated semiconductor device.
【図１】 本発明に係る半導体装置の一実施例の模式断
面図FIG. 1 is a schematic sectional view of an embodiment of a semiconductor device according to the present invention.
【図２】 本発明の方法の一実施例の工程断面図FIG. 2 is a process sectional view of an embodiment of the method of the present invention.
【図３】 従来方法の工程断面図FIG. 3 is a process sectional view of a conventional method.
１ シリコン基板 ２ Si3N4膜 ３ SiO2 膜 ４ 開孔 ５ テーパ状拡大部 5P 凹部 ６ トレンチ ７ 第２のSiO2膜 ８ ポリシリコン層 ９ 第３のSiO2膜 10 トレンチ開口の角部 11 本発明に係るトレンチ状素子間分離領域 12 ゲート酸化膜 13 ゲート電極 14 ソース領域 14′隣接素子のソース領域 15 ドレイン領域 15′隣接素子のドレイン領域 16 層間絶縁膜 17 コンタクト窓 18 ソース配線 19 ドレイン配線1 Silicon Substrate 2 Si 3 N 4 Film 3 SiO 2 Film 4 Opening 5 Tapered Expansion 5P Recess 6 Trench 7 Second SiO 2 Film 8 Polysilicon Layer 9 Third SiO 2 Film 10 Corner of Trench Opening 11 Trench-shaped element isolation region according to the present invention 12 Gate oxide film 13 Gate electrode 14 Source region 14 'Adjacent device source region 15 Drain region 15' Adjacent device drain region 16 Interlayer insulating film 17 Contact window 18 Source wiring 19 Drain wiring
Claims (2)
ンチ状素子間分離領域を有することを特徴とする半導体
装置。1. A semiconductor device having a trench-shaped element isolation region having a tapered enlarged portion in an opening.
ンチ状素子間分離領域を形成するに際して、 半導体基板上に窒化シリコン膜と第１の酸化シリコン膜
を順次積層する工程、該第１の酸化シリコン膜と窒化シ
リコン膜を貫通してトレンチ形成領域を表出する開孔を
形成する工程、 該開孔を介する等方性エッチング手段により、該半導体
基板に、テーパ状のアンダカット部を該窒化シリコン膜
の下部に有する凹部を形成する工程、 該開孔を介し異方性ドライエッチング手段により、該凹
部の下部にトレンチを形成する工程、 該窒化シリコン膜をマスクにし選択酸化手段により該凹
部及びトレンチの内面に第２の酸化シリコン膜を形成す
る工程、 該基板上に該凹部及びトレンチ内を完全に埋める厚さに
シリコン層を気相成長させる工程、 該第１の酸化シリコン膜上にある該シリコン層、該第１
の酸化シリコン膜、該開孔内の窒化シリコン膜より上部
にあるシリコン層を順次除去する工程、 該窒化シリコン膜をマスクにし選択酸化手段により、該
シリコン層の表面に第３の酸化シリコン膜を形成する工
程を有することを特徴とする半導体装置の製造方法。2. A step of sequentially laminating a silicon nitride film and a first silicon oxide film on a semiconductor substrate when forming a trench-shaped element isolation region having a tapered enlarged portion in an opening, A step of forming an opening penetrating the silicon oxide film and the silicon nitride film to expose a trench formation region, and a tapered undercut portion is formed on the semiconductor substrate by an isotropic etching means through the opening. A step of forming a recess under the silicon nitride film, a step of forming a trench under the recess by anisotropic dry etching means through the opening, the recess by selective oxidation means using the silicon nitride film as a mask And forming a second silicon oxide film on the inner surface of the trench, vapor-depositing a silicon layer on the substrate to a thickness that completely fills the recess and the trench, The silicon layer on the first silicon oxide film;
The step of sequentially removing the silicon oxide film and the silicon layer above the silicon nitride film in the opening, and using the silicon nitride film as a mask to selectively oxidize the third silicon oxide film on the surface of the silicon layer. A method of manufacturing a semiconductor device, comprising the step of forming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20773491A JPH0547920A (en) | 1991-08-20 | 1991-08-20 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20773491A JPH0547920A (en) | 1991-08-20 | 1991-08-20 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0547920A true JPH0547920A (en) | 1993-02-26 |
Family
ID=16544657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20773491A Pending JPH0547920A (en) | 1991-08-20 | 1991-08-20 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0547920A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0645809A1 (en) * | 1993-09-23 | 1995-03-29 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device comprising a semiconductor body with field insulation regions formed by grooves filled with insulating material |
| KR100470161B1 (en) * | 1998-06-29 | 2005-04-06 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device isolation film using trench |
| JP2006140523A (en) * | 2006-01-10 | 2006-06-01 | Seiko Instruments Inc | Vertical mos transistor and its manufacturing method |
| CN107098309A (en) * | 2012-09-12 | 2017-08-29 | 快捷半导体(苏州)有限公司 | Modified silicon hole including many material fillers |
-
1991
- 1991-08-20 JP JP20773491A patent/JPH0547920A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0645809A1 (en) * | 1993-09-23 | 1995-03-29 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device comprising a semiconductor body with field insulation regions formed by grooves filled with insulating material |
| BE1007588A3 (en) * | 1993-09-23 | 1995-08-16 | Philips Electronics Nv | Process for the production of a semiconductor device having a semiconductor body with field isolation regions FORMED BY by an insulating material filled grooves. |
| KR100470161B1 (en) * | 1998-06-29 | 2005-04-06 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device isolation film using trench |
| JP2006140523A (en) * | 2006-01-10 | 2006-06-01 | Seiko Instruments Inc | Vertical mos transistor and its manufacturing method |
| CN107098309A (en) * | 2012-09-12 | 2017-08-29 | 快捷半导体(苏州)有限公司 | Modified silicon hole including many material fillers |
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