JPH0547744A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0547744A JPH0547744A JP20666891A JP20666891A JPH0547744A JP H0547744 A JPH0547744 A JP H0547744A JP 20666891 A JP20666891 A JP 20666891A JP 20666891 A JP20666891 A JP 20666891A JP H0547744 A JPH0547744 A JP H0547744A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon nitride
- nitride film
- process gas
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は，半導体集積回路装置の
カバー膜の構造とその製造方法に関する。近年の半導体
集積回路の高集積化，多層配線化にともない，素子の表
面を保護するカバー絶縁膜においても高い信頼性が要求
されている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a cover film of a semiconductor integrated circuit device and a manufacturing method thereof. With the recent trend toward higher integration and multilayer wiring of semiconductor integrated circuits, high reliability is also required for the cover insulating film that protects the surface of the device.
【０００２】そのため，カバー絶縁膜が耐湿性や応力
（ストレス）等，配線に与える影響をできるだけ軽減さ
せる必要がある。Therefore, it is necessary to reduce the influence of the insulating cover film on the wiring, such as moisture resistance and stress.
【０００３】[0003]
【従来の技術】図３は従来例の説明図である。図におい
て，17は半導体基板, 18は配線膜, 19は下層絶縁膜, 20
は窒化シリコン膜である。2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example. In the figure, 17 is a semiconductor substrate, 18 is a wiring film, 19 is a lower insulating film, 20
Is a silicon nitride film.
【０００４】カバー絶縁膜としては，二酸化シリコン(S
iO2)膜や燐珪酸ガラス(PSG) 膜, 或いは窒化シリコン(S
i3N4) 膜が多く用いられており，この内， Si3N4膜は耐
湿性の点で最も優れている。Silicon dioxide (S
iO 2 ) film, phosphosilicate glass (PSG) film, or silicon nitride (S
Many i 3 N 4 ) films are used, and among these, the Si 3 N 4 film is the most excellent in terms of moisture resistance.
【０００５】従来， Si3N4膜の成膜には，プロセスガス
として，シラン(SiH4)，アンモニア(NH3),窒素(N2)の三
元系ガスを用いる場合，或いは，SiH4, N2の二元系ガス
を用いる場合が主流であった。Conventionally, when forming a Si 3 N 4 film, a ternary gas of silane (SiH 4 ), ammonia (NH 3 ), and nitrogen (N 2 ) is used as a process gas, or SiH 4 , N 2 binary gas was the mainstream.
【０００６】ところが，SiH4, NH3,N2の三元系ガスを用
いて成膜した Si3N4膜は基板の熱処理等で応力が下の表
１のように圧縮から引張と反転し易い。However, in the Si 3 N 4 film formed by using a ternary gas of SiH 4 , NH 3 and N 2 , the stress due to heat treatment of the substrate is reversed from compression to tension as shown in Table 1 below. easy.
【０００７】[0007]
【表１】 [Table 1]
【０００８】そのため，図３（ｂ）に示すように， Si3
N4膜20の成膜後は, 半導体基板17は圧縮応力により表面
が凸に沿っているが, N2雰囲気中,450℃で30分のアニー
ルを行うと, 引張応力により, 反対に表面が凹に反って
しまう。[0008] Therefore, as shown in FIG. 3 (b), Si 3
After the N 4 film 20 is formed, the surface of the semiconductor substrate 17 is convex due to the compressive stress. However, if annealing is performed at 450 ° C. for 30 minutes in the N 2 atmosphere, the surface of the semiconductor substrate 17 is opposite due to the tensile stress. It warps in the concave.
【０００９】このため, Si3N4膜20にクラックが入った
り, 配線膜が断線したりする。また, 赤外線吸収スペク
トルで，プロセスガスに NH3を使用した場合と使用しな
い場合の二種の Si3N4膜の水素の含有量を調べて見る
と, 水素の含有量が多いと2170cm-1のSi−Ｈと, 3340cm
-1のＮ−Ｈのピークが大きくなるので，図４に示すよう
に, NH3 を使用した三元系のプロセスガスで成膜した S
i3N4膜は水素を多く含んで, 特性的に問題を起こす欠点
がある。Therefore, the Si 3 N 4 film 20 is cracked or the wiring film is broken. In addition, the infrared absorption spectra of the two types of Si 3 N 4 films with and without NH 3 as the process gas were examined to find that the hydrogen content was 2170 cm −1 when the hydrogen content was high. Si-H, 3340cm
Since the N-H peak of -1 becomes large, as shown in Fig. 4, the S film formed by the ternary process gas using NH 3 was deposited.
The i 3 N 4 film has a drawback that it contains a large amount of hydrogen and causes problems in characteristics.
【００１０】一方, SiH4, N2の二元系プロセスガスを用
いて成膜した Si3N4膜は耐湿性が悪く, 例えば，二層配
線の製品で, ２気圧，121 ℃, 湿度100 ％の条件で耐湿
試験を行うと, SiH4, NH3, N2 の三元系ガスを用いて成
膜した Si3N4膜は良好な耐湿性を示したが, SiH4, N2の
二元系ガスを用いて成膜した Si3N4膜では, クラックが
多発した。On the other hand, a Si 3 N 4 film formed by using a binary process gas of SiH 4 and N 2 has poor moisture resistance. For example, a product with two-layer wiring has a pressure of 2 atm, a temperature of 121 ° C. and a humidity of 100 Doing% condition moisture resistance test in the, SiH 4, NH 3, Si 3 N 4 film formed by using the ternary gas N 2 showed good moisture resistance, of SiH 4, N 2 The Si 3 N 4 film formed by using the binary gas had many cracks.
【００１１】[0011]
【発明が解決しようとする課題】従って，上記の二種の
構成のプロセスガスを用いて成膜した Si3N4膜をカバー
絶縁膜として半導体集積回路に用いた場合，何れの Si3
N4膜を用いても信頼性に難があった。[0005] Thus, when used in a semiconductor integrated circuit to the Si 3 N 4 film was deposited using a process gas of a configuration of the above two as a cover insulating film, any of Si 3
Even with the N 4 film, the reliability was low.
【００１２】本発明は，上記の問題点を解決し，配線に
影響を与える耐湿性やストレス等を改善して，カバー絶
縁膜の信頼性向上を目的として提供されるものである。The present invention is provided for the purpose of solving the above problems, improving moisture resistance and stress that affect wiring, and improving reliability of a cover insulating film.
【００１３】[0013]
【課題を解決するための手段】図１は本発明の原理説明
図である。図において，１は半導体基板，２は配線膜，
３は下層絶縁膜，４は第１のSi3N4膜，５は第２の Si3N
4膜である。FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a wiring film,
3 is the lower insulating film, 4 is the first Si 3 N 4 film, and 5 is the second Si 3 N
There are 4 membranes.
【００１４】上記の問題点を解決するためには, 三元系
のプロセスガスとアンモニアを含まない二元系のプロセ
スガスを用いて成膜した Si3N4膜を重ねて，二層以上の
多重層にすれば良い。In order to solve the above problems, Si 3 N 4 films formed by using a ternary process gas and a binary process gas containing no ammonia are stacked to form two or more layers. It may be multi-layered.
【００１５】これにより，二種の Si3N4膜が有する欠点
が補われて，信頼性の良いカバー膜を得ることがてき
る。即ち，本発明の目的は，配線膜２等が形成された半
導体基板１上に， Si3N4膜を成膜する製造方法であっ
て，SiH4，N2，NH3 の三元系プロセスガスを用い，ＣＶ
Ｄ法により該半導体基板１上に第１の Si3N4膜４を被覆
し，続いて，NH3 を含まない，SiH4，N2の二元系プロセ
スガスを用い，ＣＶＤ法により前記第１の Si3N4膜４上
に第１の Si3N4膜４の少なくとも２倍以上の厚さの第２
の Si3N4膜５を積層することにより，或いは，SiH4，
N2，NH3 の三元系プロセスガスと，SiH4，N2の二元系プ
ロセスガスを交互に用いて，ＣＶＤ法により該半導体基
板１上に順に二種の Si3N4膜４，５を交互に積層するこ
とにより達成される。As a result, the drawbacks of the two kinds of Si 3 N 4 films are compensated, and a reliable cover film can be obtained. That is, an object of the present invention is a manufacturing method for forming a Si 3 N 4 film on a semiconductor substrate 1 on which a wiring film 2 and the like are formed, which is a ternary process of SiH 4 , N 2 and NH 3. CV using gas
The first Si 3 N 4 film 4 is coated on the semiconductor substrate 1 by the D method, and subsequently, the above-mentioned first Si 3 N 4 film 4 is deposited by the CVD method using a binary process gas of SiH 4 and N 2 containing no NH 3 . The second Si layer having a thickness at least twice that of the first Si 3 N 4 film 4 is formed on the first Si 3 N 4 film 4.
By laminating the Si 3 N 4 film 5 of, or, SiH 4,
By alternately using a ternary process gas of N 2 and NH 3 and a ternary process gas of SiH 4 and N 2 , two types of Si 3 N 4 films 4 are sequentially formed on the semiconductor substrate 1 by a CVD method. This is achieved by stacking 5 alternately.
【００１６】[0016]
【作用】本発明では，最下層に三元系のプロセスガスに
より成膜した第１の Si3N4膜を1,000Å程度に薄く被覆
して水分を阻止（ブロック）し，その上に二元系のプロ
セスガスにより成膜した第２の Si3N4膜を厚く成長す
る。In the present invention, the first Si 3 N 4 film formed by the ternary process gas as the lowermost layer is thinly coated to about 1,000 Å to block (block) water, and the binary A second Si 3 N 4 film formed by a system process gas is grown thick.
【００１７】この膜の厚さを前者の少なくとも２倍以上
にすればストレスの変化の軽減が図れる。If the thickness of this film is at least twice the thickness of the former, the change in stress can be reduced.
【００１８】[0018]
【実施例】図１は本発明の原理説明図兼一実施例の模式
断面図，図２はプラズマＣＶＤ装置である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic cross-sectional view of one embodiment of the present invention, and FIG.
【００１９】図において１は半導体基板，２は配線膜，
３は下層絶縁膜，４は第１の Si3N4膜，５は第２の Si3
N4膜，６はチャンバ，７はガスシャワー，８は石英窓，
９はランプヒータ，10はガス導入口, 11はシランガス容
器, 12は窒素ガス容器, 13はアンモニアガス容器, 14は
開閉バルブ, 15は排気口, 16はＲＦ電源である。In the figure, 1 is a semiconductor substrate, 2 is a wiring film,
3 is the lower insulating film, 4 is the first Si 3 N 4 film, and 5 is the second Si 3
N 4 film, 6 chamber, 7 gas shower, 8 quartz window,
9 is a lamp heater, 10 is a gas inlet, 11 is a silane gas container, 12 is a nitrogen gas container, 13 is an ammonia gas container, 14 is an opening / closing valve, 15 is an exhaust port, and 16 is an RF power supply.
【００２０】本発明の一実施例について，図１，図２に
より工程順に説明する。図１に示すように，半導体基板
１として，既に１μｍの厚さに，アルミニウム(Al)の配
線膜２がパターニングされたシリコンウエハを用い，下
層絶縁膜３として, PSG 膜を常圧ＣＶＤ層装置を用い，
基板温度 410℃, SiH4ガス80sccm, 酸素(02)ガス１slm,
フォスフィン(PH3) ガス 900sccmをプロセスガスとして
用いて,5,000 Åの厚さに被覆する。An embodiment of the present invention will be described in the order of steps with reference to FIGS. As shown in FIG. 1, the semiconductor substrate 1 is a silicon wafer on which the aluminum (Al) wiring film 2 is already patterned to a thickness of 1 μm, and the PSG film is used as the lower insulating film 3 under the atmospheric pressure CVD layer device. Using
Substrate temperature 410 ℃, SiH 4 gas 80sccm, Oxygen (0 2 ) gas 1slm,
The phosphine (PH 3 ) gas 900sccm is used as the process gas to coat the thickness of 5,000Å.
【００２１】次に, 図２に示すプラズマＣＶＤ装置を用
い，基板温度415 ℃にチャンバ６内にセットした半導体
基板をランプヒータ９により石英窓８を通して加熱し，
各プロセスガスの容器から，SiH4 25sccm, NH3 150scc
m, N2 300sccmの三元系プロセスガスをガス導入口10よ
りガスシャワー７を通してチャンパ６内に導入し, ＲＦ
周波数200KHz, 出力30Ｗ，チャンバ６内圧力１.0Torrの
条件で，半導体基板１上に第１の Si3N4膜４を，1,000
Åの厚さに形成する。Next, using the plasma CVD apparatus shown in FIG. 2, the semiconductor substrate set in the chamber 6 at a substrate temperature of 415 ° C. is heated by the lamp heater 9 through the quartz window 8,
From each process gas container, SiH 4 25sccm, NH 3 150scc
A ternary process gas of m, N 2 300 sccm was introduced into the champer 6 through the gas shower 7 through the gas inlet 10 and RF.
Under the conditions of a frequency of 200 KHz, an output of 30 W, and a chamber 6 internal pressure of 1.0 Torr, a first Si 3 N 4 film 4 of 1,000 was formed on the semiconductor substrate 1.
Form to a thickness of Å.
【００２２】続いて, アンモニアガス容器に通ずる開閉
バルブ14を閉じて, SiH4を80sccm,N2を1500sccmの二元
系のプロセスガスを用い, 前述と同様の条件で, 半導体
基板１の第１の Si3N4膜４上に第２の Si3N4膜５を 2,5
00Åの厚さに積層する。Next, the on-off valve 14 leading to the ammonia gas container was closed, and a binary process gas of SiH 4 of 80 sccm and N 2 of 1500 sccm was used, and the first substrate of the semiconductor substrate 1 was processed under the same conditions as described above. A second Si 3 N 4 film 5 is formed on the Si 3 N 4 film 4 of
Stack to a thickness of 00Å.
【００２３】この結果, 二種の Si3N4膜４，５をカバー
絶縁膜として積層したため, Al配線膜に耐する耐湿性は
向上し, かつ応力の反転も少ない基板が得られた。As a result, since the two kinds of Si 3 N 4 films 4 and 5 were laminated as the cover insulating film, the humidity resistance against the Al wiring film was improved, and the substrate with less stress reversal was obtained.
【００２４】[0024]
【発明の効果】以上説明したように, 本発明によれば,
耐湿性を向上させるとともに，熱処理によるストレス反
転の程度を軽減でき，配線の信頼性向上に寄与するとこ
ろが大きい。As described above, according to the present invention,
In addition to improving the moisture resistance, it is possible to reduce the degree of stress reversal due to heat treatment, which greatly contributes to improving the reliability of the wiring.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 プラズマＣＶＤ装置FIG. 2 Plasma CVD apparatus
【図３】 従来例の説明図FIG. 3 is an explanatory diagram of a conventional example.
【図４】 Si3N4膜の赤外線吸収スペクトルFig. 4 Infrared absorption spectrum of Si 3 N 4 film
１ 半導体基板 ２ 配線膜 ３ 下層絶縁膜 ４ 第１の Si3N4膜 ５ 第２の Si3N4膜 ６ チャンバ ７ ガスシャワー ８ 石英窓 ９ ランプヒータ 10 ガス導入口 11 シランガス容器 12 窒素ガス容器 13 アンモニアガス容器 14 開閉バルブ 15 排気口 16 ＲＦ電源1 semiconductor substrate 2 wiring film 3 lower insulating film 4 first Si 3 N 4 film 5 second Si 3 N 4 film 6 chamber 7 gas shower 8 quartz window 9 lamp heater 10 gas inlet 11 silane gas container 12 nitrogen gas container 13 Ammonia gas container 14 Open / close valve 15 Exhaust port 16 RF power supply
Claims (2)
に，窒化シリコン膜を成膜する製造方法であって， シラン，窒素，アンモニアの三元系プロセスガスを用
い，ＣＶＤ法により該半導体基板上に第１の窒化シリコ
ン膜を被覆し， 続いて，アンモニアを含まない，シラン，窒素の二元系
プロセスガスを用い，ＣＶＤ法により前記第１の窒化シ
リコン膜上に第１の窒化シリコン膜の少なくとも２倍以
上の厚さの第２の窒化シリコン膜を積層することを特徴
とする半導体装置の製造方法。1. A manufacturing method for forming a silicon nitride film on a semiconductor substrate on which an electrode wiring film is formed, wherein the semiconductor substrate is formed by a CVD method using a ternary process gas of silane, nitrogen and ammonia. The first silicon nitride film is coated on the first silicon nitride film, and then the first silicon nitride film is formed on the first silicon nitride film by a CVD method using a binary process gas containing no ammonia and containing silane and nitrogen. Of the second silicon nitride film having a thickness at least twice as much as the above.
に，窒化シリコン膜を成膜する製造方法であって， シラン，窒素，アンモニアの三元系プロセスガスとアン
モニアを含まない，シラン，窒素の二元系プロセスガス
を交互に用いて，ＣＶＤ法により該半導体基板上に順に
窒化シリコン膜を積層することを特徴とする半導体装置
の製造方法。2. A manufacturing method for forming a silicon nitride film on a semiconductor substrate on which an electrode wiring film is formed, which is a ternary process gas of silane, nitrogen, and ammonia and does not contain ammonia. 2. A method of manufacturing a semiconductor device, wherein a silicon nitride film is sequentially deposited on the semiconductor substrate by a CVD method by alternately using the binary system process gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20666891A JPH0547744A (en) | 1991-08-19 | 1991-08-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20666891A JPH0547744A (en) | 1991-08-19 | 1991-08-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0547744A true JPH0547744A (en) | 1993-02-26 |
Family
ID=16527154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20666891A Withdrawn JPH0547744A (en) | 1991-08-19 | 1991-08-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0547744A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008300678A (en) * | 2007-05-31 | 2008-12-11 | Oki Electric Ind Co Ltd | Manufacturing method for semiconductor device, and semiconductor device |
| WO2010098295A1 (en) * | 2009-02-25 | 2010-09-02 | 日本電気株式会社 | Optical waveguide, optical waveguide circuit, and method for manufacturing optical waveguide circuit |
| JP2021100093A (en) * | 2019-12-20 | 2021-07-01 | 東京エレクトロン株式会社 | Etching method, substrate processing device, and substrate processing system |
-
1991
- 1991-08-19 JP JP20666891A patent/JPH0547744A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008300678A (en) * | 2007-05-31 | 2008-12-11 | Oki Electric Ind Co Ltd | Manufacturing method for semiconductor device, and semiconductor device |
| WO2010098295A1 (en) * | 2009-02-25 | 2010-09-02 | 日本電気株式会社 | Optical waveguide, optical waveguide circuit, and method for manufacturing optical waveguide circuit |
| JP2021100093A (en) * | 2019-12-20 | 2021-07-01 | 東京エレクトロン株式会社 | Etching method, substrate processing device, and substrate processing system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981112 |