JPH0546706B2 - - Google Patents
Info
- Publication number
- JPH0546706B2 JPH0546706B2 JP59215155A JP21515584A JPH0546706B2 JP H0546706 B2 JPH0546706 B2 JP H0546706B2 JP 59215155 A JP59215155 A JP 59215155A JP 21515584 A JP21515584 A JP 21515584A JP H0546706 B2 JPH0546706 B2 JP H0546706B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- oxide film
- island
- film
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 82
- 229910021426 porous silicon Inorganic materials 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 2
- 239000013078 crystal Substances 0.000 description 26
- 238000000034 method Methods 0.000 description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 13
- 239000010410 layer Substances 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 230000007547 defect Effects 0.000 description 10
- 239000012535 impurity Substances 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 235000002918 Fraxinus excelsior Nutrition 0.000 description 1
- 239000002956 ash Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000001659 ion-beam spectroscopy Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は高密度にして高速度な大規模集積回路
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to high-density, high-speed large-scale integrated circuits.
（従来技術）
従来、半導体集積回路における素子分離法とし
てMOSLSIの場合、LOCOS法、バイポーラLSI
の場合pn接合分離あるいはアイソプレーナ法等
が用いられてきた。しかし、LSIの寄生容量の低
減、寄生トランジスタの防止等のためには素子間
を誘電体で完全に分離することが理想的である。
誘電体を用いた完全分離法としてはこれまでに
CEPIC技術、SOS技術、SIMOX技術、FIPOS技
術等がある。(Prior art) Conventionally, element isolation methods in semiconductor integrated circuits include MOSLSI, LOCOS, and bipolar LSI.
In this case, pn junction isolation or isoplanar methods have been used. However, in order to reduce the parasitic capacitance of LSI and prevent parasitic transistors, it is ideal to completely isolate the elements with a dielectric material.
Until now, there has been no complete isolation method using a dielectric.
There are CEPIC technology, SOS technology, SIMOX technology, FIPOS technology, etc.
（発明が解決しようとする問題点）
CEPIC技術は厚い多結晶シリコン層を形成し、
研磨やエツチングでSi面を加工するが、加工精度
の点から高密度大規模なLSIの素子間分離には適
さない。SOS技術はエピタキシヤル成長させたSi
薄膜の結晶性が不完全でかつ基板価格の点で難点
がある。SIMOX技術は基板製作のスループツト
をあげるための高電流イオン注入装置の開発が待
たれている。又、基板内部に埋め込まれた酸化膜
の膜厚増加が望まれる。FIPOS技術は上記の各
方法が有する問題点、例えば高密度大規模化、結
晶性、基板価格、製作スループツト、埋め込まれ
た酸化膜厚等の点で優れた特徴をもつ技術である
が従来の製造方法では、化成酸化後にSiウエハの
そりが増大したり、完全分離されたSi島に結晶欠
陥が発生する等の欠点があつた。第７図に従来の
FIPOS構造の断面図を示す。図において１はｐ
型シリコン基板、２は多孔質シリコン酸化膜、３
は多孔質シリコン酸化膜２によつて１から完全に
分離されたSi島でこの島の中にはソース６、ドレ
イン７が含まれている。４はゲート酸化膜、５は
多結晶Siゲート、８は層間絶縁膜、９は電極配線
である。(Problem to be solved by the invention) CEPIC technology forms a thick polycrystalline silicon layer,
Although the Si surface is processed by polishing or etching, it is not suitable for isolation between elements in high-density, large-scale LSIs due to processing accuracy. SOS technology uses epitaxially grown Si
The problem is that the crystallinity of the thin film is incomplete and the cost of the substrate is low. SIMOX technology is awaiting the development of high-current ion implantation equipment to increase the throughput of substrate fabrication. Furthermore, it is desired to increase the thickness of the oxide film buried inside the substrate. FIPOS technology is a technology that has superior features in terms of problems that each of the above methods have, such as high density and large scale, crystallinity, substrate cost, manufacturing throughput, and embedded oxide film thickness, but it is a technology that is superior to conventional manufacturing. This method had drawbacks such as increased warpage of the Si wafer after chemical oxidation and the occurrence of crystal defects in completely isolated Si islands. Figure 7 shows the conventional
A cross-sectional view of the FIPOS structure is shown. In the figure, 1 is p
type silicon substrate, 2 is porous silicon oxide film, 3
is a Si island completely separated from 1 by a porous silicon oxide film 2, and this island contains a source 6 and a drain 7. 4 is a gate oxide film, 5 is a polycrystalline Si gate, 8 is an interlayer insulating film, and 9 is an electrode wiring.
第７図Ａに示すように、完全分離されたSi島３
の長さＷの中には、ゲート５及びソース６、ドレ
イン７が作られ、ソース６とドレイン７の上に堆
積した層間絶縁膜８には電極配線９とソース６及
びドレイン７とをコンタクトさせるためにスルー
ホールがあけられる。第７図Ａに示されているＷ
はMOSFETのゲート長方向を示し、このＷに垂
直で、かつ紙面に垂直な方向がゲート巾方向を示
す。ゲート幅Wpが、ゲート長Lpの数倍以下のト
ランジスタでは、ゲート幅方向のSi島の幅の方が
ゲート長方向のSi島の幅よりも小さくなるため、
完全分離に必要な多孔質シリコン酸化膜の厚さは
ゲート幅方向のSi島の幅で決定される。しかしな
がら、LSIの中には、種々のゲート幅をもつトラ
ンジスタが存在し、それらのトランジスタを完全
分離するための多孔質シリコン酸化膜の膜厚Ｔと
しては１ウエハについては１種類だけ選ばれる。
通常完全分離されるSi島の長さＷはａ＝δ、ｂ＝
2δのとき最小となり、Ｗ＝｛（Lp＋2δ）＋２（Lc＋
2δ）｝となる。Lpはゲート長、δはSi島３に対す
るゲートおよびスルーホールの合わせ精度、Lc
はソース、又はドレインに対するコンタクトのた
めのスルーホールの寸法である。Si島のゲート長
方向の長さが上のＷであれば、ゲート長さLpは
ゲート長Lpの数倍以上大きいトランジスタでも
完全分離される。例えば、2μｍパタンルールで、
Lp＝2μｍ、Lc＝2μｍ、δ＝0.5μｍと仮定した場
合、Ｗは9μｍとなる。一方、Ａ図に示すように
完全分離されたSi島の厚さをｔ、多孔質シリコン
酸化膜の厚さをＴとすると、（2T−2t）＞Ｗが成
立するため、Ｗ＝9μｍ、ｔ＝0.5μｍとした場合、
Ｔ＞5μｍとなる。完全分離のためには多孔質シ
リコンがSi島の両側から十分にくつつく必要があ
るためＴとしては余裕をみて7μｍ程度が必要と
なる。 As shown in Figure 7A, completely separated Si island 3
A gate 5, a source 6, and a drain 7 are formed within the length W, and an electrode wiring 9, source 6, and drain 7 are brought into contact with an interlayer insulating film 8 deposited on the source 6 and drain 7. A through hole is drilled for this purpose. W shown in Figure 7A
indicates the gate length direction of the MOSFET, and the direction perpendicular to this W and perpendicular to the paper surface indicates the gate width direction. In a transistor where the gate width Wp is several times the gate length Lp or less, the width of the Si island in the gate width direction is smaller than the width of the Si island in the gate length direction.
The thickness of the porous silicon oxide film required for complete isolation is determined by the width of the Si island in the gate width direction. However, LSIs include transistors with various gate widths, and only one type of porous silicon oxide film thickness T is selected for each wafer to completely isolate these transistors.
Normally, the length W of the Si island that is completely separated is a=δ, b=
It is minimum when 2δ, and W={(Lp+2δ)+2(Lc+
2δ)}. Lp is the gate length, δ is the alignment accuracy of the gate and through hole with respect to Si island 3, Lc
is the size of the through-hole for the contact to the source or drain. If the length of the Si island in the gate length direction is W above, even a transistor whose gate length Lp is several times larger than the gate length Lp can be completely isolated. For example, with a 2μm pattern rule,
Assuming Lp=2 μm, Lc=2 μm, and δ=0.5 μm, W is 9 μm. On the other hand, as shown in Figure A, if the thickness of the completely separated Si island is t and the thickness of the porous silicon oxide film is T, then (2T-2t)>W holds, so W = 9 μm, t When = 0.5μm,
T>5μm. For complete separation, it is necessary for the porous silicon to be sufficiently penetrated from both sides of the Si island, so T needs to be approximately 7 μm with a margin.
この様に厚い多孔質シリコン酸化膜を形成した
場合、通常の酸化法では基板１のウエハのそりは
大きい。ケ・イマイその他（K.IMAI etal.）に
よつて文献１（IEEE Trans.on Electron
Devices、P.297、vol ED−31、No.3、1984）に
述べられているように、多孔質シリコンの酸化膜
厚が大きい程ウエハのそりは大きくなり、多孔質
シリコン酸化膜の膜厚が７〜8μｍの時、ウエハ
のそりは数十μｍから100μｍ程度と非常に大き
くなる。この場合、微細パタンの形成において合
わせズレの問題が生じたり、完全分離されたSi島
３にウエハのそりに起因して大きな応力が加わ
り、結晶欠陥が生じトランジスタの特性を劣化さ
せる。多孔質シリコン酸化膜厚が5μｍ程度以下
ならウエハのそりも数十μｍ以下に小さくなる
が、結晶欠陥の原因となるSi島に加わる応力の点
からみると、多孔質シリコン酸化膜の膜厚Ｔは
5μｍと言わず小さい程望ましいことは言うまで
もない。 When such a thick porous silicon oxide film is formed, the warpage of the wafer of the substrate 1 is large when a normal oxidation method is used. Reference 1 (IEEE Trans.on Electron) by K.IMAI etal.
Devices, P.297, vol ED−31, No.3, 1984), the larger the thickness of the porous silicon oxide film, the greater the wafer warpage; When is 7 to 8 μm, the warpage of the wafer becomes extremely large, ranging from several tens of μm to about 100 μm. In this case, a problem of misalignment occurs in the formation of a fine pattern, and a large stress is applied to the completely separated Si island 3 due to warpage of the wafer, causing crystal defects and deteriorating the characteristics of the transistor. If the thickness of the porous silicon oxide film is about 5 μm or less, the warpage of the wafer will be reduced to less than several tens of μm, but from the point of view of the stress applied to the Si islands that causes crystal defects, the thickness of the porous silicon oxide film T teeth
Needless to say, the smaller the diameter is, the more desirable it is, not just 5 μm.
多孔質シリコンの酸化法として高圧酸化法を用
いてウエハのそりを小さくする方法もあり、この
場合は厚い多孔質シリコン酸化膜でもウエハのそ
りを数十μｍ以下に小さくできる。しかしなが
ら、そり低減のメカニズムとしては、音居らによ
つて文献２（講演予稿集1a−Ｖ−４、59年度春季
応用物理学会）に述べられている様に、酸化の初
期あるいは酸化の程度が少ない状態での熱処理に
おいてはウエハは一度凸側に大きくそり酸化が進
むに伴つてそりは凹側へシフトし低減する。高圧
酸化法はこの様に結果としてはウエハのそりは小
さいが酸化の過程では一度大きいそりを経過して
いるため完全分離されたSi島はその時、応力をう
けて結晶欠陥を発生しトランジスタの特性劣化の
原因となる。この様にＡ図のFIPOS構造ではSi
島の長さが大きく多孔質シリコン酸化膜の完全分
離に必要な膜厚が大きいため、完全分離されたSi
島に結晶欠陥が多数発生するという欠点がある。 As a method of oxidizing porous silicon, there is a method of reducing the warpage of the wafer by using a high-pressure oxidation method, and in this case, even with a thick porous silicon oxide film, the warpage of the wafer can be reduced to several tens of micrometers or less. However, as described by Otoi et al. in Reference 2 (Presentation proceedings 1a-V-4, 1959 Spring Applied Physics Society), the mechanism of warpage reduction is the initial stage of oxidation or a small degree of oxidation. In the heat treatment under this condition, the wafer once has a large warp on the convex side, and as oxidation progresses, the warpage shifts to the concave side and is reduced. In this way, the high-pressure oxidation method results in a small warpage of the wafer, but since the wafer undergoes a large warpage once during the oxidation process, the completely separated Si islands are subjected to stress and crystal defects occur, resulting in the characteristics of the transistor. This may cause deterioration. In this way, in the FIPOS structure shown in Figure A, Si
Because the length of the island is large and the film thickness required for complete separation of the porous silicon oxide film is large, completely separated Si
The drawback is that many crystal defects occur in the islands.
又、Ａ図のFIPOS構造のトランジスタにおい
てはウエハのそりや結晶欠陥の問題でＷの値とし
ては約10μｍが上限の値である。従つてそれより
長さの大きなSi島を必要とするトランジスタでは
Ｂ図に示すような構造が採用されている。ただし
以下に述べる様にＢ図の寸法はＡ図の寸法には対
応していない。即ち、Ｂ図のＡ＞Ｗ，Ｅ＞Ｗと仮
定した場合、Si島の中に多孔質シリコン形成時の
化成用の窓１０，１１が設けられ、Ｂ図中のＣ，
Ｄ，ＥをともにＷより小さくしてSi島を完全に分
離する。Ｂ図から明らかなようにSi島が大きいパ
タンでは１０，１１のパタンの様な特別なパタン
の工夫がパタン設計上必要となる。Ａ，Ｂ図の
FIPOS構造がもつ欠点を除いた構造として第８
図Ａ，Ｂの構造が提案されている。図において１
２はSi基板、１３は多孔質シリコン酸化膜、１４
は１３によつて完全分離されたSi島を形成後、全
面にSi薄膜を堆積してレーザアニール等で全面を
単結晶化したSi層である。この１４のSi層にトラ
ンジスタを製作してＢ図を得る。Ｂ図において１
５は選択酸化膜、１６はシリコンゲート、１７は
ゲート酸化膜、１８は完全分離されたSi層、１９
は完全分離されたSi層に形成されたソース又はド
レイン、２０は層間絶縁膜、２１は電極配線であ
る。第８図Ａ，Ｂの製造方法には次の様な問題点
がある。即ち、Si薄層全面を単結晶化するため
に、Ａ図の構造をSi基板全面に欠陥なく作るこ
と、叉、Si薄層無いに単結晶粒界が生じないよう
にSi薄層全面を単結晶とすることが必要とされる
が、これを実現することはむずかしい。 Furthermore, in the FIPOS structure transistor shown in Figure A, the upper limit of the value of W is about 10 μm due to problems such as wafer warpage and crystal defects. Therefore, in transistors that require a longer Si island, a structure as shown in Figure B is adopted. However, as described below, the dimensions in Figure B do not correspond to the dimensions in Figure A. That is, assuming that A>W and E>W in figure B, windows 10 and 11 for chemical formation during the formation of porous silicon are provided in the Si island, and C,
Both D and E are made smaller than W to completely separate the Si islands. As is clear from Figure B, patterns with large Si islands require special pattern design such as patterns 10 and 11. A and B diagrams
The 8th structure eliminates the drawbacks of the FIPOS structure.
The structures shown in Figures A and B are proposed. In the figure 1
2 is a Si substrate, 13 is a porous silicon oxide film, 14
13 is a Si layer in which completely isolated Si islands are formed, a Si thin film is deposited on the entire surface, and the entire surface is made into a single crystal by laser annealing or the like. A transistor is fabricated on these 14 Si layers to obtain diagram B. In figure B, 1
5 is a selective oxide film, 16 is a silicon gate, 17 is a gate oxide film, 18 is a completely isolated Si layer, 19
2 is a source or drain formed in a completely isolated Si layer, 20 is an interlayer insulating film, and 21 is an electrode wiring. The manufacturing methods shown in FIGS. 8A and 8B have the following problems. In other words, in order to make the entire thin Si layer into a single crystal, the structure shown in Figure A must be made without defects on the entire Si substrate, and the entire thin Si layer must be made into a single crystal so that no single crystal grain boundaries occur in the thin Si layer. Although crystallization is required, this is difficult to achieve.
このように従来のFIPOS構造は完全分離され
たSi島内の結晶欠陥ウエハのそり、完全分離のた
めの特別なパタンの工夫の必要性等の問題があ
り、FIPOS基板へSi堆積した構造ではSi薄膜の全
面における単結晶性に問題があつた。 As described above, the conventional FIPOS structure has problems such as warpage of the crystal defective wafer in the completely isolated Si islands and the need to devise a special pattern for complete isolation. There was a problem with single crystallinity over the entire surface.
（問題点を解決するための手段）
本発明は上記の欠点を改善するために提案され
たもので、結晶欠陥の少ないSi島を形成し、Si島
内にMOSFETを形成して高密度で高速度なLSI
を実現することを目的とするもので、FIPOS構
造において、完全分離されたSi島の長さを、ゲー
トの長さにソース及びドレイン領域となる不純物
領域の最小限必要な長さを加えた大きさとするこ
とにより、完全分離のために必要な多孔質シリコ
ン酸化膜の膜厚を小さくできることを特徴とする
ものである。(Means for Solving the Problems) The present invention was proposed to improve the above-mentioned drawbacks, and it forms Si islands with few crystal defects, and forms MOSFETs in the Si islands to achieve high density and high speed operation. LSI
The aim is to achieve this by increasing the length of the completely isolated Si island in the FIPOS structure to the length of the gate plus the minimum required length of the impurity regions that will become the source and drain regions. By doing so, the thickness of the porous silicon oxide film required for complete separation can be reduced.
次に本発明の実施例を説明する。なお実施例は
一つの例示であつて、本発明の精神を逸脱しない
範囲で、種々の変更あるいは改良を行いうること
は言うまでもない。 Next, examples of the present invention will be described. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.
第１図Ａ〜Ｅは本発明の半導体装置およびその
製造方法の実施例を示すものであつて、多孔質シ
リコン酸化膜によつて完全分離されたSi島領域及
び多孔質シリコン酸化膜領域の上にエピタキシヤ
ルSiを成長させ、上記のSi島領域とその上に成長
させたエピタキシヤルSi領域にチヤネルが形成さ
れる単結晶領域と、ソース及びドレインの接合面
とがつくり込まれる。第１図Ａは半導体基板２２
に多孔質シリコン酸化膜２３によつて完全分離さ
れた単結晶Si領域２４を形成して得られる。この
上にSi薄膜をSiH4をソースガスとしたエピタキ
シヤル成長あるいはSi分子線エピタキシヤル成長
などの方法によつて堆積し、Ｂ図を得る。２５は
単結晶領域２４の上にエピタキシヤルSiが成長し
た単結晶領域であり、２６は多孔質シリコン酸化
膜２３の上に堆積した多結晶Si膜である。素子領
域を除く領域を選択的に酸化して形成した酸化膜
２８によつて素子間を分離し、ゲート酸化膜２７
を形成した後、シリコンゲート２９を形成してＣ
図を得る。多孔質Si酸化膜２３の厚さをＴ、完全
分離されたSi領域２４の厚さをｔ、長さをＷ、シ
リコンゲート２９のパタン上のゲート長をLp、
シリコンゲート２９のSi領域２４に対する合わせ
精度を±δとした場合、（2T−2t）＞Ｗであり、
Ｗ＝（Lp＋2δ）が成立する。ただし、Ｃ図中で０
＜ε＜2δである。2μｍルールを仮定し、Lp＝2μ
ｍ、δ＝0.5μｍ、ｔ＝0.5μｍとした場合、Ｗ＝3μ
ｍとなり、Ｔ＞2μｍとなる。完全分離のために
Ｔとしては余裕が必要で、Ｔとして3μｍ程度が
必要となる。Ｃ図の構造にセルフアラインでイオ
ン注入によりソース、ドレインの不純物を注入し
て熱処理して不純物を活性化してソース３２，３
３、ドレイン３４，３５を形成する。しかる後、
層間絶縁膜３０を堆積し、ソース、ドレインへの
コンタクトホールを形成し、電極配線３１を形成
してＤ図を得る。Ｅ図にＣ図の平面パタンを示
す。一点鎖線３６，３７での断面構造がＣ図であ
る。第７図Ａの構造と比較した場合、Ｗが第７図
Ａに比べて第１図の構造は（2Lc＋4δ）だけ小さ
くなり、そのため第１図の構造はＴを非常に薄く
できる。 FIGS. 1A to 1E show an embodiment of the semiconductor device and its manufacturing method of the present invention, and show the tops of Si island regions and porous silicon oxide film regions completely separated by a porous silicon oxide film. Epitaxial Si is grown to form the Si island region, a single crystal region in which a channel is formed in the epitaxial Si region grown thereon, and a source/drain junction surface. FIG. 1A shows a semiconductor substrate 22
This is obtained by forming single crystal Si regions 24 completely separated by a porous silicon oxide film 23. A Si thin film is deposited thereon by a method such as epitaxial growth using SiH 4 as a source gas or Si molecular beam epitaxial growth to obtain diagram B. 25 is a single crystal region in which epitaxial Si is grown on the single crystal region 24, and 26 is a polycrystalline Si film deposited on the porous silicon oxide film 23. The devices are separated by an oxide film 28 formed by selectively oxidizing regions other than the device region, and a gate oxide film 27 is formed.
After forming C, a silicon gate 29 is formed and C
Get the picture. The thickness of the porous Si oxide film 23 is T, the thickness of the completely isolated Si region 24 is t, the length is W, and the gate length on the pattern of the silicon gate 29 is Lp.
When the alignment accuracy of the silicon gate 29 with respect to the Si region 24 is ±δ, (2T−2t)>W,
W=(Lp+2δ) holds true. However, in diagram C, 0
<ε<2δ. Assuming 2μm rule, Lp=2μ
When m, δ = 0.5μm, t = 0.5μm, W = 3μ
m, and T>2 μm. For complete separation, a margin of T is required, and T is approximately 3 μm. Source and drain impurities are implanted by self-aligned ion implantation into the structure shown in Figure C, and the impurities are activated by heat treatment to form sources 32 and 3.
3. Form drains 34 and 35. After that,
An interlayer insulating film 30 is deposited, contact holes to the source and drain are formed, and electrode wiring 31 is formed to obtain diagram D. Figure E shows the plane pattern of Figure C. The cross-sectional structure along dashed-dotted lines 36 and 37 is shown in Fig. C. When compared to the structure of FIG. 7A, W is smaller in the structure of FIG. 1 by (2L c +4δ) than in FIG. 7A, so the structure of FIG. 1 allows T to be made very thin.
第２図Ａ〜Ｃ、第３図Ａ〜Ｂは第１図Ｂ〜Ｃの
プロセスにおいてエピタキシヤルSi薄膜の単結晶
領域を種々変えた場合の適用可能な例である。第
２図Ａはラテラルエピタキシーによつて単結晶領
域３６を矢印の方向へ拡大してＢ図に示すように
大きな単結晶領域３８を得、３８以外の領域３９
を選択酸化することによつてＣ図を得る。この構
造にした場合、ゲート酸化膜２７を形成した時２
７は全面で一様な膜厚となる利点がある。第３図
Ａ，Ｂは単結晶化の拡大を素子領域全面とせず、
その一部４０のみにとどめた例である。この場
合、ラテラルエピタキシーの距離が第２図Ｂより
も短いため、第２図Ｂに比べてラテラルエピタキ
シーの時間も短時間で済み、技術的にも容易にな
る。 2A to 3C and 3A to 3B are applicable examples in which the single crystal region of the epitaxial Si thin film is variously changed in the process of FIGS. 1B to C. In FIG. 2A, a single crystal region 36 is expanded in the direction of the arrow by lateral epitaxy to obtain a large single crystal region 38 as shown in FIG.
Figure C is obtained by selectively oxidizing. In this structure, when the gate oxide film 27 is formed, 2
No. 7 has the advantage of having a uniform film thickness over the entire surface. In Figures 3A and 3B, single crystallization is not expanded to cover the entire device area;
This is an example in which only a portion of 40 is included. In this case, since the distance of lateral epitaxy is shorter than that in FIG. 2B, the time required for lateral epitaxy is shorter than that in FIG. 2B, and it is technically easier.
第４図Ａ〜Ｄに、第１図〜第３図で述べたよう
なSi薄膜の堆積を利用せずセルフアラインコンタ
クト技術を適用した例を示す。この方法を用いた
場合でも、第１図Ｃと同様の考え方が成り立ち
（2T−2t）＞ＷでありＷ＝（Lp＋2δ＋2d）の関係が
満足されている。ただしｄは、完全分離されたSi
島内にゲートに対してセルフアライメントに配置
されたソース、ドレインへの各々の取り出し電極
のコンタクトの長さである。Si基板５３上に多孔
質Si酸化膜５４によつて完全分離された単結晶Si
領域の島５５を形成する。島５５の上にゲート酸
化膜５６、シリコンゲート５７を形成し、パタン
形成したシリコンゲート５７をマスクにして露出
したゲート酸化膜５６をエツチングして除去し、
第４図Ａを得る。各寸法ｔ，Ｔ，Ｗ，Lp，δは
第１図Ｃと同一の定義である。ただし、０＜ε＜
2δである。たとえば2μｍルールでLp＝2μｍ、δ
＝ｄ＝0.5μｍとした場合Ｗ＝4μｍとなり、Ｔ＞
2.5μｍとなる。Ｔとして余裕をみて3.5μｍ程度が
必要となる。Ａ図を熱酸化して、再び酸化膜を単
結晶領域５５が露出する程度にエツチングした
後、全面に多結晶Si５８を堆積してＢ図を得る。
この場合、多結晶Si５７の方が単結晶Si５５より
酸化速度が大きいことを利用してＢ図に示すよう
に多結晶Si５９の周囲に熱酸化膜を残す。多結晶
Si５８をパタン形成し、予め不純物を含有する多
結晶Si５８から島５５の中へ不純物拡散させるこ
とによつてソース６０、ドレイン６１を形成し、
Ｃ図を得る。この上に層間絶縁膜６２、コンタク
トホール、電極配線６３を形成してＤ図を得る。
Ｄ図の製作方法はこの様に、Siのエピタキシヤル
技術は使用しなくてすむ代わりに、セルフアライ
ンコンタクト技術を使用する。第４図Ｄの構造を
第７図Ａの構造と比較した場合、Ｗが第７図Ａに
比べて、（2Lc＋4δ−2d）だけ小さくなり、その
ため第４図Ｄの構造はＴを第７図Ａよりもうすく
でき、結晶欠陥の少ないSi島となる。又、第１図
と比較した場合、Ｔは少し大きくなるがエピタキ
シヤルSiが不要な分だけプロセスが容易である。 FIGS. 4A to 4D show an example in which the self-aligned contact technique is applied without using the Si thin film deposition as described in FIGS. 1 to 3. Even when this method is used, the same concept as in FIG. However, d is completely separated Si
This is the length of each lead-out electrode contact to the source and drain arranged in self-alignment with respect to the gate within the island. Single crystal Si completely separated by a porous Si oxide film 54 on a Si substrate 53
An island 55 of regions is formed. A gate oxide film 56 and a silicon gate 57 are formed on the island 55, and the exposed gate oxide film 56 is removed by etching using the patterned silicon gate 57 as a mask.
Figure 4A is obtained. The dimensions t, T, W, Lp, and δ have the same definition as in FIG. 1C. However, 0<ε<
2δ. For example, in the 2μm rule, Lp = 2μm, δ
If = d = 0.5 μm, W = 4 μm, and T >
It becomes 2.5 μm. Considering T, a margin of about 3.5 μm is required. Figure A is thermally oxidized, the oxide film is etched again to the extent that the single crystal region 55 is exposed, and then polycrystalline Si 58 is deposited on the entire surface to obtain Figure B.
In this case, taking advantage of the fact that polycrystalline Si 57 has a higher oxidation rate than single-crystalline Si 55, a thermal oxide film is left around polycrystalline Si 59 as shown in Figure B. polycrystalline
A source 60 and a drain 61 are formed by patterning Si 58 and diffusing impurities from polycrystalline Si 58 containing impurities into the islands 55,
Obtain diagram C. On this, an interlayer insulating film 62, contact holes, and electrode wiring 63 are formed to obtain diagram D.
In this way, the manufacturing method shown in Figure D does not require the use of Si epitaxial technology, but instead uses self-aligned contact technology. When comparing the structure of FIG. 4D with the structure of FIG. 7A, W is smaller by (2L c +4δ−2d) than that of FIG. The Si island can be made thinner than that shown in Figure 7A and has fewer crystal defects. Also, when compared with FIG. 1, although T is a little larger, the process is easier because epitaxial Si is not required.
第５図Ａ〜Ｅに、ポリSiの代りに方向性のある
膜堆積法によつてアモルフアスSi膜を堆積してセ
ルフアラインコンタクトを行なつた例を示す。第
５図Ａは第４図ＢにおけるポリSiの堆積前の工程
まで進めた構造である。この上にECR型プラズ
マ堆積法、SiMBE、あるいはイオンビームスパ
ツタ法等の方向性を有する膜堆積法によつて、基
板を比較的低温に保つてアモルフアスSi膜６５を
堆積してＢ図を得る。シリコンゲートである多結
晶Si５９の段差側壁に堆積したアモルフアスSi膜
は脆弱な膜質のためスライトエツチングによつて
容易に除去され、平坦な部分にのみアモルフアス
Si膜６５が残る。全面に有機系レジスト６６を塗
布し、これを酸素RIEで平坦部分のレジスト６６
が消滅する程度にエツチングした後、再度レジス
ト６７を塗布してシリコンゲート５９のパタンの
反転パタンを６７に形成してＣ図を得る。ここで
反転パタンを使用する代わりにレジストをネガか
らポジへ変えてもよい。アツシングによつてレジ
スト６７と６６を除去した後、熱処理によつてア
モルフアスSi６５中の不純物を５５の中へ拡散し
てソース６８、ドレイン６９を形成する。ソー
ス、ドレインのレジストパタン７０を形成してＤ
図を得る。この熱処理によつてアモルフアスSi６
５は多結晶Siに変わる。７０をマスクにして多結
晶Si６５をエツチングし、層間絶縁膜７１を堆積
し、コンタクトホールを形成後、電極配線７２を
形成してＥ図を得る。第５図Ａ〜Ｅの方法は第４
図Ｃにおける５８のパタン形成を避けられるため
製作技術が容易となる。 FIGS. 5A to 5E show an example in which an amorphous Si film is deposited by a directional film deposition method instead of poly-Si to form a self-aligned contact. FIG. 5A shows a structure in which the process in FIG. 4B has been advanced up to the step before poly-Si deposition. On top of this, an amorphous Si film 65 is deposited by a directional film deposition method such as ECR type plasma deposition method, SiMBE, or ion beam sputtering method while keeping the substrate at a relatively low temperature to obtain diagram B. . The amorphous Si film deposited on the stepped sidewalls of the polycrystalline Si 59, which is the silicon gate, is a fragile film and is easily removed by light etching.
A Si film 65 remains. An organic resist 66 is applied to the entire surface, and then the flat parts of the resist 66 are coated using oxygen RIE.
After etching is performed to such an extent that the resist 67 disappears, a resist 67 is applied again to form a pattern 67 that is the inverse of the pattern of the silicon gate 59, thereby obtaining diagram C. Instead of using an inversion pattern here, the resist may be changed from negative to positive. After resists 67 and 66 are removed by ashes, impurities in the amorphous Si 65 are diffused into the amorphous Si 55 by heat treatment to form a source 68 and a drain 69. A source and drain resist pattern 70 is formed and D
Get the picture. Through this heat treatment, amorphous Si6
5 changes to polycrystalline Si. Using 70 as a mask, polycrystalline Si 65 is etched, interlayer insulating film 71 is deposited, contact holes are formed, and electrode wiring 72 is formed to obtain diagram E. The methods shown in Figure 5 A to E are the 4th method.
Since the formation of the pattern 58 in FIG. C can be avoided, the manufacturing technology becomes easier.
第６図Ａ〜Ｅに第５図Ａ〜Ｅと同様、方向性の
ある膜堆積法を利用した方法を示す。第６図Ａ〜
Ｅの方法は第４図Ａ〜Ｅの方法に比べて露光工程
が１回少なくなり工程が簡単になる長所をもつ
が、ソースドレインのパタンとシリコンゲートの
パタンの形成が各々独立に決定できないという欠
点をもつ。第４図Ａと同様の工程で第６図Ａを得
る。この上に第５図Ａ〜Ｂと同様、方向性のある
膜堆積法によつてアモルフアスSi７５を堆積して
第６図Ｂを得る。シリコンゲート７４の段差側壁
に堆積したアモルフアスSi膜は脆弱な膜質をもち
酸化速度は平坦な領域のアモルフアスSi膜よりも
非常に大きいため、適当な熱酸化条件で、平坦な
部分に堆積したアモルフアスSiをわずか酸化する
のみで段差側壁のアモルフアスSiを熱酸化膜７６
に変えてＣ図を得る。この場合、アモルフアスSi
は多結晶Siに変わると同時に、アモルフアスSi中
に導入した不純物が単結晶Si領域５５中へ拡散
し、ソース７７、ドレイン７８が形成されてＤ図
を得る。層間絶縁膜７９、コンタクトホール、電
極配線８０を形成してＥ図を得る。 Similar to FIGS. 5A to 5E, FIGS. 6A to 6E show a method using a directional film deposition method. Figure 6 A~
Method E has the advantage of simplifying the process by requiring one less exposure step than the methods shown in FIGS. 4A to E, but it has the disadvantage that the formation of the source-drain pattern and the silicon gate pattern cannot be determined independently. have shortcomings. FIG. 6A is obtained by the same process as FIG. 4A. Amorphous Si 75 is deposited thereon by a directional film deposition method, as in FIGS. 5A to 5B, to obtain the structure shown in FIG. 6B. The amorphous Si film deposited on the step sidewall of the silicon gate 74 has a fragile film quality and the oxidation rate is much higher than that of the amorphous Si film on the flat area. Therefore, under appropriate thermal oxidation conditions, the amorphous Si film deposited on the flat area Thermal oxide film 76 is applied to the amorphous Si on the step sidewall by slightly oxidizing the
to obtain diagram C. In this case, amorphous Si
At the same time as changing into polycrystalline Si, the impurity introduced into the amorphous Si diffuses into the single crystal Si region 55, forming a source 77 and a drain 78 to obtain diagram D. An interlayer insulating film 79, contact holes, and electrode wiring 80 are formed to obtain diagram E.
（発明の効果）
以上説明した様に、本発明による方法は、多孔
質シリコンの酸化膜厚を薄くできるため従来の
FIPOS技術にみられたウエハのそりや結晶欠陥
を低減でき、又、ゲート長さが大きいトランジス
タに対しても特別なパタンを必要としないという
利点をもつ。応用分野としては、高速度大容量な
CMOSLSIに適している。(Effects of the Invention) As explained above, the method according to the present invention can reduce the thickness of the oxide film on porous silicon, making it possible to reduce the thickness of the oxide film on porous silicon.
It has the advantage of reducing wafer warpage and crystal defects seen in FIPOS technology, and does not require special patterns even for transistors with large gate lengths. Application fields include high-speed, large-capacity
Suitable for CMOS LSI.
第１図〜第３図はエピタキシヤルSi層を用いた
本発明の半導体装置とその製造方法の実施例、第
４図〜第６図はセルフアラインコンタクト技術を
用いた本発明の実施例、第７図は従来のFIPOS
構造の半導体装置、第８図は従来のラテラルエピ
タキシヤルSi層を用いたFIPOSの応用例を示す。
１……Si基板、２……多孔質シリコン酸化膜、
３……完全分離されたSi島のチヤネルが生成され
る領域、４……ゲート酸化膜、５……多結晶Siゲ
ート、６……ソース、７……ドレイン、８……層
間絶縁膜、９……電極配線、１０，１１……穴あ
きパタン、１２……Si基板、１３……多孔質シリ
コン酸化膜、１４……１３によつてSi島を形成
後、全面にSi薄膜を堆積してレーザーアニール等
で全面を単結晶化したSi層、１５……選択酸化
膜、１６……シリコンゲート、１７……ゲート酸
化膜、１８……完全分離されたSi層、１９……ソ
ース又はドレイン、２０……層間絶縁膜、２１…
…電極配線、２２……半導体基板、２３……多孔
質シリコン酸化膜、２４……単結晶領域、２５…
…２４の上にエピタキシヤルSiが成長した単結晶
領域、２６……２３の上に堆積した多結晶Si膜、
２７……ゲート酸化膜、２８……選択酸化膜、２
９……シリコンゲート、３０……層間絶縁膜、３
１……電極配線、３２，３３……ソース、３４，
３５……ドレイン、３８……単結晶領域、３９…
…３８以外のSi領域、４０……単結晶領域、４１
……４０以外のSi領域、５３……Si基板、５４…
…多孔質シリコン酸化膜、５５……完全分離され
たSi島、５６……ゲート酸化膜、５７……シリコ
ンゲート、５８……多結晶Si、５９……多結晶
Si、６０……ソース、６１……ドレイン、６２…
…層間絶縁膜、６３……電極配線、６４……多結
晶Siの酸化膜、６５……アモルフアスSi膜、６６
……レジスト、６７……レジスト、６８……ソー
ス、６９……ドレイン、７０……マスク、７１…
…層間絶縁膜、７２……電極配線、７３……ゲー
ト酸化膜、７４……シリコンゲート、７５……ア
モルフアスSi膜、７６……熱酸化膜、７７……ソ
ース、７８……ドレイン、７９……層間絶縁膜、
８０……電極配線。
1 to 3 show an embodiment of the semiconductor device of the present invention using an epitaxial Si layer and its manufacturing method, and FIGS. 4 to 6 show an embodiment of the present invention using self-aligned contact technology. Figure 7 shows conventional FIPOS
FIG. 8 shows an example of the application of FIPOS using a conventional lateral epitaxial Si layer. 1...Si substrate, 2...porous silicon oxide film,
3...A region where a completely isolated Si island channel is generated, 4...Gate oxide film, 5...Polycrystalline Si gate, 6...Source, 7...Drain, 8...Interlayer insulating film, 9 ... Electrode wiring, 10, 11 ... Hole pattern, 12 ... Si substrate, 13 ... Porous silicon oxide film, 14 ... After forming a Si island with 13, a Si thin film was deposited on the entire surface. Si layer whose entire surface is made into a single crystal by laser annealing, etc., 15... selective oxide film, 16... silicon gate, 17... gate oxide film, 18... completely separated Si layer, 19... source or drain, 20... interlayer insulating film, 21...
... Electrode wiring, 22 ... Semiconductor substrate, 23 ... Porous silicon oxide film, 24 ... Single crystal region, 25 ...
... a single crystal region in which epitaxial Si is grown on 24, a polycrystalline Si film deposited on 26 ... 23,
27... Gate oxide film, 28... Selective oxide film, 2
9...Silicon gate, 30...Interlayer insulating film, 3
1... Electrode wiring, 32, 33... Source, 34,
35...Drain, 38...Single crystal region, 39...
...Si region other than 38, 40... Single crystal region, 41
...Si region other than 40, 53...Si substrate, 54...
... Porous silicon oxide film, 55 ... Completely isolated Si island, 56 ... Gate oxide film, 57 ... Silicon gate, 58 ... Polycrystalline Si, 59 ... Polycrystalline
Si, 60...source, 61...drain, 62...
...Interlayer insulating film, 63... Electrode wiring, 64... Polycrystalline Si oxide film, 65... Amorphous Si film, 66
...Resist, 67...Resist, 68...Source, 69...Drain, 70...Mask, 71...
... Interlayer insulating film, 72 ... Electrode wiring, 73 ... Gate oxide film, 74 ... Silicon gate, 75 ... Amorphous Si film, 76 ... Thermal oxide film, 77 ... Source, 78 ... Drain, 79 ... ...interlayer insulating film,
80...Electrode wiring.
Claims (1)
を有する半導体基板上にSi薄膜が存在し、少なく
とも該Si島に接してその上方に存在する該Si薄膜
が単結晶Siであり、該Si島と該単結晶Siとからな
るSi領域にMOSFETが形成された半導体装置に
おいて、該Si島と該単結晶SiとからなるSi領域に
該MOSFETのゲートに対してセルフアライメン
トにソースおよびドレインが配置され、ゲート長
方向の該Si島の長さが、ゲート長と、該Si島に対
するゲートの合わせ精度の寸法とを加えた長さに
設定されていることを特徴とする半導体装置。 ２ 多孔質シリコン酸化膜によつて半導体基板か
ら完全分離されたSi島を形成する工程と、該半導
体基板上にSi薄膜を堆積する工程と、少なくとも
該Si島に接触してその上方に堆積されたSi薄膜の
領域を単結晶化する工程と、該Si薄膜内の該単結
晶化領域にゲート酸化膜を形成する工程と、該単
結晶化領域の長さよりも小さいゲート長をもつゲ
ート電極を該単結晶化領域内に設ける工程と、こ
のゲート電極とセルフアライメントでソース、ド
レインを該単結晶化領域内に形成する工程とを具
備し、ソースドレインの接合面を該単結晶化領域
内に設けることを特徴とする半導体装置の製造方
法。[Claims] 1. A Si thin film is present on a semiconductor substrate having Si islands completely separated by a porous Si oxide film, and at least the Si thin film that is in contact with and above the Si islands is monolithic. In a semiconductor device in which a MOSFET is formed in a Si region made of crystalline Si and made up of the Si island and the single crystal Si, a self-contained MOSFET is formed in the Si region made of the Si island and the single crystal Si with respect to the gate of the MOSFET. A source and a drain are arranged in alignment, and the length of the Si island in the gate length direction is set to the sum of the gate length and the alignment accuracy dimension of the gate with respect to the Si island. semiconductor devices. 2. A step of forming a Si island completely separated from a semiconductor substrate by a porous silicon oxide film, a step of depositing a Si thin film on the semiconductor substrate, and a step of depositing a Si thin film in contact with at least the Si island and above it. a step of forming a gate oxide film in the single crystallized region in the Si thin film; and a step of forming a gate electrode having a gate length smaller than the length of the single crystallized region. a step of forming a source and a drain in the single crystallized region in self-alignment with the gate electrode; A method of manufacturing a semiconductor device, comprising: providing a semiconductor device;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21515584A JPS6194367A (en) | 1984-10-16 | 1984-10-16 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21515584A JPS6194367A (en) | 1984-10-16 | 1984-10-16 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6194367A JPS6194367A (en) | 1986-05-13 |
| JPH0546706B2 true JPH0546706B2 (en) | 1993-07-14 |
Family
ID=16667572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21515584A Granted JPS6194367A (en) | 1984-10-16 | 1984-10-16 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6194367A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3191061B2 (en) * | 1992-01-31 | 2001-07-23 | キヤノン株式会社 | Semiconductor device and liquid crystal display device |
| US5434441A (en) * | 1992-01-31 | 1995-07-18 | Canon Kabushiki Kaisha | Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness |
| JP2000307112A (en) | 1999-04-26 | 2000-11-02 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5317286A (en) * | 1976-07-31 | 1978-02-17 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS57113252A (en) * | 1980-12-29 | 1982-07-14 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPS57167677A (en) * | 1981-03-31 | 1982-10-15 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
-
1984
- 1984-10-16 JP JP21515584A patent/JPS6194367A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5317286A (en) * | 1976-07-31 | 1978-02-17 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS57113252A (en) * | 1980-12-29 | 1982-07-14 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPS57167677A (en) * | 1981-03-31 | 1982-10-15 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6194367A (en) | 1986-05-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |