JPH0542137B2 - - Google Patents
Info
- Publication number
- JPH0542137B2 JPH0542137B2 JP13713487A JP13713487A JPH0542137B2 JP H0542137 B2 JPH0542137 B2 JP H0542137B2 JP 13713487 A JP13713487 A JP 13713487A JP 13713487 A JP13713487 A JP 13713487A JP H0542137 B2 JPH0542137 B2 JP H0542137B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- thin film
- source
- drain
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 239000010409 thin film Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910021645 metal ion Inorganic materials 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 239000011521 glass Substances 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 4
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 4
- 239000005297 pyrex Substances 0.000 description 4
- 239000012298 atmosphere Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005984 hydrogenation reaction Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は集積回路、アクテイブマトリツクス
デイスプレイなどに応用される、多結晶シリコン
薄膜を半導体活性層とする薄膜トランジスタに関
し、特に、駆動力が大きく、高速動作可能な薄膜
トランジスタの製造方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to thin film transistors having a polycrystalline silicon thin film as a semiconductor active layer, which are applied to integrated circuits, active matrix displays, etc. The present invention relates to a method of manufacturing a thin film transistor capable of high-speed operation.
［従来の技術］
薄膜トランジスタをアクテイブマトリツクス方
式の液晶デイスプレイ用駆動素子として大画面の
情報端末やTV用に適用する場合、あるいは、集
積回路、特に三次元LSIへ適用する場合、以下に
列挙するような点が要請される。[Prior Art] When thin film transistors are used as drive elements for active matrix liquid crystal displays in large-screen information terminals and TVs, or when applied to integrated circuits, especially three-dimensional LSIs, the following methods are used: The following points are requested.
(i) 多結晶トランジスタは単結晶トランジスタと
比較してキヤリア移動度が小さいために、素子
の駆動能力が低く、高速動作を確保しにくい。
したがつて、ソース、ドレインおよびゲート部
分の抵抗を低くする必要がある。(i) Polycrystalline transistors have lower carrier mobility than single-crystalline transistors, so the driving ability of the device is lower, making it difficult to ensure high-speed operation.
Therefore, it is necessary to reduce the resistance of the source, drain, and gate portions.
(ii) 安価であるという特徴を生かすために、フオ
トマスク数が少なく、プロセスが簡単である必
要がある。(ii) In order to take advantage of the low cost, the number of photomasks needed is small and the process needs to be simple.
(iii) 三次元LSIへの適用の場合は、下層の素子を
破壊、変質させないため、アクテイブマトリツ
クスへの適用の場合は基板ガラスを変形させな
いためにプロセス温度は低い方が望ましい。(iii) When applied to three-dimensional LSIs, it is desirable that the process temperature be low so as not to destroy or alter the underlying elements, and when applied to active matrices, so as not to deform the substrate glass.
(iv) 再現性を確保するために、セルフアライン方
式であることが望ましい。(iv) In order to ensure reproducibility, a self-aligning method is preferable.
(v) 多結晶シリコントランジスタの場合、多結晶
シリコン中のダングリングボンドを終端するた
め、水素化を行なう必要があるが、ゲートが厚
いと水素が入りにくい。したがつて、ゲートは
薄く、かつ水素の透過しやすい物質で構成する
必要がある。(v) In the case of polycrystalline silicon transistors, it is necessary to perform hydrogenation to terminate dangling bonds in the polycrystalline silicon, but if the gate is thick, it is difficult for hydrogen to enter. Therefore, the gate needs to be thin and made of a material that allows hydrogen to easily permeate.
これら要求を満たすため、次に示すような先行
技術があつた。 In order to meet these demands, the following prior art has been developed.
第３図は1986年秋期応用物理学界学術講演会予
稿集27P−Ｑ−９に示されたPtSiのソースドレイ
ン構造を有する多結晶シリコントランジスタの断
面構造である。 FIG. 3 is a cross-sectional structure of a polycrystalline silicon transistor having a PtSi source-drain structure shown in Proceedings of the 1986 Fall Academic Conference on Applied Physics 27P-Q-9.
図において１１は基板、１２は多結晶シリコン
膜１３はシリコン酸化膜、１４は電極、１５はゲ
ートキヤツプ、１６はPSGの保護膜、１７は配
線である。 In the figure, 11 is a substrate, 12 is a polycrystalline silicon film 13, a silicon oxide film, 14 is an electrode, 15 is a gate cap, 16 is a PSG protective film, and 17 is a wiring.
従来技術によれば、PtSiとSiのシヨツトキー接
合を用いるため、ソース、ドレイン部へのＰ型不
純物注入工程が不要であり、かつ、低抵抗なため
高速動作の妨げにならないという利点があつた。 According to the conventional technology, since a Schottky junction of PtSi and Si is used, there is no need for a step of implanting P-type impurities into the source and drain regions, and the low resistance does not interfere with high-speed operation.
［発明が解決しようとする問題点］
従来のサリサイド（Self Align Siliside）構造
を応用した多結晶シリコン薄膜トランジスタは以
上のように構成されているので、以下に示すよう
な問題点がある。[Problems to be Solved by the Invention] Since the polycrystalline silicon thin film transistor using the conventional salicide (self-aligned silicide) structure is configured as described above, it has the following problems.
(i) 水素化を容易にするため、ゲートとなる多結
晶シリコンを薄くしなければならないが、ゲー
トが薄いとサイドウオール構造を採用しにく
い。その結果、ソース、ドレイン部のPtSiとゲ
ート部PtSiが短絡するような欠陥が生じやす
い。(i) To facilitate hydrogenation, the polycrystalline silicon that serves as the gate must be made thin, but a thin gate makes it difficult to adopt a sidewall structure. As a result, defects such as a short circuit between PtSi in the source and drain portions and PtSi in the gate portion are likely to occur.
(ii) 水素化が容易で、かつSiとシヨツトキー接合
を形成するようシリサイドを形成する金属とし
ては、Pt，Pdなどが考えられるが、これらの
スパツタターゲツトは極めて高価である。な
お、プロセスの上からは、未反応の金属を選択
エツチング液でエツチング除去し、洗浄するウ
エツト工程が必要で、資源の有効活用の観点か
らもコストの面からも得策ではない。(ii) Pt, Pd, and the like are conceivable metals that can be easily hydrogenated and form silicides to form Schottky junctions with Si, but these sputter targets are extremely expensive. In addition, from the top of the process, a wet step is required to remove unreacted metal by etching with a selective etching solution and cleaning, which is not a good idea from the viewpoint of effective utilization of resources and from the viewpoint of cost.
この発明は以上述べたような問題点を解消する
ためになされたもので、高速動作可能で低コスト
かつ再現性、歩留りの優れた薄膜トランジスタの
製造方法を得ることを目的としている。 The present invention has been made to solve the above-mentioned problems, and aims to provide a method for manufacturing a thin film transistor that can operate at high speed, is low in cost, and has excellent reproducibility and yield.
［問題点を解決するための手段］
この発明に係る薄膜トランジスタの製造方法
は、Siとシリサイドを形成し、かつSiと前記シリ
サイドとの接合がシヨツトキー接合となるような
金属を、イオン化、加速して多結晶シリコン膜に
注入することによつてゲート、ソース、ドレイン
部分を形成する。この後に300℃〜800℃程度の比
較的低温のアニールを行ない、被注入金属をシリ
サイド化することによつてゲート、ソース、ドレ
イン部を形成したものである。[Means for Solving the Problems] A method for manufacturing a thin film transistor according to the present invention includes ionizing and accelerating a metal that forms silicide with Si and forms a Schottky junction between Si and the silicide. The gate, source, and drain portions are formed by implanting into the polycrystalline silicon film. After this, annealing is performed at a relatively low temperature of about 300° C. to 800° C. to silicide the implanted metal, thereby forming the gate, source, and drain portions.
［作用］
この発明に係る薄膜トランジスタの製造方法
は、シリサイドを形成する金属をイオン注入法を
用いて注入しているセルフアラインプロセスであ
るため、ソース、ドレイン部と、ゲートとの短絡
による歩留り低下が理論的に生じない。また、選
択エツチング洗浄等のウエツト工程が不要で、使
用する金属も少量で済む。またシリサイド化され
たソース、ドレイン、ゲート部等は、不純物イオ
ン注入によつて形成した導電層よりも低抵抗で、
配線としても使用できる。[Function] Since the method for manufacturing a thin film transistor according to the present invention is a self-alignment process in which the metal that forms silicide is implanted using an ion implantation method, there is no reduction in yield due to short circuits between the source/drain portion and the gate. Theoretically it does not occur. Further, a wet process such as selective etching cleaning is not necessary, and only a small amount of metal can be used. In addition, the silicided source, drain, gate, etc. have lower resistance than conductive layers formed by impurity ion implantation.
It can also be used as wiring.
［発明の実施例］
以下、この発明の一実施例をガラス上に形成し
た低温プロセス薄膜トランジスタを用いて図につ
いて説明する。[Embodiments of the Invention] Hereinafter, an embodiment of the present invention will be explained with reference to the drawings using a low-temperature process thin film transistor formed on glass.
第１図ａ〜ｆはこの発明に係る多結晶シリコン
薄膜トランジスタの製造プロセスを示した図であ
る。 FIGS. 1a to 1f are diagrams showing a manufacturing process of a polycrystalline silicon thin film transistor according to the present invention.
基板１は絶縁物質であるパイレツクスガラスで
ある。第１図ａに示すように有機洗浄および酸洗
浄したパイレツクスガラス基板１上面に、真空蒸
着法により多結晶シリコン薄膜２を蒸着し、パタ
ーニングを行なつた。多結晶シリコン薄膜２の形
成は、基板温度500℃、真空度１×10-5Pa、成膜
速度１Å／secの条件で行ない、形成された膜厚
は500Åであつた。次いで第１図ｂに示すように
常圧CVD法により基板温度420℃でゲート絶縁膜
となるシリコン酸化膜３を500Å堆積した。酸素
雰囲気中500℃で２時間のアニールを行ない、次
いで酸素プラズマを基板温度400℃で30分間照射
する。このときの酸素プラズマの出力は
150mW／cm3である。次いで第１図ｃのごとく、
前述と同一の条件による真空蒸着法により多結晶
シリコン膜４を1000Å堆積した後、この上に常圧
CVD法でシリコン酸化膜５を500Å堆積した。こ
れらをRIE法を用いて引き続きパターニングして
ゲート電極を形成した。 The substrate 1 is made of Pyrex glass, which is an insulating material. As shown in FIG. 1a, a polycrystalline silicon thin film 2 was deposited by vacuum evaporation on the top surface of a Pyrex glass substrate 1 which had been organically and acid-washed, and patterned. The polycrystalline silicon thin film 2 was formed under conditions of a substrate temperature of 500° C., a degree of vacuum of 1×10 −5 Pa, and a deposition rate of 1 Å/sec, and the formed film thickness was 500 Å. Next, as shown in FIG. 1b, a silicon oxide film 3 to be a gate insulating film was deposited to a thickness of 500 Å at a substrate temperature of 420° C. by atmospheric pressure CVD. Annealing is performed for 2 hours at 500°C in an oxygen atmosphere, and then oxygen plasma is irradiated for 30 minutes at a substrate temperature of 400°C. The output of oxygen plasma at this time is
It is 150mW/ cm3 . Then, as shown in Figure 1c,
After depositing a polycrystalline silicon film 4 with a thickness of 1000 Å by vacuum evaporation under the same conditions as mentioned above,
A silicon oxide film 5 of 500 Å was deposited using the CVD method. These were subsequently patterned using the RIE method to form gate electrodes.
次いで第１図ｄのごとく104．6pd+を200KeV
で、２×1017cm-2注入する。前述の常圧CVD法で
アニール保護膜兼層間絶縁膜であるSiO2６を堆
積した後、N2雰囲気中で500℃で30分間のアニー
ルを行なう。これにより注入されたPdはPd2Siに
なる。（第１図ｅ）その後、純水素、1Torr、RF
パワー200Wにて発生させた水素プラズマ雰囲気
中で基板温度350℃で30分アニールを行なつた。
次にソースドレインSD領域のそれぞれのコンタ
クトホール７，８をフオトリソグラフイ法によつ
て開孔し、AlSi膜を5000Å堆積した後、再びフ
オトリソグラフイ法によつてソース、ドレイン配
線９，１０を形成した。（第１図ｆ）最後に水素
雰囲気中で440℃30分のアニールを行なつた。こ
のプロセスの最高温度は500℃でありパイレツク
スガラス基板上に安定にトランジスタを形成し得
るのが特徴である。 Then, as shown in Figure 1d, 104.6 pd + is 200KeV.
Then, inject 2×10 17 cm -2 . After depositing SiO 2 6, which serves as an annealing protective film and interlayer insulating film, by the above-mentioned atmospheric pressure CVD method, annealing is performed at 500° C. for 30 minutes in an N 2 atmosphere. As a result, the implanted Pd becomes Pd 2 Si. (Fig. 1 e) After that, pure hydrogen, 1 Torr, RF
Annealing was performed for 30 minutes at a substrate temperature of 350°C in a hydrogen plasma atmosphere generated with a power of 200W.
Next, contact holes 7 and 8 in the source and drain SD regions are opened by photolithography, and an AlSi film is deposited to a thickness of 5000 Å, and then source and drain wirings 9 and 10 are formed by photolithography again. Formed. (Fig. 1f) Finally, annealing was performed at 440°C for 30 minutes in a hydrogen atmosphere. The maximum temperature of this process is 500°C, which makes it possible to stably form transistors on Pyrex glass substrates.
第２図に、このトランジスタサンプルＡのID−
VG特性を示す。 Figure 2 shows the I D − of this transistor sample A.
Shows V G characteristics.
Pd+注入の代わりに11B+を２×1015cm-2、
15KeVで注入することによつてソース、ドレイ
ン部を形成し、それ以外は全く同一のプロセスで
作製した多結晶シリコントランジスタサンプルＢ
の動作特性（破線）と比較すると、ON電流が増
加している。これは、ソース、ドレイン部の抵抗
が低下したためで、駆動力が向上し、高速動作が
可能なことを示している。 11B + instead of Pd + injection at 2 × 10 15 cm -2 ,
Polycrystalline silicon transistor sample B, in which the source and drain parts were formed by implanting at 15 KeV, but otherwise manufactured using the same process.
Compared to the operating characteristics of (dashed line), the ON current increases. This is because the resistance of the source and drain portions has been lowered, indicating that the driving force has improved and high-speed operation is possible.
このソース、ドレイン部のシート抵抗を測定する
とと30Ω／□であつた。この値はサンプルＢのソ
ース、ドレイン部のシート抵抗1.5KΩ／□と比較
して著しく小さく、配線材料としても使用可能で
ある。When the sheet resistance of the source and drain parts was measured, it was 30Ω/□. This value is significantly smaller than the sheet resistance of 1.5KΩ/□ in the source and drain portions of sample B, and it can also be used as a wiring material.
なお、本試作においては、トランジスタの母数
104に対し、ソース、ドレイン部とゲート部の短
絡に起因する破壊は１件もなく、この発明に係る
薄膜トランジスタが再現性においても極めて優れ
ていることが判明した。 In addition, in this prototype, the parameter of the transistor is
104 , there was no damage caused by a short circuit between the source/drain portion and the gate portion, and it was found that the thin film transistor according to the present invention has extremely excellent reproducibility.
なお、ドーピングする金属の種類は、形成され
るシリサイドとシリコンの接合が目的とする薄膜
トランジスタのチヤンネル極性に対してはオーミ
ツク接合、異極性に対してはシヨツトキー接合と
なるように選択すればよく、上記実施例に限定さ
れるものではない。また、注入量と加速電圧およ
びアニール条件は、それぞれの金属種と、シリサ
イド化後の目標とする抵抗値によつて決定され
る。 The type of metal to be doped may be selected so that the junction between the silicide and silicon formed is an ohmic junction for the channel polarity of the desired thin film transistor, or a Schottky junction for a different polarity. It is not limited to the examples. Further, the implantation amount, accelerating voltage, and annealing conditions are determined depending on the respective metal species and the target resistance value after silicide formation.
［発明の効果］
以上のようにこの発明によれば、薄膜トランジ
スタをPd+のようなシリコンとシリサイドを形成
し、かつシリコンと前記シリサイドとの接合がシ
ヨツトキー接合となる金属をイオン注入し、その
後に300℃〜800℃程度の比較的低温のアニールの
を行なうことによつて、Pd+のような被注入金属
をシリサイド化することによつてソース、ドレイ
ン部を形成したため、ソース、ドレイン部とゲー
ト部との短絡による歩留り低下がなく、また選択
エツチング洗浄等のウエツト工程が不要で、使用
する金属も少量のためコスト面からも有利であ
り、ソースドレイン部の抵抗が低いため高速動作
も可能であるといつた薄膜トランジスタが得られ
るという効果がある。[Effects of the Invention] As described above, according to the present invention, a thin film transistor is formed by forming a silicide with silicon such as Pd + and implanting metal ions that form a Schottky junction between the silicon and the silicide, and then By performing annealing at a relatively low temperature of about 300°C to 800°C, the source and drain parts were formed by siliciding the implanted metal such as Pd + , so that the source and drain parts and the gate There is no reduction in yield due to short circuits with parts, there is no need for wet processes such as selective etching cleaning, and there is a small amount of metal used, which is advantageous from a cost standpoint.High-speed operation is also possible because the resistance of the source and drain parts is low. This has the effect of producing a thin film transistor of a certain type.
第１図はこの発明の一実施例による多結晶シリ
コン薄膜トランジスタの作製各プロセスにおける
素子断面を示す図、第２図は作製した多結晶シリ
コン薄膜トランジスタの特性を示す図であり、第
３図はPtSiのソースドレイン構造を有する多結晶
シリコントランジスタの断面構造である。
図において１はパイレツクスガラス（絶縁基
板）、２は多結晶シリコン薄膜（活性層）、３はシ
リコン酸化膜（ゲート絶縁膜）、４は多結晶シリ
コン膜（ゲート電極）、５はシリコン酸化膜（ゲ
ート電極キヤツプ）、６はシリコン酸化膜（層間
絶縁膜）、７はコンタクトホール（ソース部）、８
はコンタクトホール（ドレイン部）、９はソース
電極、１０はドレイン電極である。なお、図中、
同一符号は同一または相当部分を示す。
FIG. 1 is a diagram showing the device cross section in each process of manufacturing a polycrystalline silicon thin film transistor according to an embodiment of the present invention, FIG. 2 is a diagram showing the characteristics of the manufactured polycrystalline silicon thin film transistor, and FIG. 1 is a cross-sectional structure of a polycrystalline silicon transistor having a source-drain structure. In the figure, 1 is Pyrex glass (insulating substrate), 2 is polycrystalline silicon thin film (active layer), 3 is silicon oxide film (gate insulating film), 4 is polycrystalline silicon film (gate electrode), 5 is silicon oxide film (gate electrode cap), 6 is silicon oxide film (interlayer insulating film), 7 is contact hole (source part), 8
9 is a contact hole (drain part), 9 is a source electrode, and 10 is a drain electrode. In addition, in the figure,
The same reference numerals indicate the same or equivalent parts.
Claims (1)
MIS型電界効果トランジスタの製造方法におい
て、基板である絶縁物質を用意し、前記基板上に
ソース、ドレインとなる多結晶シリコン薄膜を形
成し、前記シリコン薄膜上にシリコン酸化膜を形
成し、前記シリコン酸化膜上にゲートとなる多結
晶シリコン膜を形成し、前記ゲートとなる多結晶
シリコン膜上にシリコン酸化膜を形成し、その
後、金属イオンを前記ゲート、ソース、ドレイン
となる多結晶シリコン膜に注入し、前記被注入金
属イオンを低温アニールによつてシリサイド化
し、シヨツトキー接合からなるソース、ドレイン
部を形成することを特徴とする薄膜トランジスタ
の製造方法。1 Use polycrystalline silicon thin film as semiconductor active layer
In a method for manufacturing an MIS field effect transistor, an insulating material as a substrate is prepared, a polycrystalline silicon thin film is formed as a source and a drain on the substrate, a silicon oxide film is formed on the silicon thin film, and the silicon A polycrystalline silicon film that will become a gate is formed on the oxide film, a silicon oxide film is formed on the polycrystalline silicon film that will become the gate, and then metal ions are applied to the polycrystalline silicon film that will become the gate, source, and drain. 1. A method for manufacturing a thin film transistor, comprising the steps of: implanting the implanted metal ions, and silicidizing the implanted metal ions by low-temperature annealing to form source and drain portions consisting of Schottky junctions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13713487A JPS63300566A (en) | 1987-05-29 | 1987-05-29 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13713487A JPS63300566A (en) | 1987-05-29 | 1987-05-29 | Manufacture of thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63300566A JPS63300566A (en) | 1988-12-07 |
| JPH0542137B2 true JPH0542137B2 (en) | 1993-06-25 |
Family
ID=15191613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13713487A Granted JPS63300566A (en) | 1987-05-29 | 1987-05-29 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63300566A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5108953A (en) * | 1989-02-02 | 1992-04-28 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating a semiconductive device comprising a refractory metal silicide thin film |
| US5159416A (en) * | 1990-04-27 | 1992-10-27 | Nec Corporation | Thin-film-transistor having schottky barrier |
| KR100699462B1 (en) * | 2005-12-07 | 2007-03-28 | 한국전자통신연구원 | Schottky Barrier Tunnel Transistor and the Method for Manufacturing the same |
-
1987
- 1987-05-29 JP JP13713487A patent/JPS63300566A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63300566A (en) | 1988-12-07 |
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