JPH0537342A - Semiconductor logic input circuit - Google Patents
Semiconductor logic input circuitInfo
- Publication number
- JPH0537342A JPH0537342A JP3188507A JP18850791A JPH0537342A JP H0537342 A JPH0537342 A JP H0537342A JP 3188507 A JP3188507 A JP 3188507A JP 18850791 A JP18850791 A JP 18850791A JP H0537342 A JPH0537342 A JP H0537342A
- Authority
- JP
- Japan
- Prior art keywords
- ground potential
- terminal
- power supply
- noise
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体論理入力回路に関
する。BACKGROUND OF THE INVENTION The present invention relates to a semiconductor logic input circuit.
【０００２】[0002]
【従来の技術】従来の半導体論理入力回路、例えば相補
型ＭＯＳ集積回路の論理入力部は、図４（ａ）に示すよ
うに前段および後段インバータ６，１１で構成される。
すなわち、入力端子２から入力する外部論理入力信号１
０２は、前段インバータ６と後段インバータ１１でＣＭ
ＯＳレベルに調整され内部回路論理入力信号１１１とな
る。2. Description of the Related Art A conventional semiconductor logic input circuit, for example, a logic input section of a complementary MOS integrated circuit is composed of front and rear inverters 6 and 11 as shown in FIG.
That is, the external logic input signal 1 input from the input terminal 2
02 is a CM for the front stage inverter 6 and the rear stage inverter 11.
It is adjusted to the OS level and becomes the internal circuit logic input signal 111.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の半導体
論理入力回路は、図４（ｂ）の各電圧波形が示すよう
に、接地電位端子３にノイズＶＮＧが発生した場合にト
ランジスタＱ２が導通状態であれば、インバータ６の論
理出力信号１０６に歪が生じ、この論理出力１０６の歪
電位が後段インバータ１１の論理スレッシュホールドを
越えた場合には、内部回路論理入力信号１１１のレベル
は反転する。In the conventional semiconductor logic input circuit described above, the transistor Q2 is in a conductive state when noise VNG occurs at the ground potential terminal 3, as shown by the voltage waveforms in FIG. 4B. If so, the logic output signal 106 of the inverter 6 is distorted, and when the distorted potential of the logic output 106 exceeds the logic threshold of the latter-stage inverter 11, the level of the internal circuit logic input signal 111 is inverted.
【０００４】電源端子１にノイズＶＮＤが発生した時も
同様に、内部回路論理入力信号１１１のレベルに影響を
及ぼす。その結果として内部回路１０を誤動作させると
いう問題点があった。Similarly, when noise VND is generated at the power supply terminal 1, the level of the internal circuit logic input signal 111 is affected. As a result, there is a problem that the internal circuit 10 malfunctions.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体論理入力
回路は、２端子以上の接地電位端子（同電位電源端子）
に接続する前段および後段の論理ゲートを有する半導体
論理入力回路において、前記接地電位端子（同電位電源
端子）の一方の論理入力信号が入力する前記前段論理ゲ
ートに接続する接地電位端子（同電位電源端子）と他方
の接地電位端子（同電位電源端子）の電位とを比較する
比較器を付加し、かつ前記後段論理ゲートが、前記比較
器の出力信号を入力して制御されるクロックドインバー
タを有して構成されている。The semiconductor logic input circuit of the present invention has two or more ground potential terminals (equal potential power supply terminals).
In a semiconductor logic input circuit having front and rear logic gates connected to each other, a ground potential terminal (equal potential power supply) connected to the preceding logic gate to which one logic input signal of the ground potential terminal (equal potential power supply terminal) is input. Terminal) and a potential of another ground potential terminal (same potential power supply terminal), and a clocked inverter controlled by inputting the output signal of the comparator to the latter logic gate. It is configured to have.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ），（ｂ）は、それぞれ本発明の第１の実
施例の回路図およびその電圧波形図である。この半導体
論理入力回路は外部論理入力信号１０２が入力する前段
インバータ６と、このインバータ６に接続する接地電位
端子３の接地電位１０３と接地電位端子４の接地電位１
０４とを比較する比較器５と、比較器５の出力信号１０
５が入力するインバータ７と、前段インバータ６の論理
出力信号１０６が入力し比較器出力信号１０５とインバ
ータ７の出力信号１０７とで制御されるクロックドイン
バータ８で構成される。The present invention will be described below with reference to the drawings. 1A and 1B are a circuit diagram and a voltage waveform diagram thereof, respectively, according to a first embodiment of the present invention. This semiconductor logic input circuit includes a front stage inverter 6 to which an external logic input signal 102 is input, a ground potential 103 of a ground potential terminal 3 and a ground potential 1 of a ground potential terminal 4 connected to this inverter 6.
And the output signal 10 of the comparator 5.
5 and the clocked inverter 8 to which the logical output signal 106 of the preceding-stage inverter 6 is input and which is controlled by the comparator output signal 105 and the output signal 107 of the inverter 7.
【０００７】接地電位１０３にノイズＶＮＧが発生した
場合、図１（ｂ）に示すように、論理出力信号１０６に
も接地電位ノイズＶＧＮが乗る。しかし、比較器出力１
０５と論理出力信号１０７がそれぞれゲートに入力する
トランジスタＱ４とＱ５は、接地電位ノイズＶＮＧの発
生期間ＴＧは非導通となり、その結果内部論理回路入力
信号１０８は、接地電位ノイズＶＮＧの影響を受けず、
ノイズ発生前の電位を保持する。従って接地電位ノイズ
ＶＮＧにより、内部回路の動作が乱されることはない。When noise VNG is generated in the ground potential 103, the ground potential noise VGN is also added to the logic output signal 106, as shown in FIG. 1B. However, the comparator output 1
05 and the logic output signal 107 are input to the gates of the transistors Q4 and Q5, respectively, are non-conductive during the generation period TG of the ground potential noise VNG, so that the internal logic circuit input signal 108 is not affected by the ground potential noise VNG. ,
Holds the potential before noise is generated. Therefore, the operation of the internal circuit is not disturbed by the ground potential noise VNG.
【０００８】図２（ａ），（ｂ）は、それぞれ本発明の
第２の実施例の回路図及び各電圧波形図である。本実施
例と第１の実施例との違いは、電源電位のノイズＶＮＤ
による誤動作を防ぐため、比較器５の入力端を電源端子
１と電源端子９に接続した点である。2 (a) and 2 (b) are a circuit diagram and a voltage waveform diagram of a second embodiment of the present invention, respectively. The difference between this embodiment and the first embodiment is that the noise VND of the power supply potential
The input terminal of the comparator 5 is connected to the power supply terminal 1 and the power supply terminal 9 in order to prevent a malfunction due to.
【０００９】電源電位１０１にノイズＶＮＤが発生した
場合は第１の実施例と同様に、トランジスタＱ４とＱ５
は電源電位ノイズＶＮＤの発生期間ＴＤ非導通となり、
その結果内部論理回路１０８は電源電位ノイズＶＮＤの
影響を受けない。従って内部回路の動作が乱されること
はない。When noise VND is generated in the power supply potential 101, the transistors Q4 and Q5 are used as in the first embodiment.
Is non-conducting during the generation of the power supply potential noise VND,
As a result, internal logic circuit 108 is not affected by power supply potential noise VND. Therefore, the operation of the internal circuit is not disturbed.
【００１０】図３（ａ），（ｂ）は、それぞれ本発明の
第３の実施例の回路図及び各電圧波形図である。本実施
例は接地電位１０３，１０４と電源電位１０１，１０９
の両方のノイズＶＮＧ，ＶＮＤによる誤動作を防ぐため
に比較器５，５ａを設け、比較器５ａには電源端子１と
電源端子９を接続し、比較器５には接地電位端子３と接
地電位端子４を接続しとものである。3 (a) and 3 (b) are a circuit diagram and a voltage waveform diagram of a third embodiment of the present invention, respectively. In this embodiment, the ground potentials 103 and 104 and the power supply potentials 101 and 109 are used.
In order to prevent malfunction due to both noises VNG and VND, comparators 5 and 5a are provided, the power supply terminal 1 and the power supply terminal 9 are connected to the comparator 5a, and the ground potential terminal 3 and ground potential terminal 4 are connected to the comparator 5. It is connected to the original.
【００１１】接地電位１０３にノイズＶＮＧが発生した
場合、インバータ７の論理出力信号１０７は図３（ｂ）
の如く変化し、トランジスタＱ５は接地電位ノイズ発生
期間ＴＧは非導通となり、内部回路論理入力信号１０８
はノイズＶＮＧの影響を受けない。When noise VNG is generated in the ground potential 103, the logic output signal 107 of the inverter 7 is shown in FIG.
The transistor Q5 becomes non-conductive during the ground potential noise generation period TG, and the internal circuit logic input signal 108 changes.
Is not affected by noise VNG.
【００１２】同様に、電源電位１０１にノイズＶＮＤが
発生した場合にトランジスタＱ４は電源電位ノイズ発生
期間ＴＤ非導通となり、内部回路論理入力信号１０８は
ノイズＶＮＤの影響を受けない。Similarly, when noise VND is generated in the power supply potential 101, the transistor Q4 becomes non-conductive during the power supply potential noise generation period TD, and the internal circuit logic input signal 108 is not affected by the noise VND.
【００１３】従って、接地電位，電源電位のいずれのノ
イズＶＮＧ，ＶＮＤが発生した場合でも、内部回路の動
作が乱されることはない。Therefore, even if the noise VNG or VND of the ground potential or the power source potential occurs, the operation of the internal circuit is not disturbed.
【００１４】[0014]
【発明の効果】以上説明したように本発明によれば、従
来問題とされた接地電位ノイズ及び電源電位ノイズの影
響による内部回路の誤動作を防止できるので、半導体集
積回路装置の回路動作の信頼性向上に大きな効果をあげ
ることができる。As described above, according to the present invention, it is possible to prevent the malfunction of the internal circuit due to the influence of the ground potential noise and the power source potential noise, which has been a problem in the prior art. A great effect can be given to the improvement.
【図１】（ａ），（ｂ）はそれぞれ本発明の第１の実施
例の回路図およびその電圧波形図である。1A and 1B are a circuit diagram and a voltage waveform diagram thereof, respectively, according to a first embodiment of the present invention.
【図２】（ａ），（ｂ）はそれぞれ本発明の第２の実施
例の回路図およびその電圧波形図である。2A and 2B are respectively a circuit diagram and a voltage waveform diagram thereof according to a second embodiment of the present invention.
【図３】（ａ），（ｂ）はそれぞれ本発明の第３の実施
例の回路図およびその電圧波形図である。3A and 3B are a circuit diagram and a voltage waveform diagram thereof, respectively, according to a third embodiment of the present invention.
【図４】（ａ），（ｂ）はそれぞれ従来の半導体論理入
力回路の一例の回路図およびその電圧波形図である。4A and 4B are a circuit diagram and a voltage waveform diagram of an example of a conventional semiconductor logic input circuit, respectively.
１，９ 電源端子 ２ 入力端子 ３，４ 接地電位端子 ５，５ａ 比較器 ６，７，１１ インバータ ８ クロックドインバータ １０ 内部回路 Ｑ１，Ｑ３，Ｑ４ Ｐ型ＭＯＳトランジスタ Ｑ２，Ｑ５，Ｑ６ Ｎ型ＭＯＳトランジスタ １０１，１０９ 電源電位 １０２ 外部論理入力信号 １０３，１０４ 接地電位 １０５，１１０ 比較器出力 １０６，１０７ 論理出力信号 １０８，１１１ 内部回路論理入力信号 1,9 Power supply terminal 2 Input terminal 3,4 Ground potential terminal 5,5a Comparator 6,7,11 Inverter 8 Clocked inverter 10 Internal circuit Q1, Q3, Q4 P-type MOS transistor Q2, Q5, Q6 N-type MOS transistor 101, 109 Power supply potential 102 External logic input signal 103, 104 Ground potential 105, 110 Comparator output 106, 107 Logic output signal 108, 111 Internal circuit logic input signal
Claims (1)
端子）に接続する前段および後段の論理ゲートを有する
半導体論理入力回路において、前記接地電位端子（同電
位電源端子）の一方の論理入力信号が入力する前記前段
論理ゲートに接続する接地電位端子（同電位電源端子）
と他方の接地電位端子（同電位電源端子）の電位とを比
較する比較器を付加し、かつ前記後段論理ゲートが、前
記比較器の出力信号を入力して制御されるクロックドイ
ンバータを有することを特徴とする半導体論理入力回
路。Claim: What is claimed is: 1. In a semiconductor logic input circuit having front and rear logic gates connected to two or more ground potential terminals (equal potential power supply terminals), the ground potential terminal (equal potential power supply terminal). ) A ground potential terminal (equal potential power supply terminal) connected to the preceding logic gate to which one logic input signal is input
And a comparator for comparing the potential of the other ground potential terminal (same potential power supply terminal) with each other, and the latter-stage logic gate has a clocked inverter controlled by inputting an output signal of the comparator. A semiconductor logic input circuit characterized by.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3188507A JPH0537342A (en) | 1991-07-29 | 1991-07-29 | Semiconductor logic input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3188507A JPH0537342A (en) | 1991-07-29 | 1991-07-29 | Semiconductor logic input circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0537342A true JPH0537342A (en) | 1993-02-12 |
Family
ID=16224934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3188507A Pending JPH0537342A (en) | 1991-07-29 | 1991-07-29 | Semiconductor logic input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0537342A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0887935A1 (en) * | 1997-06-27 | 1998-12-30 | United Memories, Inc. | Noise isolation circuit |
-
1991
- 1991-07-29 JP JP3188507A patent/JPH0537342A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0887935A1 (en) * | 1997-06-27 | 1998-12-30 | United Memories, Inc. | Noise isolation circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2772522B2 (en) | Power-on signal generation circuit | |
| KR930000972B1 (en) | Semiconductor device comprising cmos inverter | |
| JP2575956B2 (en) | Substrate bias circuit | |
| EP0887935B1 (en) | Noise isolation circuit | |
| US5418486A (en) | Universal digital filter for noisy lines | |
| US5120988A (en) | Clock generator circuit providing reduced current consumption | |
| US6037827A (en) | Noise isolation circuit | |
| US4307308A (en) | Digital signal conversion circuit | |
| JPS5928986B2 (en) | semiconductor integrated circuit | |
| JPH0537342A (en) | Semiconductor logic input circuit | |
| JP3329621B2 (en) | Dual power interface circuit | |
| JP2856355B2 (en) | Semiconductor integrated circuit | |
| KR100290892B1 (en) | Complementary metal oxide semiconductor voltage level shift circuit | |
| JP3184356B2 (en) | Output buffer circuit in semiconductor integrated circuit | |
| JP3279717B2 (en) | Bus input interface circuit | |
| JPH05322984A (en) | Test input circuit | |
| JP2757632B2 (en) | Test signal generation circuit | |
| JP2798510B2 (en) | Semiconductor integrated circuit | |
| US5412264A (en) | Signal input/output circuit for semiconductor integrated circuit | |
| KR940005873Y1 (en) | Slewrate control tri-state output buffer | |
| JP2849222B2 (en) | Semiconductor storage device | |
| JPH03204219A (en) | Cmos latch circuit | |
| JPH0691459B2 (en) | 3-value output circuit | |
| JPH09200029A (en) | Output circuit | |
| JPH01256814A (en) | Gate array |