JPH05343692A - Vertical field-effect transistor - Google Patents
Vertical field-effect transistorInfo
- Publication number
- JPH05343692A JPH05343692A JP4149080A JP14908092A JPH05343692A JP H05343692 A JPH05343692 A JP H05343692A JP 4149080 A JP4149080 A JP 4149080A JP 14908092 A JP14908092 A JP 14908092A JP H05343692 A JPH05343692 A JP H05343692A
- Authority
- JP
- Japan
- Prior art keywords
- region
- diffusion layer
- layer
- gate electrode
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は縦型電界効果トランジス
タに関する。FIELD OF THE INVENTION The present invention relates to a vertical field effect transistor.
【０００２】[0002]
【従来の技術】従来の縦型電界効果トランジスタは、図
２に示すように、Ｎ型シリコン基板１のセル形成領域に
設けたＰ型のベース領域２とセル形成領域外のパッド形
成領域に設けたＰ型拡散層３と、ベース領域２内に設け
たソース領域４と、ベース領域２を含む表面に設けたゲ
ート絶縁膜５の上に設けてＰ型拡散層３上に延在させた
ゲート電極６と、ゲート電極６を含む表面に設けた層間
絶縁膜８に設けたコンタクト孔を介してソース電極４及
びＰ型拡散層３に接続したソース電極９と、Ｐ型拡散層
３上のゲート電極６に接続して層間絶縁膜８上に形成し
たゲート電極パッド１０を有している。2. Description of the Related Art A conventional vertical field effect transistor is provided in a P type base region 2 provided in a cell forming region of an N type silicon substrate 1 and a pad forming region outside the cell forming region, as shown in FIG. A P-type diffusion layer 3, a source region 4 provided in the base region 2, and a gate insulating film 5 provided on the surface including the base region 2 and extending over the P-type diffusion layer 3. The electrode 6, the source electrode 9 connected to the source electrode 4 and the P-type diffusion layer 3 through the contact hole provided in the interlayer insulating film 8 provided on the surface including the gate electrode 6, and the gate on the P-type diffusion layer 3. It has a gate electrode pad 10 connected to the electrode 6 and formed on the interlayer insulating film 8.
【０００３】[0003]
【発明が解決しようとする課題】この従来の縦型電界効
果トランジスタは、ゲート電極パッド下のＰ型拡散層
と、Ｎ型シリコン基板とにより形成されるＰＮ接合の順
バイアス時にドレイン領域に注入したキャリアが逆バイ
アスの印加時にＰ型拡散層へ収集されるが、Ｐ型拡散層
に収集されなかった一部のキャリアがセル部のベース領
域に集中し、ソース電極を介してベース領域及びソース
領域と直接接続されているＰ型拡散層の拡散抵抗（２０
０ｍΩ／□程度）によって引き抜く効率が低下し、キャ
リアがセル部へ集中し、セルの破壊を招くという問題が
あった。（破壊耐量としては、逆バイアスの印加速さ１
０ｖ／ｎｓ程度である。）In this conventional vertical field effect transistor, the PN junction formed by the P type diffusion layer under the gate electrode pad and the N type silicon substrate is injected into the drain region during forward bias. The carriers are collected in the P-type diffusion layer when a reverse bias is applied, but some of the carriers that are not collected in the P-type diffusion layer are concentrated in the base region of the cell part, and the base region and the source region pass through the source electrode. The diffusion resistance of the P-type diffusion layer (20
However, there is a problem in that the extraction efficiency is reduced by about 0 mΩ / □), carriers are concentrated in the cell portion, and the cell is destroyed. (As for the breakdown resistance, the reverse bias application speed is 1
It is about 0 v / ns. )
【課題を解決するための手段】本発明の縦型電界効果ト
ランジスタは、一導電型半導体基板のセル形成領域に配
列して設けた逆導電型のベース領域及び前記セル形成領
域以外のパッド形成領域に設けた逆導電型の拡散層と、
前記ベース領域内に設けてチャネル領域を規定する一導
電型のソース領域と、前記チャネル領域上に設けて前記
拡散層上に延在されたゲート電極と、前記拡散層に設け
た溝内に埋込んで設けた高融点金属層と、前記ソース領
域と前記高融点金属層とを接続して設けたソース電極
と、前記ゲート電極と接続して前記拡散層上に設けたゲ
ート電極パッドとを有する。A vertical field effect transistor according to the present invention comprises a reverse conductivity type base region arranged in a cell formation region of a one conductivity type semiconductor substrate and a pad formation region other than the cell formation region. A reverse conductivity type diffusion layer provided in
A source region of one conductivity type provided in the base region to define a channel region, a gate electrode provided on the channel region and extending on the diffusion layer, and buried in a groove provided in the diffusion layer. And a source electrode provided by connecting the source region and the refractory metal layer, and a gate electrode pad provided on the diffusion layer in connection with the gate electrode. ..
【０００４】[0004]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【０００５】図１は本発明の一実施例を示す断面図であ
る。FIG. 1 is a sectional view showing an embodiment of the present invention.
【０００６】図１に示すように、Ｎ型シリコン基板１の
セル形成領域に規則的に配列して設けたＰ型のベース領
域２と、セル形成領域以外のパッド形成領域に設けたＰ
型拡散層３と、ベース領域２内に設けてチャネル領域を
規定するＮ型のソース領域４と、ベース領域２を含む表
面に設けたゲート絶縁膜５と、チャネル領域上のゲート
絶縁膜５の上に設けてパッド形成領域のＰ型拡散層３上
に延在させたゲート電極６と、Ｐ型拡散層３の表面に設
けた深さ１〜２μｍ，幅０．３〜２μｍの溝内に埋込ん
で設けたタングステン層７とゲート電極６を含む表面に
設けた層間絶縁膜８と、層間絶縁膜８に設けたコンタク
ト孔を介してソース電極４及びタングステン層７に接続
したソース電極９と、Ｐ型拡散層３上のゲート電極６に
接続して層間絶縁膜８上に設けたゲート電極パッド１０
とを有して構成される。As shown in FIG. 1, a P-type base region 2 is arranged regularly in a cell formation region of an N-type silicon substrate 1, and a P-type P region is provided in a pad formation region other than the cell formation region.
The type diffusion layer 3, the N type source region 4 provided in the base region 2 to define the channel region, the gate insulating film 5 provided on the surface including the base region 2, and the gate insulating film 5 on the channel region. The gate electrode 6 provided above and extending on the P-type diffusion layer 3 in the pad formation region and the groove having a depth of 1 to 2 μm and a width of 0.3 to 2 μm provided on the surface of the P-type diffusion layer 3. An interlayer insulating film 8 provided on the surface including the embedded tungsten layer 7 and the gate electrode 6, and a source electrode 9 connected to the source electrode 4 and the tungsten layer 7 through a contact hole provided in the interlayer insulating film 8. , A gate electrode pad 10 connected to the gate electrode 6 on the P-type diffusion layer 3 and provided on the interlayer insulating film 8.
And is configured.
【０００７】ここで、Ｐ型拡散層３とＮ型シリコン基板
１とにより形成されるＰＮ接合の順バイアス時にドレイ
ン領域に注入したキャリアが逆バイアスの印加によりＰ
型拡散層３に収集されるが、従来技術に比べＰ型拡散層
３内の拡散抵抗（２００ｍΩ／□程度）が１／２程度に
減少するため、キャリアの収集効率が改善され、破壊耐
量としては逆バイアス印加速さ２０ｖ／ｎｓに改善され
る。Here, the carriers injected into the drain region at the forward bias of the PN junction formed by the P-type diffusion layer 3 and the N-type silicon substrate 1 are applied with the reverse bias to P.
Although it is collected in the type diffusion layer 3, the diffusion resistance (about 200 mΩ / □) in the P type diffusion layer 3 is reduced to about 1/2 of that in the conventional technique, so that the carrier collection efficiency is improved and the breakdown resistance is increased. Is improved to a reverse bias application speed of 20 v / ns.
【０００８】[0008]
【発明の効果】以上説明したように本発明は、パッド形
成領域に設けたＰ型拡散層に埋込んで高融点金属層を設
けることにより、ゲート電極パッド下のＰ型拡散層のキ
ャリア収集効率が向上し、ＰＮ接合の順バイアス時にド
レイン領域に注入されたキャリアが、逆バイアス時に効
率よくＰ型拡散層に収集されるため、セルにキャリアが
集中することがなくセルの破壊を防止し、デバイスの破
壊耐量が向上できるという効果を有する。As described above, according to the present invention, the high-melting-point metal layer is embedded in the P-type diffusion layer provided in the pad formation region to provide the carrier collection efficiency of the P-type diffusion layer under the gate electrode pad. Since the carriers injected into the drain region at the time of forward bias of the PN junction are efficiently collected in the P-type diffusion layer at the time of reverse bias, the carriers are prevented from being concentrated in the cell and the destruction of the cell is prevented. This has the effect of improving the breakage resistance of the device.
【図１】本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】従来の縦型電界効果トランジスタの一例を示す
断面図。FIG. 2 is a sectional view showing an example of a conventional vertical field effect transistor.
１ Ｎ型シリコン基板 ２ ベース領域 ３ Ｐ型拡散層 ４ ソース領域 ５ ゲート絶縁膜 ６ ゲート電極 ７ タングステン層 ８ 層間絶縁膜 ９ ソース電極 １０ ゲート電極パッド 1 N-type silicon substrate 2 Base region 3 P-type diffusion layer 4 Source region 5 Gate insulating film 6 Gate electrode 7 Tungsten layer 8 Interlayer insulating film 9 Source electrode 10 Gate electrode pad
Claims (2)
列して設けた逆導電型のベース領域及び前記セル形成領
域以外のパッド形成領域に設けた逆導電型の拡散層と、
前記ベース領域内に設けてチャネル領域を規定する一導
電型のソース領域と、前記チャネル領域上に設けて前記
拡散層上に延在されたゲート電極と、前記拡散層に設け
た溝内に埋込んで設けた高融点金属層と、前記ソース領
域と前記高融点金属層とを接続して設けたソース電極
と、前記ゲート電極と接続して前記拡散層上に設けたゲ
ート電極パッドとを有することを特徴とする縦型電界効
果トランジスタ。1. A reverse conductivity type base region arranged in a cell formation region of a single conductivity type semiconductor substrate, and a reverse conductivity type diffusion layer provided in a pad formation region other than the cell formation region,
A source region of one conductivity type provided in the base region to define a channel region, a gate electrode provided on the channel region and extending on the diffusion layer, and buried in a groove provided in the diffusion layer. And a source electrode provided by connecting the source region and the refractory metal layer, and a gate electrode pad provided on the diffusion layer in connection with the gate electrode. A vertical field effect transistor characterized by the above.
求項１記載の縦型電界効果トランジスタ。2. The vertical field effect transistor according to claim 1, wherein the refractory metal layer is a tungsten layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4149080A JPH05343692A (en) | 1992-06-09 | 1992-06-09 | Vertical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4149080A JPH05343692A (en) | 1992-06-09 | 1992-06-09 | Vertical field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05343692A true JPH05343692A (en) | 1993-12-24 |
Family
ID=15467261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4149080A Withdrawn JPH05343692A (en) | 1992-06-09 | 1992-06-09 | Vertical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05343692A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015057850A (en) * | 2010-06-30 | 2015-03-26 | 三菱電機株式会社 | Power semiconductor device |
| WO2015107742A1 (en) | 2014-01-16 | 2015-07-23 | 富士電機株式会社 | Semiconductor device |
-
1992
- 1992-06-09 JP JP4149080A patent/JPH05343692A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015057850A (en) * | 2010-06-30 | 2015-03-26 | 三菱電機株式会社 | Power semiconductor device |
| WO2015107742A1 (en) | 2014-01-16 | 2015-07-23 | 富士電機株式会社 | Semiconductor device |
| US9620595B2 (en) | 2014-01-16 | 2017-04-11 | Fuji Electric Co., Ltd. | Semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990831 |