JPH05335622A - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device

Info

Publication number
JPH05335622A
JPH05335622A JP13522092A JP13522092A JPH05335622A JP H05335622 A JPH05335622 A JP H05335622A JP 13522092 A JP13522092 A JP 13522092A JP 13522092 A JP13522092 A JP 13522092A JP H05335622 A JPH05335622 A JP H05335622A
Authority
JP
Japan
Prior art keywords
layer
type
light emitting
electrode
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP13522092A
Other languages
Japanese (ja)
Inventor
Hideaki Imai
秀秋 今井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd filed Critical Asahi Chemical Industry Co Ltd
Priority to JP13522092A priority Critical patent/JPH05335622A/en
Publication of JPH05335622A publication Critical patent/JPH05335622A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Abstract

PURPOSE:To obtain a gallium nitride semiconductor device having high light extracting efficiency by forming a light emitting layer of a gallium nitride compound and extracting light from an electrode on which a pattern for uniformly applying a voltage is formed. CONSTITUTION:After an n-GaN semiconductor layer is formed by opening a Ga shutter 13 while a substrate 8 is heated to and maintained at 700 deg.C and an ammonia gas is supplied from a cracking gas cell 6, a Zn-doped p-GaN semiconductor layer is grown on the n-GaN semiconductor layer by opening shutters 13 and 16b. Then an element pattern and electrodes are formed through a precise machining process and an Al electrode and netlike Au electrode (covering 25% of the surface) are respectively formed on the surface of the n-GaN and p-GaN semiconductor layers by vacuum deposition. Therefore, a semiconductor light emitting device having an excellent performance can be obtained when a package is formed after elements are cut off with a dicing saw and wiring is made with gold wires.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、特に表示、ディスプレ
ー、光通信に最適な紫外域〜橙色半導体発光装置に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultraviolet to orange semiconductor light emitting device which is most suitable for display, display and optical communication.

【０００２】[0002]

【従来の技術】半導体素子、特に可視域発光ダイオード
（ＬＥＤ）は、広い分野において表示素子として使用さ
れているが、従来、紫外域〜青色発光ダイオードおよび
レーザーダイオードは実用化されておらず、特に３原色
を必要とするディスプレー用として開発が急がれてい
る。紫外域〜青色発光ダイオードおよびレーザーダイオ
ードとしては、ＺｎＳｅ、ＺｎＳ、ＧａＮやＳｉＣなど
を用いたものが報告されている。2. Description of the Related Art Semiconductor devices, particularly visible light emitting diodes (LEDs), are used as display devices in a wide range of fields, but ultraviolet to blue light emitting diodes and laser diodes have not been put into practical use. Development is urgently needed for displays that require three primary colors. Ultraviolet to blue light emitting diodes and laser diodes using ZnSe, ZnS, GaN, SiC or the like have been reported.

【０００３】しかし、一般的に大きなバンドギャップを
有する化合物半導体の作製は難しく、とくに発光素子に
使用可能な薄膜の製造方法はまだ確立されているとは言
えない。そのなかで、短波長発光素子として有望視され
ている窒化ガリウム系半導体薄膜は、これまではサファ
イア基板上にＭＢＥ法、ＭＯＣＶＤ法、ハロゲンＣＶＤ
法、スパッタリング法により作製されている［プログレ
ス オブ クリスタルグロース アンド キャラクタラ
イゼイション（Ｐｒｏｇｒｅｓｓ ｏｆ Ｃｒｙｓｔａ
ｌ Ｇｒｏｗｔｈ ａｎｄ Ｃｈａｒａｃｔｅｒｉｚａ
ｔｉｏｎ）１７（１９８８）５３−７８］。窒化ガリウ
ム系半導体薄膜においてはそれ自身の単結晶基板がない
ため、ヘテロエピタキシー法による薄膜成長を行なわな
くてはならず、発光素子として使用できる結晶性の良好
な薄膜を作製することが困難であるという問題点があ
る。基板としては、サファイア、酸化亜鉛、シリコン、
石英、ＳｉＣ、ＧａＡｓやＧａＰ等が用いられている。
しかし、シリコン、ＳｉＣ、ＧａＡｓやＧａＰのような
導電性の基板上での結晶性の良好な窒化ガリウム系半導
体薄膜の成長は困難であり、従来は絶縁性の基板が主と
して用いられている。なかでも、サファイアＣ面基板を
用いてその上にＡｌＮのバッファー層を設けることによ
り結晶性の良好なＧａＮ薄膜を得ることができるという
報告がある［日本結晶成長学会誌 １５（１９８８）３
３４−３４２］。しかしながら、絶縁性の基板を使用す
るため、電極の取り出し方法が困難であるとか、発光し
た光を基板を通して取り出すために基板による光の吸収
があるため発光効率が低くなるとかいう問題点がある。However, it is generally difficult to produce a compound semiconductor having a large band gap, and it cannot be said that a method for producing a thin film which can be used particularly for a light emitting device has been established yet. Among them, gallium nitride-based semiconductor thin films, which are regarded as promising as a short-wavelength light emitting element, have hitherto been known as MBE method, MOCVD method, halogen CVD method on a sapphire substrate.
And the sputtering method [Progress of Crystal Growth and Characterization (Progress of Crystal
l Growth and Characteriza
17) (1988) 53-78]. Since a gallium nitride based semiconductor thin film does not have its own single crystal substrate, it is necessary to grow a thin film by the heteroepitaxy method, and it is difficult to produce a thin film with good crystallinity that can be used as a light emitting device. There is a problem. Substrates include sapphire, zinc oxide, silicon,
Quartz, SiC, GaAs, GaP, etc. are used.
However, it is difficult to grow a gallium nitride based semiconductor thin film having good crystallinity on a conductive substrate such as silicon, SiC, GaAs or GaP, and an insulating substrate has been mainly used conventionally. Among them, there is a report that a GaN thin film having good crystallinity can be obtained by using a sapphire C-plane substrate and providing an AlN buffer layer thereon [Journal of Crystal Growth Society of Japan 15 (1988) 3
34-342]. However, since an insulating substrate is used, there is a problem that it is difficult to take out the electrode, and that light emission efficiency is lowered because the substrate absorbs light to take out the emitted light through the substrate.

【０００４】したがって、窒化ガリウム系半導体薄膜か
らなる光の取り出し効率の良い発光装置を得ることは困
難であり、とくに短波長発光素子作製の大きな問題点で
あった。Therefore, it is difficult to obtain a light emitting device composed of a gallium nitride based semiconductor thin film and having a good light extraction efficiency, which is a big problem especially in the production of a short wavelength light emitting device.

【０００５】[0005]

【発明が解決しようとする課題】本発明は、短波長発光
素子として、発光した光の取り出し効率に優れ、かつ電
極の形成および取り出しが容易な窒化ガリウム系半導体
発光装置を提供しようとするものである。SUMMARY OF THE INVENTION The present invention is intended to provide a gallium nitride based semiconductor light emitting device as a short-wavelength light emitting device, which is excellent in the extraction efficiency of emitted light and in which electrodes can be easily formed and extracted. is there.

【０００６】[0006]

【課題を解決するための手段】本発明者らは前記問題点
を解決するため鋭意研究を重ねた結果、基板を通さずに
発光した光を取り出すことができる構造とすることによ
り、優れた性能を有する半導体発光装置を得ることを可
能とした。すなわち、本発明は透明基板上に窒化ガリウ
ム系化合物からなるｎ型半導体層およびｐ型あるいはｉ
型半導体層を組み合わせてなる発光層を少なくとも一つ
有し、該発光層に電圧を印加するために半導体層の所望
の部位に電極が形成されている半導体発光素子構造にお
いて、ｐ型あるいはｉ型半導体層を表面層とし、かつ該
ｐ型あるいはｉ型半導体層からなる表面層に電圧を均一
に印加するためのパターンを形成された電極が、該半導
体表面層の表面を、５０％を超えない範囲で覆い、その
電極側から光を取り出すことを特徴とする半導体発光装
置、および透明基板上の一方の基板面に少なくとも一層
の金属層を有し、かつその反対側の基板面上に窒化ガリ
ウム系化合物からなるｎ型半導体層およびｐ型あるいは
ｉ型半導体層を組み合わせてなる発光層を少なくとも一
つ有し、該発光層に電圧を印加するために半導体層の所
望の部位に電極が形成されている半導体発光素子構造に
おいて、ｐ型あるいはｉ型半導体層を表面層とし、かつ
該ｐ型あるいはｉ型半導体層からなる表面層に電圧を均
一に印加するためのパターンを形成された電極が、該半
導体表面層の表面を、５０％を超えない範囲で覆い、そ
の電極側から光を取り出すことを特徴とする半導体発光
装置である。The inventors of the present invention have conducted extensive studies to solve the above-mentioned problems, and as a result, have a structure in which emitted light can be taken out without passing through the substrate, which results in excellent performance. It is possible to obtain a semiconductor light emitting device having That is, the present invention provides an n-type semiconductor layer made of a gallium nitride compound and a p-type or i-type on a transparent substrate.
P-type or i-type in a semiconductor light emitting device structure having at least one light emitting layer formed by combining type semiconductor layers, and an electrode being formed at a desired portion of the semiconductor layer for applying a voltage to the light emitting layer. The electrode having a semiconductor layer as a surface layer and having a pattern for uniformly applying a voltage to the surface layer made of the p-type or i-type semiconductor layer does not exceed 50% of the surface of the semiconductor surface layer. A semiconductor light emitting device characterized by covering with a range and extracting light from the electrode side thereof, and at least one metal layer on one substrate surface of the transparent substrate, and gallium nitride on the opposite substrate surface. There is at least one light emitting layer formed by combining an n-type semiconductor layer made of a compound and a p-type or i-type semiconductor layer, and an electrode is provided at a desired portion of the semiconductor layer for applying a voltage to the light emitting layer. In the formed semiconductor light emitting device structure, an electrode having a p-type or i-type semiconductor layer as a surface layer and having a pattern for uniformly applying a voltage to the surface layer made of the p-type or i-type semiconductor layer The semiconductor light emitting device is characterized in that the surface of the semiconductor surface layer is covered within a range not exceeding 50% and light is extracted from the electrode side.

【０００７】本発明においては、基板としては透明で表
面が平坦であれば良く、一般的に用いられるガラス、多
結晶基板、あるいは単結晶基板を用いることができる。
その例としては、石英ガラス、高ケイ酸ガラス等のガラ
スや、炭化ケイ素（ＳｉＣ）、酸化マグネシウム（Ｍｇ
Ｏ）、サファイア（Ａｌ2Ｏ3）、石英（ＳｉＯ2）、酸
化チタン（ＴｉＯ2）、チタン酸ストロンチウム（Ｓｒ
ＴｉＯ3）、ランタンアルミネート（ＬａＡｌＯ3）等の
単結晶基板がある。なかでも、上記のような単結晶基板
において、該基板上に直接形成する窒化ガリウム系半導
体の少なくとも一つの格子定数の整数倍が、該単結晶基
板の格子定数の整数倍とと５％以下、好ましくは２％以
下のミスマッチとなるような表面を出した単結晶基板を
用いることが好ましいものとなる。このような表面を有
する基板を得る方法としては、単結晶基板の適当な面を
基準として、これから所望の角度だけ傾いた面が出るよ
うに結晶を成長させるか、基準となる面を有する結晶を
成長した後にカッティング・研磨することにより行うこ
とができる。これにより、この基板上に結晶性の良好な
窒化ガリウム系半導体薄膜を形成することが可能とな
る。この場合に、基板面のＲＨＥＥＤ（Ｒｅｆｒａｃｔ
ｉｖｅ Ｈｉｇｈ Ｅｎｅｒｇｙ Ｅｌｅｃｔｒｏｎ
Ｄｉｆｆｒａｃｔｉｏｎ）パターンにおいてストリーク
パターンが観察できる基板であればさらに良質な窒化ガ
リウム系半導体薄膜を得ることができる。さらに、一般
的に用いられるガラス、多結晶基板あるいは単結晶基板
の上に、窒化ガリウム系半導体の格子定数が、該単結晶
基板の格子定数の整数倍と５％以下のミスマッチとなる
ような単結晶あるいは高配向性の薄膜を形成せしめて、
その上に目的とする窒化ガリウム系半導体薄膜を成長す
ることもできる。In the present invention, the substrate may be transparent and has a flat surface, and commonly used glass, polycrystalline substrate, or single crystal substrate can be used.
Examples thereof include glass such as quartz glass and high silicate glass, silicon carbide (SiC), magnesium oxide (Mg).
O), sapphire (Al 2 O 3 ), quartz (SiO 2 ), titanium oxide (TiO 2 ), strontium titanate (Sr)
There are single crystal substrates such as TiO 3 ) and lanthanum aluminate (LaAlO 3 ). Among them, in the single crystal substrate as described above, an integer multiple of at least one lattice constant of the gallium nitride-based semiconductor formed directly on the substrate is an integer multiple of the lattice constant of the single crystal substrate and 5% or less, It is preferable to use a single crystal substrate having a surface that gives a mismatch of preferably 2% or less. As a method for obtaining a substrate having such a surface, the crystal is grown so that a plane inclined by a desired angle from the appropriate plane of the single crystal substrate is used as a reference, or a crystal having a reference plane is used. It can be performed by cutting and polishing after the growth. This makes it possible to form a gallium nitride-based semiconductor thin film having good crystallinity on this substrate. In this case, the RHEED (Refract) of the substrate surface
Ive High Energy Electron
If a streak pattern can be observed in the Diffraction pattern, a higher quality gallium nitride based semiconductor thin film can be obtained. Furthermore, on a commonly used glass, polycrystal substrate or single crystal substrate, a single crystal substrate in which the lattice constant of the gallium nitride-based semiconductor is a mismatch of 5% or less with an integer multiple of the lattice constant of the single crystal substrate. Form a crystal or highly oriented thin film,
A desired gallium nitride-based semiconductor thin film can be grown on it.

【０００８】本発明において、窒化ガリウム系化合物と
はガリウム単独からなるＧａＮ半導体あるいはガリウム
とＩＩＩ族元素からなるガリウム系混晶半導体のことで
ある。ガリウム系混晶半導体としてはＧａＩｎＮ、Ｇａ
ＡｌＮ、ＧａＩｎＡｌＮ、ＧａＡｌＢＮ等があるがとく
にこれらに限定されるものではない。窒化ガリウム系化
合物の導電型を制御するためには適当な不純物をドーピ
ングすればよいが、ｎ型ドーパントの例としてはＳｉ、
Ｇｅ、Ｃ、Ｓｎ、Ｓｅ、Ｔｅ等があり、ｐ型ドーパント
の例としてはＭｇ、Ｃａ、Ｓｒ、Ｚｎ、Ｂｅ、Ｃｄ、Ｈ
ｇやＬｉ等がある。これらのドーパントの種類とドーピ
ング量を変えることによってキャリアーの種類やキャリ
アー密度を変えることができる。また、この時に膜厚の
方向によりドーピングする濃度を変えた構造としたり、
特定の層のみにドーピングするδドーピング層を設けた
構造とすることもできる。ドーピングの方法としては、
窒化ガリウム系半導体薄膜を形成しながら、あるいは薄
膜作製後にイオン注入や拡散法等によって行うことがで
きる。In the present invention, the gallium nitride-based compound is a GaN semiconductor composed of gallium alone or a gallium-based mixed crystal semiconductor composed of gallium and a group III element. GaInN, Ga as the gallium-based mixed crystal semiconductor
There are AlN, GaInAlN, GaAlBN and the like, but the material is not particularly limited to these. In order to control the conductivity type of the gallium nitride-based compound, it suffices to dope appropriate impurities, but Si is an example of an n-type dopant.
Ge, C, Sn, Se, Te, etc., and examples of p-type dopants are Mg, Ca, Sr, Zn, Be, Cd, H.
g and Li. The type of carrier and the carrier density can be changed by changing the type and doping amount of these dopants. Also, at this time, the structure in which the doping concentration is changed depending on the film thickness direction,
It is also possible to have a structure in which a δ-doping layer is provided for doping only a specific layer. As a method of doping,
This can be performed while forming the gallium nitride-based semiconductor thin film or after forming the thin film by ion implantation or diffusion.

【０００９】本発明の半導体発光装置としては、少なく
とも一種類のｎ型窒化ガリウム系半導体層およびｐ型あ
るいはｉ型半導体層を組み合わせてなる発光層を有し、
その発光層はこれらの半導体層を適当に組み合わせれば
よく、たとえばｎ／ｉ、ｎ／ｐ、ｎ／ｉ／ｐ、ｎ+／ｎ
／ｐ、ｎ+／ｎ／ｉ、ｎ／ｐ／ｐ+等のような構造を有
し、さらにそれぞれの層は組成の異なる単結晶窒化ガリ
ウム系半導体層を用いることも可能である。また、単結
晶窒化ガリウム系半導体からなる量子井戸構造を形成せ
しめて、発光効率を高めたり発光波長を制御することも
できる。The semiconductor light emitting device of the present invention has a light emitting layer formed by combining at least one type of n-type gallium nitride based semiconductor layer and p-type or i-type semiconductor layer,
The light emitting layer may be formed by appropriately combining these semiconductor layers, and for example, n / i, n / p, n / i / p, n + / n
It is also possible to use a single crystal gallium nitride based semiconductor layer having a structure such as / p, n + / n / i, n / p / p + and the like, and each layer having a different composition. Further, by forming a quantum well structure made of a single crystal gallium nitride based semiconductor, it is possible to enhance the light emission efficiency and control the light emission wavelength.

【００１０】半導体発光装置の構造の例としては、図３
に示すｎ−ＧａＮ／ｐ−ＧａＮや図４に示すｎ−Ｇａ
1-xＩｎxＮ／ｐ−Ｇａ1-xＩｎxＮの他に、ｎ−Ｇａ1-x
ＡｌxＮ／ｐ−Ｇａ1-xＡｌxＮ、ｎ−ＧａＮ／ｐ−Ｇａ
Ｎ、ｎ−Ｇａ1-xＩｎxＮ／ｐ−Ｇａ1-yＩｎyＮ（０≦ｘ
≦１、０≦ｙ≦１）、あるいは図５に示すｎ+−ＧａＮ
／ｎ−ＧａＮ／ｐ−ＧａＮ、図６に示すｎ−Ｇａ1-xＩ
ｎxＮ／ｉ−Ｇａ1-yＩｎyＮ／ｐ−Ｇａ1-xＩｎxＮ（ｘ
≦ｙ、０≦ｘ≦１、０≦ｙ≦１）、図７に示すｎ−Ｇａ
1-xＩｎxＮ／ｐ−Ｇａ1-yＩｎyＮ／ｐ−Ｇａ1-xＩｎxＮ
（ｘ≦ｙ、０≦ｘ≦１、０≦ｙ≦１）、図８に示すｎ−
Ｇａ1-xＡｌxＮ／ｉ−Ｇａ1-yＡｌyＮ／ｐ−Ｇａ1-xＡ
ｌxＮ（ｘ≦ｙ、０≦ｘ≦１、０≦ｙ≦１）、図９に示
すｎ−Ｇａ1-x-yＩｎxＡｌyＮ／ｉ−Ｇａ1-a-bＩｎaＡ
ｌbＮ／ｐ−Ｇａ1-x-yＩｎxＡｌyＮ（ｘ＋ｙ≦ａ＋ｂ、
０≦ｘ≦１、０≦ｙ≦１、０≦ａ≦１、０≦ｂ≦１）、
図１０に示すｎ−ＧａＮ／ｐ−ＧａＮ／ｎ−Ｇａ1-xＩ
ｎxＮ／ｐ−Ｇａ1-xＩｎxＮ（０≦ｘ≦１）、図１１に
示すＧａＩｎＮ系組成傾斜構造／ｎ−Ｇａ1-xＩｎxＮ／
ｐ−Ｇａ1-xＩｎxＮ（０≦ｘ≦１）、図１２に示すｎ−
Ｇａ1-xＩｎxＮ／量子井戸構造／ｐ−Ｇａ1-xＩｎxＮ
（０≦ｘ≦１）、図１３に示すＧａＮ−ＧａＩｎＮ歪超
格子層／ｎ−Ｇａ1-xＩｎxＮ／ｐ−Ｇａ1-xＩｎxＮ（０
≦ｘ≦１）等がある。ここで、組成傾斜構造とは基板側
から発光層側へ順次混晶の組成を変化せしめて格子整合
をとることにより発光層の特性を向上することを可能と
したもので、歪超格子層とは組成の異なる数百オングス
トローム以下の超薄膜を交互に積層して基板と発光層の
間の歪を緩和して発光特性を向上することを可能とした
ものである。量子井戸構造とは量子効果が発現する数百
オングストローム以下の厚さの窒化ガリウム系半導体混
晶の活性層をそれよりもバンドギャップの大きな窒化ガ
リウム系半導体混晶のクラッド層ではさんだ構造であ
る。このような構造を一つ有する単一量子井戸構造や、
この量子井戸構造を薄いバリア層で隔てて多層に積層し
た多重量子井戸構造とすることにより、発光効率を高め
たり、発光のしきい値電流を低くすることも可能であ
る。また図１４にはｎ−Ｇａ1-xＩｎxＮ／ｐ−Ｇａ1-x
ＩｎxＮ／ｎ−Ｇａ1-yＩｎyＮ／ｐ−Ｇａ1-yＩｎyＮ
（０≦ｘ≦１、０≦ｙ≦１）のような発光層を２層有す
るような構造を示す。この場合、たとえば電極２２イと
電極２２ロの間に電圧を印加すると青色の発光を、電極
２２ハと電極２３の間に電圧を印加すると緑色の発光
を、電極２２イと電極２３の間に電圧を印加すると黄色
の発光色を得ることができる。このように電圧を印加す
る電極を選ぶことによって二つの異なった発光色や中間
色を発光できる素子を得ることが可能となる。As an example of the structure of the semiconductor light emitting device, FIG.
N-GaN / p-GaN shown in FIG. 4 and n-Ga shown in FIG.
1-x In x N / In addition to the p-Ga 1-x In x N, n-Ga 1-x
Al x N / p-Ga 1-x Al x N, n-GaN / p-Ga
N, n-Ga 1-x In x N / p-Ga 1-y In y N (0 ≦ x
≦ 1, 0 ≦ y ≦ 1), or n + -GaN shown in FIG.
/ N-GaN / p-GaN, n-Ga 1-x I shown in FIG.
n x N / i-Ga 1 -y In y N / p-Ga 1-x In x N (x
≦ y, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1), n-Ga shown in FIG.
1-x In x N / p -Ga 1-y In y N / p-Ga 1-x In x N
(X ≦ y, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1), n− shown in FIG.
Ga 1-x Al x N / i-Ga 1-y Al y N / p-Ga 1-x A
l x N (x ≦ y, 0 ≦ x ≦ 1,0 ≦ y ≦ 1), n-Ga 1-xy In shown in FIG. 9 x Al y N / i- Ga 1-ab In a A
l b N / p-Ga 1 -xy In x Al y N (x + y ≦ a + b,
0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ a ≦ 1, 0 ≦ b ≦ 1),
N-GaN / p-GaN / n-Ga 1-x I shown in FIG.
n x N / p-Ga 1-x In x N (0 ≦ x ≦ 1), GaInN-based composition gradient structure / n-Ga 1-x In x N / shown in FIG. 11.
p-Ga 1-x In x N (0 ≦ x ≦ 1), n− shown in FIG.
Ga 1-x In x N / quantum well structure / p-Ga 1-x In x N
(0 ≦ x ≦ 1), GaN-GaInN strained superlattice layer / n-Ga 1-x In x N / p-Ga 1-x In x N (0
≦ x ≦ 1) and the like. Here, the compositionally graded structure is a structure in which the composition of the mixed crystal is sequentially changed from the substrate side to the light emitting layer side to achieve lattice matching, thereby improving the characteristics of the light emitting layer. Is capable of improving the light emission characteristics by alternately laminating ultrathin films having a composition of several hundred angstroms or less and relaxing the strain between the substrate and the light emitting layer. The quantum well structure is a structure in which a gallium nitride-based semiconductor mixed crystal active layer having a thickness of several hundred angstroms or less, in which a quantum effect is exhibited, is sandwiched by a gallium nitride-based semiconductor mixed crystal cladding layer having a larger band gap. A single quantum well structure having one such structure,
By forming this quantum well structure into a multi-quantum well structure in which the barrier layers are separated by a thin barrier layer and laminated in multiple layers, it is possible to increase the light emission efficiency and reduce the light emission threshold current. Further, in FIG. 14, n-Ga 1-x In x N / p-Ga 1-x
In x N / n-Ga 1 -y In y N / p-Ga 1-y In y N
A structure having two light emitting layers such as (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) is shown. In this case, for example, when a voltage is applied between the electrodes 22a and 22b, blue light is emitted, and when a voltage is applied between the electrodes 22c and 23, green light is emitted, and between the electrodes 22a and 23, a green light is emitted. A yellow emission color can be obtained by applying a voltage. By thus selecting the electrode to which the voltage is applied, it becomes possible to obtain an element capable of emitting two different emission colors and intermediate colors.

【００１１】本発明における窒化ガリウム系半導体薄膜
の全体膜厚としては、とくに限定はされないが、エッチ
ング等のプロセスを容易にするためには、５μｍ以下に
することが好ましく、さらに好ましくは３μｍ以下にす
ることである。本発明において、ｐ型あるいはｉ型半導
体層を基板側から一番遠い位置に設ける、すなわち表面
層となるが、その上に発光層に電圧を印加するための電
極を形成せしめる。ｐ型あるいはｉ型半導体層の表面に
均一に電圧を印加することが発光装置の発光輝度を上げ
たり、発光を半導体層の表面で均一に行うということで
好ましいものとなる。ｐ型あるいはｉ型半導体層の表面
に形成する電極の材料としてはＡｌ、Ｉｎ、Ｃｕ、Ａ
ｇ、Ａｕ、Ｐｔ、Ｉｒ、Ｐｄ、Ｒｈ、Ｗ、Ｔｉ、Ｎｉ等
の金属の単体あるいはそれらの合金やＰｔ、Ｗ、Ｍｏ等
のシリサイドを用いることができる。ｐ型あるいはｉ型
半導体層と直接に接触する電極の材料としては、仕事関
数が３．５ｅＶ以上であることが好ましく、さらに好ま
しくは４．０ｅＶ以上であり、これにより電極と該ｐ型
あるいはｉ型半導体層間のバリアーを小さくして良好な
オーミック特性を得ることができる。その場合、それら
の電極材料を一層のみとするか、あるいは積層構造とす
ることも可能である。とくに、Ｎｉ、Ｗ、Ｔｉのような
高融点の金属を積層する構造とすることにより、電極の
耐熱性、耐ボンディング性を向上せしめるのも好ましい
ものである。発光素子を均一に発光させるためにｐ型あ
るいはｉ型半導体層に均一に電圧を印加することが好ま
しく、さらに発光した光を電極側から取り出すために該
ｐ型あるいはｉ型半導体層の表面を電極が覆う面積は５
０％以下、好ましくは４０％以下、さらに好ましくは３
０％以下とすることである。そのために、電極はｐ型あ
るいはｉ型半導体層の表面上にパターンを形成すること
が必要で、パターンの例としては図１５に示すネット
状、図１６に示すクシ状、図１７に示すミアンダ状とす
ることができるが、さらにはこれらのパターンの組合せ
や渦状、島状等があるが、とくにこれらに限定されるも
のではない。電極の幅と電極間の距離はｐ型あるいはｉ
型半導体層の電気的抵抗や印加する電圧の大きさにより
変えればよく、電極の幅を狭くして、電極間の距離を小
さくすれば、光の取り出し効率が向上する。電極の幅を
サブミクロン程度とし、かつ電極間もサブミクロン程度
の間隔とすることによりｐ型あるいはｉ型半導体層の表
面に均一に電圧を印加するとともに光の取り出し効率も
大きくすることができる。The total thickness of the gallium nitride-based semiconductor thin film in the present invention is not particularly limited, but is preferably 5 μm or less, more preferably 3 μm or less in order to facilitate processes such as etching. It is to be. In the present invention, the p-type or i-type semiconductor layer is provided at the farthest position from the substrate side, that is, the surface layer, on which an electrode for applying a voltage to the light emitting layer is formed. It is preferable to apply a uniform voltage to the surface of the p-type or i-type semiconductor layer in order to increase the emission brightness of the light emitting device and to uniformly emit light on the surface of the semiconductor layer. The material of the electrode formed on the surface of the p-type or i-type semiconductor layer is Al, In, Cu, A
It is possible to use simple metals such as g, Au, Pt, Ir, Pd, Rh, W, Ti, and Ni, alloys thereof, and silicides such as Pt, W, and Mo. The material of the electrode that is in direct contact with the p-type or i-type semiconductor layer preferably has a work function of 3.5 eV or more, and more preferably 4.0 eV or more, whereby the electrode and the p-type or i-type It is possible to obtain a good ohmic characteristic by reducing the barrier between the type semiconductor layers. In that case, it is also possible to use only one layer of those electrode materials or to have a laminated structure. In particular, it is also preferable to improve the heat resistance and bonding resistance of the electrode by adopting a structure in which high melting point metals such as Ni, W and Ti are laminated. It is preferable to apply a uniform voltage to the p-type or i-type semiconductor layer in order to make the light-emitting element emit light uniformly, and further, to extract the emitted light from the electrode side, the surface of the p-type or i-type semiconductor layer is electrode Area covered by 5
0% or less, preferably 40% or less, more preferably 3
It is to be 0% or less. Therefore, the electrode needs to form a pattern on the surface of the p-type or i-type semiconductor layer, and examples of the pattern include a net shape shown in FIG. 15, a comb shape shown in FIG. 16, and a meander shape shown in FIG. The pattern may be a combination of these patterns, a spiral shape, an island shape, or the like, but is not particularly limited thereto. The width of the electrodes and the distance between the electrodes are p-type or i
It may be changed according to the electric resistance of the type semiconductor layer and the magnitude of the applied voltage. If the width of the electrodes is narrowed and the distance between the electrodes is reduced, the light extraction efficiency is improved. By setting the width of the electrodes to about submicron and the distance between the electrodes to be about submicron, it is possible to uniformly apply a voltage to the surface of the p-type or i-type semiconductor layer and increase the light extraction efficiency.

【００１２】また、本発明においては、透明基板上の窒
化ガリウム系化合物が形成されていない面上に図１８に
示すような少なくとも一層の金属層を設けることも好ま
しいものとなる。この金属層は窒化ガリウム系化合物の
ｎ型半導体層およびｐ型あるいはｉ型半導体層を組み合
わせてなる発光層において発光して基板を通して出てく
る光を反射して電極側から取り出すことを可能とするも
のである。これにより、発光素子の光の取り出し効率を
高めることができる。金属層として使われる材料として
は、Ａｌ、Ｉｎ、Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、Ｉｒ、Ｐ
ｄ、Ｒｈ、Ｗ、Ｍｏ、Ｔｉ、Ｎｉ等の金属の単体あるい
はそれらの合金がある。金属層は、一層だけでもよい
が、反射鏡付きフレームにパッケージするときの耐ハン
ダ性、耐熱性や耐ボンディング性等を向上せしめるため
に、Ｎｉ、Ｗ、Ｍｏ等の高融点の金属を積層した構造と
することも好ましいものとなる。Further, in the present invention, it is also preferable to provide at least one metal layer as shown in FIG. 18 on the surface of the transparent substrate on which the gallium nitride compound is not formed. This metal layer emits light in a light emitting layer formed by combining an n-type semiconductor layer and a p-type or i-type semiconductor layer of a gallium nitride-based compound, and makes it possible to reflect the light emitted through the substrate and take it out from the electrode side. It is a thing. Thereby, the light extraction efficiency of the light emitting element can be improved. Materials used for the metal layer include Al, In, Cu, Ag, Au, Pt, Ir and P.
There are simple metals such as d, Rh, W, Mo, Ti and Ni or alloys thereof. The metal layer may be a single layer, but in order to improve solder resistance, heat resistance, bonding resistance, etc. when packaged in a frame with a reflecting mirror, a high melting point metal such as Ni, W, Mo is laminated. A structure is also preferable.

【００１３】つぎに本発明の発光素子の製造方法につい
て説明する。本発明においては、窒化ガリウム系化合物
からなる半導体薄膜の作製方法としては、ＣＶＤ（Ｃｈ
ｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）
法、ＭＯＣＶＤ（Ｍｅｔａｌ Ｏｒｇａｎｉｃ Ｃｈｅ
ｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｏｎ）法、ガ
スソースＭＢＥ（Ｍｏｌｅｃｕｌａｒ Ｂｅａｍ Ｅｐ
ｉｔａｘｙ））法等がある。なかでも有機化合物を用い
ず、高真空中で薄膜成長が可能なガスソースＭＢＥ法が
良質な窒化ガリウム系半導体薄膜を作製できるという点
で好ましいものである。Next, a method of manufacturing the light emitting device of the present invention will be described. In the present invention, as a method for producing a semiconductor thin film made of a gallium nitride-based compound, a CVD (Ch
electronic vapor Deposition)
Method, MOCVD (Metal Organic Che
method, gas source MBE (Molecular Beam Ep)
Itaxy)) method. Among them, the gas source MBE method capable of growing a thin film in a high vacuum without using an organic compound is preferable in that a good quality gallium nitride based semiconductor thin film can be produced.

【００１４】以下、ガスソースＭＢＥ法において、窒素
を含有するガス状化合物のガスソースとＧａ固体ソース
を併用することにより、基板上に所望の窒化ガリウム系
半導体からなる積層構造を作製する方法について説明す
る。ここで、窒素を含有するガス状化合物としては、ア
ンモニアガス、三フッ化窒素、ヒドラジン、ジメチルヒ
ドラジン等を単独で、あるいはアンモニアガス、三フッ
化窒素、ヒドラジン、ジメチルヒドラジン等を主体とす
る混合ガスを用いることができる。混合ガスとしては、
上記のような化合物を窒素、アルゴンやヘリウム等の不
活性ガスで希釈して使用することも可能である。窒素を
含有するガス状化合物の供給量は基板表面においてＧａ
の供給量より大きくする必要があり、窒素を含有するガ
ス状化合物の供給量がＧａの供給量より小さくなると生
成するＧａＮ半導体薄膜からの窒素の抜けが大きくなる
ため良好なＧａＮ半導体薄膜を得ることが困難となる。
したがって、窒素を含有するガス状化合物の供給量は固
体ソースより１０倍以上、好ましくは１００倍以上、さ
らに好ましくは１０００倍以上にすることである。窒素
を含有するガス状化合物の供給方法としてはガスセルを
用いればよく、これは窒化ボロン、アルミナ、石英、ス
テンレスなどの管を基板面に開口部を向けて薄膜成長装
置内に設置し、バルブや流量制御装置、圧力制御装置を
接続することにより供給量の制御や供給の開始・停止を
行うことをできるようにしたものである。また、クラッ
キングガスセルを使用することもアンモニアガス、三フ
ッ化窒素、ヒドラジンやジメチルヒドラジン等を活性化
した状態で基板表面に効率的に供給するということで好
ましいものとなる。クラッキングガスセルとは、触媒の
存在下においてアンモニアガス、三フッ化窒素、ヒドラ
ジンやジメチルヒドラジン等を加熱し、効率良く活性化
せしめるものであって、触媒としてはアルミナ、シリ
カ、窒化ホウ素、炭化ケイ素のようなセラミックスを繊
維状あるいは多孔質状にして表面積を大きくすることが
好ましいものとなる。クラッキングの温度は触媒の種類
やアンモニアガス、三フッ化窒素、ヒドラジン、ジメチ
ルヒドラジン等の供給量等によって変えることが必要で
あるが、１００〜６００℃の範囲に設定することが好ま
しいものとなる。In the gas source MBE method, a method for producing a desired laminated structure of a gallium nitride based semiconductor on a substrate by using a gas source of a gaseous compound containing nitrogen and a Ga solid source will be described below. To do. Here, as the nitrogen-containing gaseous compound, ammonia gas, nitrogen trifluoride, hydrazine, dimethylhydrazine or the like alone, or a mixed gas mainly containing ammonia gas, nitrogen trifluoride, hydrazine, dimethylhydrazine, etc. Can be used. As a mixed gas,
It is also possible to dilute and use the above compounds with an inert gas such as nitrogen, argon or helium. The supply amount of the nitrogen-containing gaseous compound is Ga on the substrate surface.
It is necessary to obtain a good GaN semiconductor thin film, because when the supply amount of the nitrogen-containing gaseous compound is smaller than the supply amount of Ga, the amount of nitrogen released from the GaN semiconductor thin film generated becomes large. Becomes difficult.
Therefore, the supply amount of the nitrogen-containing gaseous compound is 10 times or more, preferably 100 times or more, more preferably 1000 times or more that of the solid source. A gas cell may be used as a method of supplying the nitrogen-containing gaseous compound, which is a tube of boron nitride, alumina, quartz, stainless steel or the like installed in the thin film growth apparatus with the opening facing the substrate surface. By connecting a flow rate control device and a pressure control device, it is possible to control the supply amount and start / stop the supply. It is also preferable to use a cracking gas cell because ammonia gas, nitrogen trifluoride, hydrazine, dimethylhydrazine and the like are efficiently supplied to the substrate surface in an activated state. The cracking gas cell is one that heats ammonia gas, nitrogen trifluoride, hydrazine and dimethylhydrazine etc. in the presence of a catalyst to efficiently activate them, and as a catalyst, alumina, silica, boron nitride, or silicon carbide is used. It is preferable to make such ceramics fibrous or porous to increase the surface area. The cracking temperature needs to be changed depending on the type of catalyst, the supply amount of ammonia gas, nitrogen trifluoride, hydrazine, dimethylhydrazine, etc., but it is preferably set in the range of 100 to 600 ° C.

【００１５】ガスソースＭＢＥ法により窒化ガリウム系
半導体薄膜を作製するうえで、Ｇａ、ＩｎやＡｌのよう
なＩＩＩ属金属元素と窒素を含有するガス状化合物を同
時に基板面に供給したり、Ｇａと窒素を含有するガス状
化合物を交互に基板面に供給したり、あるいは薄膜成長
時に成長中断して結晶化を促進したりする方法を行うこ
ともできる。とくに、ＲＨＥＥＤ（Ｒｅｆｒａｃｔｉｖ
ｅ Ｈｉｇｈ Ｅｎｅｒｇｙ Ｅｌｅｃｔｒｏｎ Ｄｉ
ｆｆｒａｃｔｉｏｎ）パターンを観察してストリークが
見えることを確認しながら膜成長を行うことは好ましい
ものである。In producing a gallium nitride based semiconductor thin film by the gas source MBE method, a gaseous compound containing nitrogen and a group III metal element such as Ga, In or Al is simultaneously supplied to the substrate surface, or Ga A method of alternately supplying a nitrogen-containing gaseous compound to the substrate surface, or interrupting the growth during thin film growth to promote crystallization can also be performed. Especially, RHEED (Refractive)
e High Energy Electron Di
It is preferable to carry out film growth while observing a fracture pattern to confirm that streaks are visible.

【００１６】以下、一例としてアンモニアガスを用いた
ガスソースＭＢＥ法により作製した窒化ガリウム系半導
体薄膜からなる発光素子の製造方法について説明する
が、とくにこれに限定されるものではない。装置として
は、図１に示すような真空容器１内に、蒸発用ルツボ
（クヌードセンセル）２、３、４および５、クラッキン
グガスセル６、基板加熱ホルダー７、および四重極子質
量分析器９、ＲＨＨＥＤガン１０、およびＲＨＥＥＤス
クリーン１１を備えたガスソースＭＢＥ装置を用いた。Hereinafter, as an example, a method of manufacturing a light emitting device made of a gallium nitride based semiconductor thin film manufactured by a gas source MBE method using ammonia gas will be described, but the invention is not particularly limited thereto. As an apparatus, in a vacuum container 1 as shown in FIG. 1, an evaporation crucible (Knudsen cell) 2, 3, 4 and 5, a cracking gas cell 6, a substrate heating holder 7, and a quadrupole mass analyzer 9 are provided. , A RHHED gun 10 and a RHEED screen 11 were used for the gas source MBE apparatus.

【００１７】蒸発用ルツボ２にはＧａ金属を入れ、基板
面において１０13〜１０19／cm2・secになる温度に加熱
した。アンモニアガスや三フッ化窒素の導入にはクラッ
キングガスセル６を用い、アンモニアガスや三フッ化窒
素を基板８に直接吹き付けるように設置した。導入量は
基板表面において１０16〜１０20／cm2・secになるよう
に供給した。蒸発用ルツボ４および５にはＭｇ、Ｃａ、
Ｚｎ、Ｂｅ、Ｃｄ、Ｓｒ、Ｈｇ、Ｌｉ等のｐ型ドーパン
トやＳｉ、Ｇｅ、Ｓｎ、Ｃ、Ｓｅ、Ｔｅ等のｎ型ドーパ
ントを入れ、所定の供給量になるように温度および供給
時間を制御することによりドーピングを行なう。Ga metal was placed in the evaporation crucible 2 and heated to a temperature of 10 13 to 10 19 / cm 2 · sec on the substrate surface. A cracking gas cell 6 was used to introduce ammonia gas or nitrogen trifluoride, and the ammonia gas or nitrogen trifluoride was installed so as to be directly sprayed onto the substrate 8. The amount introduced was 10 16 to 10 20 / cm 2 · sec on the surface of the substrate. For the evaporation crucibles 4 and 5, Mg, Ca,
Inserting p-type dopants such as Zn, Be, Cd, Sr, Hg, Li or n-type dopants such as Si, Ge, Sn, C, Se, Te, etc., and controlling the temperature and supply time so as to obtain a predetermined supply amount. By doing so, doping is performed.

【００１８】基板８としては、サファイアＲ面からサフ
ァイアｃ軸のＲ面射影を回転軸として９．２度回転させ
た面を使用し、２００〜９００℃に加熱した。まず、基
板８を真空容器１内で９００℃で加熱した後、所定の成
長温度に設定し、０．１〜３０オングストローム／sec
の成長速度で膜厚０．１〜３μｍのｎ型ＧａＮ半導体薄
膜を、ついで蒸発用ルツボ２および蒸発用ルツボ４のＭ
ｇのシャッターを同時に開けて膜厚０．０１〜２μｍの
ｐ型あるいはｉ型ＧａＮ半導体薄膜を形成せしめ、発光
素子用の積層薄膜を作製した。本発明において、ＲＨＥ
ＥＤのストリークパターンを見ながら膜成長を行うこと
は好ましいものである。As the substrate 8, a surface rotated from the R-plane of the sapphire by 9.2 degrees with the R-plane projection of the sapphire c-axis as the axis of rotation was used and heated to 200 to 900 ° C. First, the substrate 8 is heated in the vacuum container 1 at 900 ° C., then set to a predetermined growth temperature, and 0.1 to 30 Å / sec is set.
N-type GaN semiconductor thin film having a film thickness of 0.1 to 3 μm at a growth rate of M, and then M of the evaporation crucible 2 and the evaporation crucible 4.
The shutter of g was opened at the same time to form a p-type or i-type GaN semiconductor thin film having a film thickness of 0.01 to 2 μm, and a laminated thin film for a light emitting device was produced. In the present invention, RHE
It is preferable to grow the film while watching the streak pattern of the ED.

【００１９】ついで、該積層薄膜にプロセシングを行う
ことにより、素子の形状を決めるとともに電圧を印可す
るための電極を設ける。リソグラフィープロセスは通常
のフォトレジスト材料を用いる一般的なプロセスで行う
ことができ、エッチング法としてはドライエッチング法
を用いることが好ましい。ドライエッチング法として
は、イオンミリング、ＥＣＲエッチング、反応性イオン
エッチング、イオンビームアシストエッチング、集束イ
オンビームエツチングを用いることができる。とくに本
発明においては、窒化ガリウム系半導体の積層薄膜の全
体膜厚が小さいためにこれらのドライエッチング法が効
率的に適用できるのも特長の一つである。Then, by processing the laminated thin film, the shape of the element is determined and an electrode for applying a voltage is provided. The lithography process can be performed by a general process using an ordinary photoresist material, and it is preferable to use a dry etching method as the etching method. As the dry etching method, ion milling, ECR etching, reactive ion etching, ion beam assisted etching, focused ion beam etching can be used. In particular, one of the features of the present invention is that these dry etching methods can be efficiently applied because the total thickness of the laminated thin film of gallium nitride-based semiconductor is small.

【００２０】ｐ型あるいはｉ型半導体層の表面に均一に
電圧を印加するための電極の材料としてはＡｌ、Ｉｎ、
Ｃｕ、Ａｇ、Ａｕ、Ｐｔ、Ｉｒ、Ｐｄ、Ｒｈ、Ｗ、Ｔ
ｉ、Ｎｉ等の金属の単体あるいはそれらの合金やＰｔ、
Ｗ、Ｍｏ等のシリサイドを用いることができる。電極
は、ＭＢＥ法、ＣＶＤ法、真空蒸着法、電子ビーム蒸着
法やスパッタ法により作製することができる。また、発
光層が形成されている面と反対側の面上に形成する金属
層の材料としてはＡｌ、Ｉｎ、Ｃｕ、Ａｇ、Ａｕ、Ｐ
ｔ、Ｉｒ、Ｐｄ、Ｒｈ、Ｗ、Ｔｉ、Ｎｉ等の金属の単体
あるいはそれらの合金を用いることができる。それらの
金属層は、ＭＢＥ法、ＣＶＤ法、真空蒸着法、電子ビー
ム蒸着法やスパッタ法により作製することができる。ま
た、金属の積層構造を作製する場合にはこれらの方法を
組み合わせることにより行うことができる。As a material of the electrode for uniformly applying a voltage to the surface of the p-type or i-type semiconductor layer, Al, In,
Cu, Ag, Au, Pt, Ir, Pd, Rh, W, T
i, Ni and other metals alone or their alloys or Pt,
A silicide such as W or Mo can be used. The electrodes can be manufactured by the MBE method, the CVD method, the vacuum evaporation method, the electron beam evaporation method or the sputtering method. The material of the metal layer formed on the surface opposite to the surface on which the light emitting layer is formed is Al, In, Cu, Ag, Au, P.
A simple substance of metal such as t, Ir, Pd, Rh, W, Ti and Ni or an alloy thereof can be used. Those metal layers can be formed by the MBE method, the CVD method, the vacuum evaporation method, the electron beam evaporation method or the sputtering method. Further, in the case of producing a metal laminated structure, these methods can be combined.

【００２１】このような方法によって得られたウエハー
をダイシングソー等で切断し、ワイヤーボンダーにより
金線を用いて配線し、エポキシ系樹脂、メタクリル系樹
脂やカーボネート系樹脂等によるパッケージを行い、発
光素子を作製した。The wafer obtained by such a method is cut with a dicing saw or the like, wired with a gold wire by a wire bonder, packaged with epoxy resin, methacrylic resin, carbonate resin, etc. Was produced.

【００２２】[0022]

【実施例】以下、実施例によりさらに詳細に説明する。
発光強度は発光表面から垂直軸上２０ｃｍの距離で測定
した。EXAMPLES The present invention will be described in more detail below with reference to examples.
The emission intensity was measured at a distance of 20 cm on the vertical axis from the emission surface.

【００２３】[0023]

【実施例１】アンモニアガスを用いたガスソースＭＢＥ
法により、サファイア基板上にＧａＮ半導体積層薄膜を
成長し、それを使用した青色の発光素子を作製した例に
ついて説明する。図１に示すような真空容器１内に、蒸
発用ルツボ２、３、４および５、クラッキングガスセル
６、基板加熱ホルダー７、四重極質量分析器９、ＲＨＥ
ＥＤ用電子銃１０、およびＲＨＥＥＤスクリーン１１を
備えたガスソースＭＢＥ装置を用いた。Example 1 Gas source MBE using ammonia gas
An example in which a GaN semiconductor laminated thin film is grown on a sapphire substrate by a method and a blue light emitting device using the same is manufactured will be described. In a vacuum container 1 as shown in FIG. 1, evaporation crucibles 2, 3, 4 and 5, a cracking gas cell 6, a substrate heating holder 7, a quadrupole mass spectrometer 9, and a RHE.
A gas source MBE device equipped with an ED electron gun 10 and a RHEED screen 11 was used.

【００２４】蒸発用ルツボ２にはＧａ金属を入れ１０２
０℃に加熱し、蒸発用ルツボ５ロにはＺｎ金属を入れ１
９０℃に加熱した。ガスの導入には内部にアルミナファ
イバーを充填したクラッキングガスセル６を使用し、４
００℃に加熱して、ガスを直接に基板７に吹き付けるよ
うにして５cc／minの速度で供給した。基板８としては
２０mm角の大きさのサファイアＲ面からサファイアｃ軸
のＲ面射影を回転軸として９．２度回転させた面を用い
た。Ga metal is put in the evaporation crucible 2 102
Heat to 0 ° C and put Zn metal into the evaporation crucible 5
Heated to 90 ° C. A cracking gas cell 6 filled with alumina fibers was used to introduce the gas.
It was heated to 00 ° C., and the gas was directly blown onto the substrate 7 so that the gas was supplied at a rate of 5 cc / min. As the substrate 8, a surface obtained by rotating a sapphire R surface having a size of 20 mm square and rotating it by 9.2 degrees with the R surface projection of the sapphire c-axis as the rotation axis was used.

【００２５】真空容器内の圧力は、成膜時において１×
１０-6Torrであった。まず、基板８を９００℃で３０分
間加熱し、ついで７００℃の温度に保持し成膜を行う。
成膜はアンモニアガスをクラッキングガスセル６から供
給しながら、まずＧａのシャッター１３を開け、１．０
オングストローム／secの成膜速度で膜厚６０００オン
グストロームのｎ−ＧａＮ半導体層を作製する。つぎ
に、シャッター１３とともにシャッター１６ロを開け該
ＧａＮ半導体薄膜上に８００オングストロームのＺｎを
ドーピングしたｐ−ＧａＮ半導体層を成長し、ＧａＮ半
導体積層薄膜を作製した。The pressure in the vacuum container is 1 × during film formation.
It was 10 -6 Torr. First, the substrate 8 is heated at 900 ° C. for 30 minutes and then maintained at a temperature of 700 ° C. to form a film.
For film formation, while supplying ammonia gas from the cracking gas cell 6, first the Ga shutter 13 is opened to 1.0
An n-GaN semiconductor layer having a film thickness of 6000 angstrom is formed at a film forming rate of angstrom / sec. Next, the shutter 16 and the shutter 16 were opened, and a p-GaN semiconductor layer doped with 800 Å of Zn was grown on the GaN semiconductor thin film to prepare a GaN semiconductor laminated thin film.

【００２６】ついで、微細加工プロセスを適用すること
により、素子パターンの作製および電極の形成を行う。
リソグラフィープロセスは通常のフォトレジスト材料を
用いるプロセスにより行うことができ、エッチング法と
してはイオンミリング法により、素子パターンの作製を
行った。ついで、ｎ−ＧａＮ半導体層にはＡｌ電極を、
ｐ−ＧａＮ半導体層には電極幅が２０μｍで電極間距離
が５０μｍのネット状のＡｕ電極（表面の２５％を覆
う）をそれぞれ真空蒸着法によって形成した。この素子
の断面構造を図３に、ダイオード特性を図２に示す。Then, by applying a fine processing process, an element pattern is formed and electrodes are formed.
The lithography process can be performed by a process using an ordinary photoresist material, and an element pattern is produced by an ion milling method as an etching method. Next, an Al electrode is formed on the n-GaN semiconductor layer,
Net-shaped Au electrodes (covering 25% of the surface) having an electrode width of 20 μm and an inter-electrode distance of 50 μm were formed on the p-GaN semiconductor layer by a vacuum deposition method. The cross-sectional structure of this element is shown in FIG. 3, and the diode characteristics are shown in FIG.

【００２７】この方法により得られた素子をダイシング
ソーで切断し、ワイヤーボンダーににより金線を用いて
配線を行った後、エポキシ樹脂によりパッケージングし
た。この素子の電極に１０Ｖの電圧を印加して１３ｍＡ
の電流を注入すると、発光強度が９０ｍｃｄの青色の発
光が観測された。The element obtained by this method was cut with a dicing saw, wired with a gold wire using a wire bonder, and then packaged with an epoxy resin. Applying a voltage of 10V to the electrode of this device,
When the current was injected, blue light emission with an emission intensity of 90 mcd was observed.

【００２８】[0028]

【実施例２】アンモニアガスを用いたガスソースＭＢＥ
法により、サファイア基板上にＧａＮ半導体積層薄膜を
成長し、それを使用した発光素子を作製した例について
説明する。図１に示すような真空容器１内に、蒸発用ル
ツボ２、３、４および５、クラッキングガスセル６、基
板加熱ホルダー７、四重極質量分析器９、ＲＨＥＥＤ用
電子銃１０、およびＲＨＥＥＤスクリーン１１を備えた
ガスソースＭＢＥ装置を用いた。[Example 2] Gas source MBE using ammonia gas
An example in which a GaN semiconductor laminated thin film is grown on a sapphire substrate by a method and a light emitting device using the same is manufactured will be described. In a vacuum container 1 as shown in FIG. 1, an evaporation crucible 2, 3, 4 and 5, a cracking gas cell 6, a substrate heating holder 7, a quadrupole mass analyzer 9, an RHEED electron gun 10 and an RHEED screen 11 are provided. The gas source MBE apparatus equipped with was used.

【００２９】蒸発用ルツボ２にはＧａ金属を入れ１０２
０℃に加熱し、蒸発用ルツボ５ロにはＺｎ金属を入れ１
９０℃に加熱した。ガスの導入には内部にアルミナファ
イバーを充填したクラッキングガスセル６を使用し、４
００℃に加熱して、ガスを直接に基板７に吹き付けるよ
うにして５cc／minの速度で供給した。基板８としては
２０mm角の大きさのオフ角が０．３度のサファイアＲ面
を用いた。Ga metal is put in the evaporation crucible 2 102
Heat to 0 ° C and put Zn metal into the evaporation crucible 5
Heated to 90 ° C. A cracking gas cell 6 filled with alumina fibers was used to introduce the gas.
It was heated to 00 ° C., and the gas was directly blown onto the substrate 7 so that the gas was supplied at a rate of 5 cc / min. As the substrate 8, a sapphire R surface having a size of 20 mm square and an off angle of 0.3 ° was used.

【００３０】真空容器内の圧力は、成膜時において１×
１０-6Torrであった。まず、基板８を９００℃で３０分
間加熱し、ついで７００℃の温度に保持し成膜を行う。
成膜はアンモニアガスをクラッキングガスセル６から供
給しながらまずシャッター１３を開け、１．０オングス
トローム／ｓｅｃの成長速度で１５００オングストロー
ムの厚みのｎ+−ＧａＮ半導体層を、続けて４５００オ
ングストロームのｎ−ＧａＮ半導体層を形成し、ついで
シャッター１３とともにシャッター１６ロを開けてＺｎ
をドーピングした５００オングスチロームの厚みのｐ−
ＧａＮ半導体層を形成しＧａＮ半導体積層薄膜を作製し
た。The pressure in the vacuum container is 1 × during film formation.
It was 10 -6 Torr. First, the substrate 8 is heated at 900 ° C. for 30 minutes and then maintained at a temperature of 700 ° C. to form a film.
For film formation, the shutter 13 is first opened while supplying ammonia gas from the cracking gas cell 6, and an n + -GaN semiconductor layer having a thickness of 1500 angstroms is continuously grown at a growth rate of 1.0 angstrom / sec, followed by 4500 angstroms of n-GaN. The semiconductor layer is formed, and then the shutter 16 and the shutter 16 are opened to form Zn.
Of 500 Å thick p-doped p-
A GaN semiconductor layer was formed to produce a GaN semiconductor laminated thin film.

【００３１】ついで、微細加工プロセスを適用すること
により、素子パターンの作製および電極の形成を行う。
リソグラフィープロセスは通常のフォトレジスト材料を
用いるプロセスにより行うことができ、エッチング法と
してはイオンミリング法により、素子パターンの作製を
行った。ついで、ｎ−ＧａＮ半導体層にはＡｌ電極を、
ｐ−ＧａＮ半導体層には電極幅が２０μｍで電極間距離
が５０μｍのネット状のＡｕ電極（表面の２５％を覆
う）をそれぞれ真空蒸着法によって形成した。この素子
の断面構造を図５に示す。Then, by applying a fine processing process, an element pattern is formed and electrodes are formed.
The lithography process can be performed by a process using an ordinary photoresist material, and an element pattern is produced by an ion milling method as an etching method. Next, an Al electrode is formed on the n-GaN semiconductor layer,
Net-shaped Au electrodes (covering 25% of the surface) having an electrode width of 20 μm and an inter-electrode distance of 50 μm were formed on the p-GaN semiconductor layer by a vacuum deposition method. The cross-sectional structure of this element is shown in FIG.

【００３２】この方法により得られた素子をダイシング
ソーで切断し、ワイヤーボンダーににより金線を用いて
配線を行った後、エポキシ樹脂によりパッケージングし
た。この素子の電極に１０Ｖの電圧を印加して１０ｍＡ
の電流を注入すると、発光強度が７０ｍｃｄの青色の発
光が観測された。The element obtained by this method was cut with a dicing saw, wired with a wire bonder using a gold wire, and then packaged with an epoxy resin. Applying a voltage of 10V to the electrode of this device,
When a current was injected, a blue light emission with an emission intensity of 70 mcd was observed.

【００３３】[0033]

【実施例 ３】ＧａＮ半導体積層薄膜が形成されていな
い基板面に金属層を形成する以外は、実施例２と同様の
方法によりＧａＮ半導体積層構造を作製した。金属層は
５０００オングストロームのＡｌ層とし、真空蒸着法に
より作製した。この素子の断面構造を図１８に示す。こ
の素子の電極に１０Ｖの電圧を印加して１０ｍＡの電流
を注入すると、発光強度が８０ｍｃｄの青色の発光が観
測された。Example 3 A GaN semiconductor laminated structure was produced in the same manner as in Example 2 except that a metal layer was formed on the surface of the substrate on which the GaN semiconductor laminated thin film was not formed. The metal layer was a 5000 angstrom Al layer and was formed by a vacuum deposition method. The cross-sectional structure of this element is shown in FIG. When a voltage of 10 V was applied to the electrode of this device and a current of 10 mA was injected, blue light emission with an emission intensity of 80 mcd was observed.

【００３４】[0034]

【実施例 ４】アンモニアガスを用いたガスソースＭＢ
Ｅ法により、サファイア基板上にＧａＩｎＮ組成傾斜構
造を成長し、その上にＧａＩｎＮ混晶からなる発光層を
形成し、それを使用した青色の発光素子を作製した例に
ついて説明する。図１に示すような真空容器１内に、蒸
発用ルツボ２、３、４および５、クラッキングガスセル
６、基板加熱ホルダー７、四重極質量分析器９、ＲＨＥ
ＥＤ用電子銃１０、およびＲＨＥＥＤスクリーン１１を
備えたガスソースＭＢＥを装置として用いた。Example 4 Gas source MB using ammonia gas
An example in which a GaInN composition gradient structure is grown on a sapphire substrate by the E method, a light emitting layer made of a GaInN mixed crystal is formed on the structure, and a blue light emitting element is manufactured using the same will be described. In a vacuum container 1 as shown in FIG. 1, evaporation crucibles 2, 3, 4 and 5, a cracking gas cell 6, a substrate heating holder 7, a quadrupole mass spectrometer 9, and a RHE.
A gas source MBE equipped with an electron gun 10 for ED and a RHEED screen 11 was used as an apparatus.

【００３５】蒸発用ルツボ２にはＧａ金属を入れ１０２
０℃に加熱し、蒸発用ルツボ３にはＩｎ金属を入れ８８
０℃に加熱し、蒸発用ルツボ５にはＭｇ金属を入れ２９
０℃に加熱した。ガスの導入には内部にアルミナファイ
バーを充填したクラッキングガスセル６を使用し、４０
０℃に加熱して、ガスを直接に基板７に吹き付けるよう
にして５cc／minの速度で供給した。Ga metal is put in the evaporation crucible 2 102
Heat to 0 ° C and put In metal into the evaporation crucible 3 88
Heat to 0 ° C and put Mg metal into the evaporation crucible 5 29
Heated to 0 ° C. A cracking gas cell 6 filled with alumina fibers was used to introduce the gas.
It was heated to 0 ° C., and the gas was directly blown onto the substrate 7 and supplied at a rate of 5 cc / min.

【００３６】基板８としては、２０mm角の大きさのサフ
ァイアＲ面からサファイアｃ軸のＲ面射影を回転軸とし
て９．２度回転させた面を用いた。真空容器内の圧力
は、成膜時において１×１０-6Torrであった。まず、基
板８を９００℃で３０分間加熱し、ついで７００℃の温
度に保持し成膜を行う。成膜はアンモニアガスをクラッ
キングガスセル６から供給しながら、まず１０秒間Ｇａ
のシャッター１３のみを開け、ついでＧａとＩｎのルツ
ボのシャッターを開けて、蒸発ルツボ３の温度を８８０
℃から９１０℃まで０．６℃／ｍｉｎの速度で昇温しな
がら、１．０オングストローム／secの成膜速度で、膜
厚３０００オングストロームのＧａＮからＧａ0.95Ｉｎ
0.05Ｎ組成傾斜構造を有するＧａＩｎＮ混晶薄膜を作製
する。つぎに、該ＧａＩｎＮ混晶薄膜上に２０００オン
グストロームのｎ型Ｇａ0.95Ｉｎ0.05Ｎ半導体層を成長
し、さらにその上に蒸発ルツボ２、３および５イのシャ
ッターを開けてＭｇをドーピングしたｐ型Ｇａ0.95Ｉｎ
0.05Ｎ半導体層を成長し、ＧａＩｎＮ混晶積層薄膜を作
製した。As the substrate 8, a surface obtained by rotating a sapphire R surface having a size of 20 mm square and rotating it by 9.2 degrees with the R surface projection of the sapphire c-axis as the rotation axis was used. The pressure in the vacuum container was 1 × 10 −6 Torr during film formation. First, the substrate 8 is heated at 900 ° C. for 30 minutes and then maintained at a temperature of 700 ° C. to form a film. For the film formation, while supplying ammonia gas from the cracking gas cell 6, first, Ga is supplied for 10 seconds.
Of the evaporation crucible 3 is opened to 880 by opening only the shutter 13 of, and then opening the shutter of the Ga and In crucibles.
GaN having a film thickness of 3000 angstroms and Ga 0.95 In at a film forming rate of 1.0 angstrom / sec while the temperature is increased from 0.6 ° C. to 910 ° C. at a rate of 0.6 ° C./min.
A GaInN mixed crystal thin film having a 0.05 N composition gradient structure is prepared. Next, a 2000 angstrom n-type Ga 0.95 In 0.05 N semiconductor layer was grown on the GaInN mixed crystal thin film, and the shutters of the evaporation crucibles 2, 3 and 5 were opened on the p-type Ga doped with Mg. 0.95 In
A 0.05N semiconductor layer was grown to prepare a GaInN mixed crystal laminated thin film.

【００３７】ついで、微細加工プロセスを適用すること
により、素子パターンの作製および電極の形成を行う。
リソグラフィープロセスは通常のフォトレジスト材料を
用いるプロセスにより行うことができ、エッチング法と
してはイオンミリング法により、素子パターンの作製を
行った。ついで、ｎ−ＧａＩｎＮ半導体層にはＡｌ電極
を、ｐ−ＧａＩｎＮ半導体層には電極幅が２０μｍで電
極間距離が５０μｍのネット状のＡｕ電極（表面の２５
％を覆う）をそれぞれ真空蒸着法によって形成した。こ
の素子の断面構造を図１１に、平面構造を図１５に示
す。Then, by applying a microfabrication process, a device pattern is formed and electrodes are formed.
The lithography process can be performed by a process using an ordinary photoresist material, and an element pattern is produced by an ion milling method as an etching method. Next, an Al electrode is formed on the n-GaInN semiconductor layer, and a net-shaped Au electrode having an electrode width of 20 μm and an interelectrode distance of 50 μm is formed on the p-GaInN semiconductor layer (25 on the surface).
%) Were each formed by a vacuum evaporation method. The cross-sectional structure of this element is shown in FIG. 11, and the plane structure is shown in FIG.

【００３８】この方法により得られた素子をダイシング
ソーで切断し、ワイヤーボンダーにより金線を用いて配
線を行った後、エポキシ樹脂によりパッケージングし
た。この素子の電極に１０Ｖの電圧を印加して１５ｍＡ
の電流を注入すると、発光強度が７０ｍｃｄの青色の発
光が観測された。The element obtained by this method was cut with a dicing saw, wired with a gold wire using a wire bonder, and then packaged with an epoxy resin. Applying a voltage of 10V to the electrode of this device, 15mA
When a current was injected, a blue light emission with an emission intensity of 70 mcd was observed.

【００３９】[0039]

【実施例５】実施例４において、ｐ−ＧａＩｎＮ半導体
積層薄膜上にネット状電極が形成されていない外は、実
施例４と同様の方法によりＧａＩｎＮ半導体積層構造を
作製した。該ｐ−ＧａＩｎＮ半導体積層薄膜上に、電極
幅が５０μｍで電極間距離が５０μｍのクシ状のＡｕ電
極（表面の２３％を覆う）を真空蒸着法により作製し
た。この素子の平面構造を図１６に示す。Fifth Embodiment A GaInN semiconductor laminated structure was manufactured by the same method as in the fourth embodiment except that the net-like electrode was not formed on the p-GaInN semiconductor laminated thin film. On the p-GaInN semiconductor laminated thin film, a comb-shaped Au electrode (covering 23% of the surface) having an electrode width of 50 μm and an interelectrode distance of 50 μm was produced by a vacuum deposition method. The planar structure of this element is shown in FIG.

【００４０】この方法により得られた素子をダイシング
ソーで切断し、ワイヤーボンダーにより金線を用いて配
線を行った後、エポキシ樹脂によりパッケージングし
た。この素子の電極に１０Ｖの電圧を印加して１３ｍＡ
の電流を注入すると、発光強度が６０ｍｃｄの青色の発
光が観測された。The element obtained by this method was cut with a dicing saw, wired with a gold wire using a wire bonder, and then packaged with an epoxy resin. Applying a voltage of 10V to the electrode of this device,
When the current was injected, blue emission with an emission intensity of 60 mcd was observed.

【００４１】[0041]

【実施例６】実施例４において、ｐ−ＧａＩｎＮ半導体
積層薄膜上にネット状電極が形成されていない外は、実
施例４と同様の方法によりＧａＩｎＮ半導体積層構造を
作製した。該ｐ−ＧａＩｎＮ半導体積層薄膜上に、電極
幅が５０μｍで電極間距離が５０μｍのミアンダ状のＡ
ｕ電極（表面の２０％を覆う）を真空蒸着法により作製
した。この素子の平面構造を図１７に示す。Example 6 A GaInN semiconductor laminated structure was produced in the same manner as in Example 4 except that the net-shaped electrode was not formed on the p-GaInN semiconductor laminated thin film in Example 4. On the p-GaInN semiconductor laminated thin film, a meandering A having an electrode width of 50 μm and an interelectrode distance of 50 μm was formed.
The u electrode (covering 20% of the surface) was produced by the vacuum evaporation method. The planar structure of this element is shown in FIG.

【００４２】この方法により得られた素子をダイシング
ソーで切断し、ワイヤーボンダーにより金線を用いて配
線を行った後、エポキシ樹脂によりパッケージングし
た。この素子の電極に１０Ｖの電圧を印加して１２ｍＡ
の電流を注入すると、発光強度が５５ｍｃｄの青色の発
光が観測された。The element obtained by this method was cut with a dicing saw, wired with a gold wire using a wire bonder, and then packaged with an epoxy resin. Applying a voltage of 10V to the electrode of this device, 12mA
When the current was injected, blue light emission with an emission intensity of 55 mcd was observed.

【００４３】[0043]

【発明の効果】本発明の発光素子においては、窒化ガリ
ウム系化合物からなる発光層を形成し、ｐ型あるいはｉ
型半導体層を表面層とし、その上に電圧を均一に印加す
るためのパターンを形成した電極を設け、電極側から光
を取り出すことにより、発光効率が優れた発光素子を得
ることができるという特長がある。In the light emitting device of the present invention, a light emitting layer made of a gallium nitride-based compound is formed, and p type or i type is formed.
A feature that a light emitting element with excellent light emission efficiency can be obtained by providing a patterned semiconductor layer as a surface layer, providing an electrode on which a pattern for uniformly applying a voltage is formed, and extracting light from the electrode side. There is.

【図面の簡単な説明】[Brief description of drawings]

【図１】薄膜作製に用いたガスソースＭＢＥ装置の概略
図である。FIG. 1 is a schematic view of a gas source MBE apparatus used for thin film production.

【図２】実施例１の素子の電流−電圧測定を示した図で
ある。2 is a diagram showing current-voltage measurement of the device of Example 1. FIG.

【図３】ｎ−ＧａＮ／ｐ−ＧａＮ構造発光素子の断面構
造を示した図である。FIG. 3 is a diagram showing a cross-sectional structure of an n-GaN / p-GaN structure light emitting device.

【図４】ｎ−Ｇａ1-xＩｎxＮ／ｐ−Ｇａ1-xＩｎxＮ構造
発光素子の断面構造を示した図である。FIG. 4 is a diagram showing a cross-sectional structure of an n-Ga 1-x In x N / p-Ga 1-x In x N structure light emitting device.

【図５】ｎ+−ＧａＮ／ｎ−ＧａＮ／ｐ−ＧａＮ構造発
光素子の断面構造を示した図である。FIG. 5 is a view showing a cross-sectional structure of an n + -GaN / n-GaN / p-GaN structure light emitting device.

【図６】ｎ−Ｇａ1-xＩｎxＮ／ｉ−Ｇａ1-yＩｎyＮ／ｐ
−Ｇａ1-xＩｎxＮ構造発光素子の断面構造を示した図で
ある。FIG. 6 n-Ga 1-x In x N / i-Ga 1-y In y N / p
It is a diagram showing a sectional structure of -Ga 1-x In x N structure light emitting element.

【図７】ｎ−Ｇａ1-xＩｎxＮ／ｐ−Ｇａ1-yＩｎyＮ／ｐ
−Ｇａ1-xＩｎxＮ構造発光素子の断面構造を示した図で
ある。FIG. 7 n-Ga 1-x In x N / p-Ga 1-y In y N / p
It is a diagram showing a sectional structure of -Ga 1-x In x N structure light emitting element.

【図８】ｎ−Ｇａ1-xＡｌxＮ／ｉ−Ｇａ1-yＡｌyＮ／ｐ
−Ｇａ1-xＡｌxＮ構造発光素子の断面構造を示した図で
ある。FIG. 8 n-Ga 1-x Al x N / i-Ga 1-y Al y N / p
FIG. 3 is a diagram showing a cross-sectional structure of a —Ga 1-x Al x N structure light emitting device.

【図９】ｎ−Ｇａ1-x-yＩｎxＡｌyＮ／ｉ−Ｇａ1-a-bＩ
ｎaＡｌbＮ／ｐ−Ｇａ1-x-yＩｎxＡｌyＮ構造発光素子
の断面構造を示した図である。[9] n-Ga 1-xy In x Al y N / i-Ga 1-ab I
is a diagram showing a n a Al b N / p- Ga 1-xy In x Al y N structural cross-sectional structure of the light-emitting element.

【図１０】ｎ−ＧａＮ／ｐ−ＧａＮ／ｎ−Ｇａ1-xＩｎx
Ｎ／ｐ−Ｇａ1-xＩｎxＮ構造発光素子の断面構造を示し
た図である。FIG. 10 n-GaN / p-GaN / n-Ga 1-x In x
It is a diagram showing a sectional structure of N / p-Ga 1-x In x N structure light emitting element.

【図１１】ＧａＩｎＮ系組成傾斜構造／ｎ−Ｇａ1-xＩ
ｎxＮ／ｐ−Ｇａ1-xＩｎxＮ構造発光素子の断面構造を
示した図である。FIG. 11: GaInN-based composition gradient structure / n-Ga 1-x I
is a diagram showing the sectional structure of the n x N / p-Ga 1 -x In x N structure light emitting element.

【図１２】ｎ−Ｇａ1-xＩｎxＮ／量子井戸構造／ｐ−Ｇ
ａ1-xＩｎxＮ構造発光素子の断面構造を示した図であ
る。FIG. 12 n-Ga 1-x In x N / quantum well structure / p-G
It is a diagram showing a sectional structure of a 1-x In x N structure light emitting element.

【図１３】ＧａＮ−ＧａＩｎＮ歪超格子構造／ｎ−Ｇａ
1-xＩｎxＮ／ｐ−Ｇａ1-xＩｎxＮ構造発光素子の断面構
造を示した図である。FIG. 13: GaN-GaInN strained superlattice structure / n-Ga
Is a diagram showing the 1-x In x N / p -Ga 1-x In x N cross-sectional structure of the structure-emitting element.

【図１４】ｎ−Ｇａ1-xＩｎxＮ／ｐ−Ｇａ1-xＩｎxＮ／
ｎ−Ｇａ1-yＩｎyＮ／ｐ−Ｇａ1-yＩｎyＮ構造発光素子
の断面構造を示した図である。FIG. 14: n-Ga 1-x In x N / p-Ga 1-x In x N /
It is a diagram showing an n-Ga 1-y In y N / p-Ga 1-y In y N cross-sectional structure of the structure-emitting element.

【図１５】ネット状電極を形成した発光素子の平面図を
示す。FIG. 15 is a plan view of a light emitting device having a net-shaped electrode.

【図１６】クシ状電極を形成した発光素子の平面図を示
す。FIG. 16 is a plan view of a light emitting device having a comb-shaped electrode.

【図１７】ミアンダ状電極を形成した発光素子の平面図
を示す。FIG. 17 is a plan view of a light emitting device having a meandering electrode.

【図１８】ｎ+−ＧａＮ／ｎ−ＧａＮ／ｐ−ＧａＮ構造
からなる発光層と該発光層が形成されていない基板面に
金属層が形成された構造からなる発光素子の断面構造を
示した図である。FIG. 18 shows a cross-sectional structure of a light emitting device including a light emitting layer having an n + -GaN / n-GaN / p-GaN structure and a metal layer formed on a substrate surface on which the light emitting layer is not formed. It is a figure.

【符号の簡単な説明】[Simple explanation of symbols]

１ 真空容器 ２ 蒸発用ルツボ ３ 蒸発用ルツボ ４ 蒸発用ルツボ ５イ蒸発用ルツボ ５ロ蒸発用ルツボ ６ クラッキングガスセル ７ 基板加熱ホルダー ８ 基板 ９ 四重極質量分析器 １０ ＲＨＥＥＤ用電子銃 １１ ＲＨＥＥＤスクリーン １２ クライオパネル １３ シャッター １４ シャッター １５ シャッター １６イシャッター １６ロシャッター １７ バルブ １８ コールドトラップ １９ 油拡散ポンプ ２０ 油回転ポンプ ２１ 基板 ２２ ｎ−ＧａＮ系半導体層に形成する電極 ２３ ｐ−あるいはｉ−ＧａＮ系半導体層に形成する電
極 ２４ ｎ−ＧａＮ ２５ ｐ−ＧａＮ ２６ ｎ−Ｇａ1-xＩｎxＮ ２７ ｐ−Ｇａ1-xＩｎxＮ ２８ ｎ+−ＧａＮ ２９ ｉ−ＧａＮ ３０ ｉ−Ｇａ1-yＩｎyＮ ３１ ｐ−Ｇａ1-yＩｎyＮ ３２ ｎ−Ｇａ1-xＡｌxＮ ３３ ｉ−Ｇａ1-xＡｌxＮ ３４ ｐ−Ｇａ1-xＡｌxＮ ３５ ｎ−Ｇａ1-x-yＩｎxＡｌyＮ ３６ ｉ−Ｇａ1-x-yＩｎxＡｌyＮ ３７ ｐ−Ｇａ1-x-yＩｎxＡｌyＮ ３８ ＧａＩｎＮ系組成傾斜構造 ３９ ＧａＮ−ＧａＩｎＮ歪超格子構造 ４０ ｎ−Ｇａ1-yＩｎyＮ ４１ ｎ−ＧａＮ系半導体層に設けられた電極 ４２ ｎ−ＧａＮ系半導体層 ４３ ｉ−あるいはｐ−ＧａＮ系半導体層 ４４ ネット状電極 ４５ クシ状電極 ４６ ミアンダ状電極 ４７ 金属層DESCRIPTION OF SYMBOLS 1 vacuum container 2 evaporation crucible 3 evaporation crucible 4 evaporation crucible 5 b evaporation crucible 5 b evaporation crucible 6 cracking gas cell 7 substrate heating holder 8 substrate 9 quadrupole mass spectrometer 10 RHEED electron gun 11 RHEED screen 12 Cryopanel 13 Shutter 14 Shutter 15 Shutter 16 E-Shutter 16 Ro-Shutter 17 Valve 18 Cold trap 19 Oil diffusion pump 20 Oil rotary pump 21 Substrate 22 Electrode formed on n-GaN semiconductor layer 23 p- or i-GaN semiconductor layer 24 n-GaN 25 p-GaN 26 n-Ga 1-x In x N 27 p-Ga 1-x In x N 28 n + -GaN 29 i-GaN 30 i-Ga 1-y In y n 31 p-Ga 1-y In y n 32 n-Ga 1-x Al x n 33 -Ga 1-x Al x N 34 p-Ga 1-x Al x N 35 n-Ga 1-xy In x Al y N 36 i-Ga 1-xy In x Al y N 37 p-Ga 1-xy In x Al y N 38 GaInN-based composition gradient structure 39 GaN-GaInN strained superlattice structure 40 n-Ga 1-y In y N 41 n-GaN-based semiconductor layer electrode 42 n-GaN-based semiconductor layer 43 i- Alternatively, p-GaN-based semiconductor layer 44 net-like electrode 45 comb-like electrode 46 meandering electrode 47 metal layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 透明基板上に窒化ガリウム系化合物から
なるｎ型半導体層およびｐ型あるいはｉ型半導体層を組
み合わせてなる発光層を少なくとも一つ有し、該発光層
に電圧を印加するために半導体層の所望の部位に電極が
形成されている半導体発光素子構造において、ｐ型ある
いはｉ型半導体層を表面層とし、かつ該ｐ型あるいはｉ
型半導体層からなる表面層に電圧を均一に印加するため
のパターンを形成された電極が、該半導体表面層の表面
を、５０％を超えない範囲で覆い、その電極側から光を
取り出すことを特徴とする半導体発光装置。1. A transparent substrate having at least one light-emitting layer formed by combining an n-type semiconductor layer made of a gallium nitride-based compound and a p-type or i-type semiconductor layer, and applying a voltage to the light-emitting layer. In a semiconductor light emitting device structure in which an electrode is formed at a desired portion of a semiconductor layer, a p-type or i-type semiconductor layer is used as a surface layer, and the p-type or i-type semiconductor layer is used.
An electrode on which a pattern for uniformly applying a voltage is applied to the surface layer formed of the semiconductor layer covers the surface of the semiconductor surface layer within a range not exceeding 50%, and light is extracted from the electrode side. A characteristic semiconductor light emitting device. 【請求項２】 透明基板上の一方の基板面に少なくとも
一層の金属層を有し、かつその反対側の基板面上に窒化
ガリウム系化合物からなるｎ型半導体層およびｐ型ある
いはｉ型半導体層を組み合わせてなる発光層を少なくと
も一つ有し、該発光層に電圧を印加するために半導体層
の所望の部位に電極が形成されている半導体発光素子構
造において、ｐ型あるいはｉ型半導体層を表面層とし、
かつ該ｐ型あるいはｉ型半導体層からなる表面層に電圧
を均一に印加するためのパターンを形成された電極が、
該半導体表面層の表面を、５０％を超えない範囲で覆
い、その電極側から光を取り出すことを特徴とする半導
体発光装置。2. An n-type semiconductor layer and a p-type or i-type semiconductor layer which has at least one metal layer on one substrate surface of a transparent substrate and which is made of a gallium nitride-based compound on the opposite substrate surface. In a semiconductor light emitting device structure having at least one light emitting layer formed by combining the above, and an electrode is formed at a desired portion of the semiconductor layer for applying a voltage to the light emitting layer, a p-type or i-type semiconductor layer is provided. As the surface layer,
In addition, an electrode formed with a pattern for uniformly applying a voltage to the surface layer made of the p-type or i-type semiconductor layer is
A semiconductor light emitting device, characterized in that the surface of the semiconductor surface layer is covered within a range not exceeding 50%, and light is extracted from the electrode side thereof. 【請求項３】 窒化ガリウム系化合物のｐ型あるいはｉ
型半導体層からなる表面層に形成される電極のパターン
がネット状、クシ状あるいはミアンダ状であることを特
徴とする請求項１あるいは２記載の半導体発光装置。3. A p-type or i-type gallium nitride-based compound
3. The semiconductor light emitting device according to claim 1, wherein the pattern of the electrode formed on the surface layer formed of the type semiconductor layer is a net shape, a comb shape, or a meander shape.
JP13522092A 1992-05-27 1992-05-27 Semiconductor light-emitting device Withdrawn JPH05335622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13522092A JPH05335622A (en) 1992-05-27 1992-05-27 Semiconductor light-emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13522092A JPH05335622A (en) 1992-05-27 1992-05-27 Semiconductor light-emitting device

Publications (1)

Publication Number Publication Date
JPH05335622A true JPH05335622A (en) 1993-12-17

Family

ID=15146636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13522092A Withdrawn JPH05335622A (en) 1992-05-27 1992-05-27 Semiconductor light-emitting device

Country Status (1)

Country Link
JP (1) JPH05335622A (en)

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1041254A (en) * 1996-07-24 1998-02-13 Sony Corp Ohmic electrode and forming method thereof
JPH10275935A (en) * 1997-03-28 1998-10-13 Rohm Co Ltd Semiconductor light-emitting element
JPH11220173A (en) * 1994-09-22 1999-08-10 Nichia Chem Ind Ltd Gallium nitride compound semiconductor light emitting element
JP2000164930A (en) * 1998-11-20 2000-06-16 Agilent Technol Inc Electrode structure for light emitting device
WO2000070129A1 (en) * 1999-05-13 2000-11-23 Emf Ireland Limited Method and apparatus for epitaxially growing a material on a substrate
US6222204B1 (en) 1994-07-19 2001-04-24 Sharp Kabushiki Kaisha Electrode structure and method for fabricating the same
WO2001073858A1 (en) * 2000-03-31 2001-10-04 Toyoda Gosei Co., Ltd. Group-iii nitride compound semiconductor device
WO2003007390A1 (en) * 2001-07-12 2003-01-23 Nichia Corporation Semiconductor device
JP2003046127A (en) * 2001-05-23 2003-02-14 Sanyo Electric Co Ltd Nitride semiconductor light-emitting element
US6835958B2 (en) 2002-02-06 2004-12-28 Toyoda Gosei Co., Ltd. Light-emitting device
US6900465B2 (en) 1994-12-02 2005-05-31 Nichia Corporation Nitride semiconductor light-emitting device
JP2006501656A (en) * 2002-09-30 2006-01-12 オスラム　オプト　セミコンダクターズ　ゲゼルシャフト　ミット　ベシュレンクテル　ハフツング Radiation-emitting semiconductor component and method for manufacturing the semiconductor component
US7109529B2 (en) 1998-05-13 2006-09-19 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
JP2006253240A (en) * 2005-03-08 2006-09-21 Mitsubishi Cable Ind Ltd GaN LIGHT EMITTING DIODE AND LIGHT EMITTING DEVICE
JP2008300421A (en) * 2007-05-29 2008-12-11 Sumitomo Electric Ind Ltd Method of manufacturing iii-v nitride semiconductor and iii-v nitride semiconductor
JP2009200514A (en) * 2001-07-24 2009-09-03 Nichia Corp Semiconductor light-emitting device
US7592636B2 (en) 2002-09-30 2009-09-22 Osram Opto Semiconductors Gmbh Radiation-emitting semiconductor component and method for the production thereof
US7635875B2 (en) 2001-07-24 2009-12-22 Nichia Corporation Semiconductor light emitting device
US7683386B2 (en) 2003-08-19 2010-03-23 Nichia Corporation Semiconductor light emitting device with protrusions to improve external efficiency and crystal growth
US8067780B2 (en) 2006-09-05 2011-11-29 Epistar Corporation Light emitting device and the manufacture method thereof
JP2011254096A (en) * 2011-08-05 2011-12-15 Mitsubishi Chemicals Corp Gan-based light-emitting diode and light-emitting device
CN102479902A (en) * 2010-11-23 2012-05-30 晶元光电股份有限公司 Light emitting assembly
JP2013062322A (en) * 2011-09-12 2013-04-04 Sumitomo Electric Ind Ltd Nitride semiconductor light-emitting element manufacturing method
JP2013062321A (en) * 2011-09-12 2013-04-04 Sumitomo Electric Ind Ltd Nitride semiconductor light-emitting element manufacturing method

Cited By (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6222204B1 (en) 1994-07-19 2001-04-24 Sharp Kabushiki Kaisha Electrode structure and method for fabricating the same
US6429111B2 (en) 1994-07-19 2002-08-06 Sharp Kabushiki Kaisha Methods for fabricating an electrode structure
JPH11220173A (en) * 1994-09-22 1999-08-10 Nichia Chem Ind Ltd Gallium nitride compound semiconductor light emitting element
US6900465B2 (en) 1994-12-02 2005-05-31 Nichia Corporation Nitride semiconductor light-emitting device
JPH1041254A (en) * 1996-07-24 1998-02-13 Sony Corp Ohmic electrode and forming method thereof
JPH10275935A (en) * 1997-03-28 1998-10-13 Rohm Co Ltd Semiconductor light-emitting element
US7109529B2 (en) 1998-05-13 2006-09-19 Toyoda Gosei Co., Ltd. Light-emitting semiconductor device using group III nitride compound
JP2000164930A (en) * 1998-11-20 2000-06-16 Agilent Technol Inc Electrode structure for light emitting device
WO2000070129A1 (en) * 1999-05-13 2000-11-23 Emf Ireland Limited Method and apparatus for epitaxially growing a material on a substrate
WO2001073858A1 (en) * 2000-03-31 2001-10-04 Toyoda Gosei Co., Ltd. Group-iii nitride compound semiconductor device
US6777805B2 (en) 2000-03-31 2004-08-17 Toyoda Gosei Co., Ltd. Group-III nitride compound semiconductor device
US7042089B2 (en) 2000-03-31 2006-05-09 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor device
JP2003046127A (en) * 2001-05-23 2003-02-14 Sanyo Electric Co Ltd Nitride semiconductor light-emitting element
WO2003007390A1 (en) * 2001-07-12 2003-01-23 Nichia Corporation Semiconductor device
US6977395B2 (en) 2001-07-12 2005-12-20 Nichia Corporation Semiconductor device
US10593833B2 (en) 2001-07-24 2020-03-17 Nichia Corporation Semiconductor light emitting device
US9368681B2 (en) 2001-07-24 2016-06-14 Nichia Corporation Semiconductor light emitting device
US10396242B2 (en) 2001-07-24 2019-08-27 Nichia Corporation Semiconductor light emitting device
US9865773B2 (en) 2001-07-24 2018-01-09 Nichia Corporation Semiconductor light emitting device
JP2009200514A (en) * 2001-07-24 2009-09-03 Nichia Corp Semiconductor light-emitting device
US8227280B2 (en) 2001-07-24 2012-07-24 Nichia Corporation Semiconductor light emitting device
US7635875B2 (en) 2001-07-24 2009-12-22 Nichia Corporation Semiconductor light emitting device
US8148744B2 (en) 2001-07-24 2012-04-03 Nichia Corporation Semiconductor light emitting device
US7745245B2 (en) 2001-07-24 2010-06-29 Nichia Corporation Semiconductor light emitting device
US7804101B2 (en) 2001-07-24 2010-09-28 Nichia Corporation Semiconductor light-emitting device
US8344403B2 (en) 2001-07-24 2013-01-01 Nichia Corporation Semiconductor light emitting device
US8344402B2 (en) 2001-07-24 2013-01-01 Nichia Corporation Semiconductor light emitting device
US8299486B2 (en) 2001-07-24 2012-10-30 Nichia Corporation Semiconductor light emitting device
US6835958B2 (en) 2002-02-06 2004-12-28 Toyoda Gosei Co., Ltd. Light-emitting device
US7592636B2 (en) 2002-09-30 2009-09-22 Osram Opto Semiconductors Gmbh Radiation-emitting semiconductor component and method for the production thereof
JP4791731B2 (en) * 2002-09-30 2011-10-12 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング Radiation-emitting semiconductor component and method for manufacturing the semiconductor component
JP2006501656A (en) * 2002-09-30 2006-01-12 オスラム　オプト　セミコンダクターズ　ゲゼルシャフト　ミット　ベシュレンクテル　ハフツング Radiation-emitting semiconductor component and method for manufacturing the semiconductor component
US8119534B2 (en) 2003-08-19 2012-02-21 Nichia Corporation Semiconductor light emitting device with protrusions to improve external efficiency and crystal growth
US7683386B2 (en) 2003-08-19 2010-03-23 Nichia Corporation Semiconductor light emitting device with protrusions to improve external efficiency and crystal growth
JP2006253240A (en) * 2005-03-08 2006-09-21 Mitsubishi Cable Ind Ltd GaN LIGHT EMITTING DIODE AND LIGHT EMITTING DEVICE
US8067780B2 (en) 2006-09-05 2011-11-29 Epistar Corporation Light emitting device and the manufacture method thereof
US8664686B2 (en) 2006-09-05 2014-03-04 Epistar Corporation Light emitting device and the manufacture method thereof
JP2008300421A (en) * 2007-05-29 2008-12-11 Sumitomo Electric Ind Ltd Method of manufacturing iii-v nitride semiconductor and iii-v nitride semiconductor
CN102479902A (en) * 2010-11-23 2012-05-30 晶元光电股份有限公司 Light emitting assembly
JP2011254096A (en) * 2011-08-05 2011-12-15 Mitsubishi Chemicals Corp Gan-based light-emitting diode and light-emitting device
JP2013062322A (en) * 2011-09-12 2013-04-04 Sumitomo Electric Ind Ltd Nitride semiconductor light-emitting element manufacturing method
JP2013062321A (en) * 2011-09-12 2013-04-04 Sumitomo Electric Ind Ltd Nitride semiconductor light-emitting element manufacturing method

Similar Documents

Publication Publication Date Title
US5602418A (en) Nitride based semiconductor device and manufacture thereof
JPH05335622A (en) Semiconductor light-emitting device
US6258617B1 (en) Method of manufacturing blue light emitting element
US5237182A (en) Electroluminescent device of compound semiconductor with buffer layer
US20080135868A1 (en) Nitride Semiconductor Light Emitting Element and Method for Manufacturing the Same
US20080048172A1 (en) Gallium Nitride-Based Compound Semiconductor Light-Emitting Device
JPH05343741A (en) Gallium nitride series semiconductor element and manufacture thereof
JPH06152072A (en) Semiconductor laser
WO2008075679A1 (en) Method for manufacturing iii nitride compound semiconductor light emitting element, iii nitride compound semiconductor light emitting element and lamp
JPH06164055A (en) Quantum-well semiconductor laser
JP3441059B2 (en) Semiconductor device and manufacturing method thereof
KR100827993B1 (en) Gallium nitride-based semiconductor device
JP3247437B2 (en) Nitride-based semiconductor device and method of manufacturing the same
JP4865118B2 (en) Semiconductor device and method for manufacturing semiconductor light emitting device
JPH05291618A (en) Light emitting device
US20070102723A1 (en) Zinc-oxide-based light-emitting diode
JPH09266327A (en) Group iii nitride chemical compound semiconductor light emitting element
Lagerstedt et al. Properties of GaN tunneling MIS light‐emitting diodes
US20090020771A1 (en) III-Nitride Semiconductor Light Emitting Device And Method For Manufacturing The Same
JPH05190903A (en) Semiconductor light-emitting element and manufacture thereof
JP2001119065A (en) P-type nitride semiconductor and producing method thereof
JPH0555631A (en) Thin semiconductor laminate film and its manufacture
JP3065780B2 (en) Gallium nitride based light emitting device and manufacturing method
JP2008106316A (en) Method for manufacturing group iii nitride compound semiconductor light-emitting device, group iii nitride compound semiconductor light-emitting device, and lamp
GB2250635A (en) Light emitting semiconductor device

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990803