JPH05343741A - Gallium nitride series semiconductor element and manufacture thereof - Google Patents

Gallium nitride series semiconductor element and manufacture thereof

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Publication number
JPH05343741A
JPH05343741A JP33525591A JP33525591A JPH05343741A JP H05343741 A JPH05343741 A JP H05343741A JP 33525591 A JP33525591 A JP 33525591A JP 33525591 A JP33525591 A JP 33525591A JP H05343741 A JPH05343741 A JP H05343741A
Authority
JP
Japan
Prior art keywords
substrate
layer
intermediate layer
single crystal
gallium nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33525591A
Other languages
Japanese (ja)
Other versions
JP3352712B2 (en
Inventor
Tetsuya Takeuchi
哲也 竹内
Hiroshi Amano
浩 天野
Isamu Akasaki
勇 赤崎
Atsushi Watanabe
温 渡辺
Katsuhide Manabe
勝英 真部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Toyoda Gosei Co Ltd
Original Assignee
Toyoda Gosei Co Ltd
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Gosei Co Ltd, Pioneer Electronic Corp filed Critical Toyoda Gosei Co Ltd
Priority to JP33525591A priority Critical patent/JP3352712B2/en
Priority to US07/971,208 priority patent/US5239188A/en
Priority to EP92310314A priority patent/EP0551721B1/en
Priority to DE69217903T priority patent/DE69217903T2/en
Priority to US08/046,960 priority patent/US5389571A/en
Publication of JPH05343741A publication Critical patent/JPH05343741A/en
Application granted granted Critical
Publication of JP3352712B2 publication Critical patent/JP3352712B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/065—Gp III-V generic compounds-processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/113—Nitrides of boron or aluminum or gallium
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Abstract

PURPOSE:To operate even by injecting a large current and to miniaturize and particularly easily form electrodes by forming a single crystal of (Ga1-xAlx)1-yInyN having high quality of crystal in which a crystal defect is suppressed and excellent flatness. CONSTITUTION:A method for manufacturing a gallium nitride series semiconductor element comprises the steps of holding a silicon single crystalline substrate 1 at 400-1300 deg.C, holding the substrate in an atmosphere containing organic metal compound including at least aluminum and compound including nitrogen, forming an intermediate layer 2 of a thin film containing at least aluminum and nitrogen partly or entirely on a surface of the substrate, and then forming at least one or multi-layer (Ga1-xAlx)1-yInyN single crystalline layer 3 on the intermediate layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ワイドギャップ半導体
として産業界より注目されている（Ｇａ1-xＡｌx）1-y
ＩｎyＮの単結晶からなる窒化ガリウム（ＧａＮ）系半
導体素子及びその作製方法に関し、特に、シリコン（Ｓ
ｉ）を基板として、その上に、特に波長にして２００〜
７００ｎｍ帯の発光及び受光素子用材料として期待され
ている（Ｇａ1-xＡｌx）1-yＩｎyＮの高品質単結晶を作
製する方法に関する。BACKGROUND OF THE INVENTION The present invention has attracted attention from the industrial world as a wide-gap semiconductor (Ga 1-x Al x ) 1-y
TECHNICAL FIELD The present invention relates to a gallium nitride (GaN) -based semiconductor device made of an In y N single crystal and a method for manufacturing the same, and particularly to silicon (S)
i) as a substrate, on which, in particular, a wavelength of 200 to
The present invention relates to a method for producing a high-quality single crystal of (Ga 1-x Al x ) 1-y In y N, which is expected as a material for light-emitting and light-receiving elements in the 700 nm band.

【０００２】[0002]

【従来の技術及び問題点】（Ｇａ1-xＡｌx）1-yＩｎyＮ
（０≦ｘ≦１，０≦ｙ≦１，但し、ｘ＝１かつｙ＝０の
場合は除く）の結晶は、室温でのエネルギーバンドギャ
ップに対応する光の波長が２００〜７００ｎｍ帯にある
直接遷移型半導体であり、特に可視短波長及び紫外光領
域の発光及び受光素子用材料として期待されている。2. Description of the Related Art (Ga 1-x Al x ) 1-y In y N
The crystal of (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, except for x = 1 and y = 0) has a light wavelength corresponding to the energy band gap at room temperature in the 200 to 700 nm band. It is a direct transition type semiconductor, and is particularly expected as a material for light emitting and light receiving elements in the visible short wavelength and ultraviolet light regions.

【０００３】（Ｇａ1-xＡｌx）1-yＩｎyＮ結晶は成長温
度付近で構成元素である窒素（Ｎ）の平衡蒸気圧が極め
て高いため、そのバルク結晶の作製は容易でない。従っ
て、現在単結晶作製は異種結晶を基板として用いたヘテ
ロエピタキシャル成長により行っている。（Ｇａ1-xＡ
ｌx）1-yＩｎyＮ結晶作製用基板として必要な条件は、
（１）融点が高いこと（少なくとも 1,000℃以上）、
（２）化学的に安定であること、（３）結晶品質がすぐ
れていること、（４）格子定数差が小さいこと、（５）
入手が容易であること、（６）基板が大型であること、
が望ましい。また、電気的に動作する素子を作製する場
合、（７）電気的特性の制御が容易であること、特に低
抵抗であること、が望ましい。Since the (Ga 1-x Al x ) 1-y In y N crystal has an extremely high equilibrium vapor pressure of nitrogen (N), which is a constituent element, near the growth temperature, it is not easy to prepare its bulk crystal. Therefore, currently, single crystal production is performed by heteroepitaxial growth using a heterogeneous crystal as a substrate. (Ga 1-x A
l x ) 1-y In y N The conditions necessary for the crystal production substrate are:
(1) High melting point (at least 1,000 ℃),
(2) Chemically stable, (3) Excellent crystal quality, (4) Small difference in lattice constant, (5)
Easy to obtain, (6) Large board,
Is desirable. Further, in the case of manufacturing an element that operates electrically, it is desirable that (7) the electrical characteristics be easily controlled, particularly that the resistance be low.

【０００４】これらすべての条件を満足する結晶はな
い。現在最もよく用いられている基板は、（１）（２）
（３）（５）（６）を満足するサファイアから形成され
ている。サファイアと（Ｇａ1-xＡｌx）1-yＩｎyＮとの
間には格子定数差が１１％以上あり、（４）の条件から
は望ましくないが、本発明者らは、（Ｇａ1-xＡｌx）1-
yＩｎyＮの結晶成長直前に、低温（〜６００℃）で薄膜
のＡｌＮ（〜５０ｎｍ）をサファイア基板上に堆積して
緩衝層とすることにより、高品質の（Ｇａ1-xＡｌx）
1-yＩｎyＮ結晶の作製が可能であることを見いだしてい
る（特願昭６０−256806号）。この技術を用いて高性能
青色、紫外光ＬＥＤの作製にも成功している。しかしな
がら、サファイアは絶縁体であり、かつ堅固であるため
窒化ガリウム系半導体素子形成、特にその電極形成が容
易でないという問題点があり、大電流注入により動作す
る半導体素子には不向きであった。No crystal satisfies all these conditions. The most popular substrates at present are (1) and (2)
It is formed of sapphire satisfying (3), (5) and (6). The lattice constant difference between sapphire and (Ga 1-x Al x ) 1-y In y N is 11% or more, which is not desirable from the condition of (4), but the present inventors have (Ga 1 -x Al x ) 1-
crystal growth immediately before the y an In y N, low temperature (to 600 ° C.) with a thin film of AlN by a deposited (up to 50 nm) on a sapphire substrate by a buffer layer, high-quality (Ga 1-x Al x)
It has found that the production of 1-y In y N crystal can be (Japanese Patent Application No. Sho 60-256806). Using this technology, we have succeeded in producing high-performance blue and ultraviolet LEDs. However, since sapphire is an insulator and is solid, it has a problem that it is not easy to form a gallium nitride-based semiconductor device, particularly an electrode thereof, and is not suitable for a semiconductor device that operates by high current injection.

【０００５】この問題点を解決する基板材料の候補の一
つにシリコン（Ｓｉ）がある。Ｓｉでは容易に低抵抗高
融点基板が得られ、しかも大型の完全に近い結晶を容易
に得ることが出来、Ｓｉ基板は安価高結晶品質でかつ大
面積化及び微細加工も容易である。すなわち、（１）
（２）（３）（５）（６）（７）の条件を満足する。Ｓ
ｉ基板上の（Ｇａ1-xＡｌx）1-yＩｎyＮ結晶作製におけ
る最も大きな問題点は、例えばＧａＮとＳｉとの間にお
いて１７％程度という大きな格子定数差であり、この格
子定数差に基づく結晶欠陥の発生を抑制する技術の確立
が望まれていた。Silicon (Si) is one of the candidates for the substrate material to solve this problem. With Si, a low-resistance high-melting-point substrate can be easily obtained, and a large, almost perfect crystal can be easily obtained. The Si substrate is inexpensive, has high crystal quality, and can easily have a large area and fine processing. That is, (1)
The conditions (2), (3), (5), (6) and (7) are satisfied. S
The biggest problem in producing (Ga 1-x Al x ) 1-y In y N crystal on the i substrate is a large lattice constant difference of, for example, about 17% between GaN and Si. It has been desired to establish a technique for suppressing the generation of crystal defects based on

【０００６】[0006]

【発明の目的】本発明の目的は、可視短波長及び紫外光
発光及び受光素子用材料として期待される（Ｇａ1-xＡ
ｌx）1-yＩｎyＮ結晶を、安価、高結晶品質で大面積
化、及び低抵抗化が容易なＳｉ基板上に形成することの
出来る窒化ガリウム系半導体素子及びその製造方法を提
供することにある。OBJECTS OF THE INVENTION The object of the present invention is expected as a material for visible short wavelength and ultraviolet light emission and light receiving elements (Ga 1-x A
Provided is a gallium nitride-based semiconductor device capable of forming an l x ) 1-y In y N crystal on a Si substrate that is inexpensive, has high crystal quality, can easily have a large area, and can have a low resistance, and a method for manufacturing the same. Especially.

【０００７】[0007]

【問題点を解決するための手段】本発明は、（Ｇａ1-x
Ａｌx）1-yＩｎyＮ単結晶をＳｉ基板に作製する場合に
おいて、（Ｇａ1-xＡｌx）1-yＩｎyＮ単結晶の成長前
に、少なくともＡｌを含む有機金属化合物、及び窒素化
合物の両方を成長炉内に導入して、少なくともＡｌ及び
Ｎを含む化合物、例えばＡｌＮ薄層をＳｉ基板表面の一
部分ないし全体に形成した後、次にＡｌを含む有機金属
化合物の供給のみを一旦止め、必要とする混晶組成に見
合った分のＡｌを含む有機金属化合物、Ｇａを含む有機
金属化合物、及びＩｎを含む有機金属化合物を引続き供
給することにより、Ａｌ及びＮを含む化合物の薄層、即
ち中間層上に（Ｇａ1-xＡｌx）1-yＩｎyＮ結晶（０≦ｘ
≦１，０≦ｙ≦１，但し、ｘ＝１かつｙ＝０の場合は除
く）を作製する工程を含む製造方法によって、窒化ガリ
ウム系半導体素子を製造することを特徴とする。The present invention provides (Ga 1-x
In the case of producing an Al x ) 1-y In y N single crystal on a Si substrate, an organometallic compound containing at least Al before the growth of the (Ga 1-x Al x ) 1-y In y N single crystal, and After introducing both of the nitrogen compounds into the growth furnace to form a compound containing at least Al and N, for example, a thin layer of AlN on a part or the whole of the surface of the Si substrate, then only supplying the organometallic compound containing Al. Once stopped, the organic metal compound containing Al, the organic metal compound containing Ga, and the organic metal compound containing In corresponding to the required mixed crystal composition are continuously supplied to reduce the thickness of the compound containing Al and N. (Ga 1-x Al x ) 1-y In y N crystal (0 ≦ x
≤1, 0 ≤ y ≤ 1, except where x = 1 and y = 0), and a gallium nitride based semiconductor device is manufactured by a manufacturing method including a step of manufacturing.

【０００８】本発明の実施例では、Ａｌを含む有機金属
化合物、及び窒素化合物を成長炉内に導入して、少なく
ともＡｌ及びＮを含む化合物、例えばＡｌＮ（以下、Ａ
ｌＮと記す）を形成する場合、Ｓｉ基板の温度は400〜1
300℃の範囲内であることが好ましい。なお、本発明
は、上記（Ｇａ1-xＡｌx）1-yＩｎyＮ層におけるＡｌＮ
モル分率が０及び１を含み０から１の範囲内で、ＩｎＮ
モル分率ｙは０及び１を含み０から１の範囲内（ただ
し、ｘ＝１かつｙ＝０の場合は除く）で有効である。In an embodiment of the present invention, an organometallic compound containing Al and a nitrogen compound are introduced into a growth furnace to produce a compound containing at least Al and N, such as AlN (hereinafter referred to as AN).
1N), the temperature of the Si substrate is 400 to 1
It is preferably in the range of 300 ° C. In the present invention, the AlN in the (Ga 1-x Al x ) 1-y In y N layer is used.
When the mole fraction is within the range of 0 to 1 including 0 and 1, InN
The mole fraction y is effective within the range of 0 to 1 inclusive of 0 and 1 (except when x = 1 and y = 0).

【０００９】[0009]

【発明の作用】本発明の発明者らは、電気的特性の制御
が容易であり結晶学的に優れた特性を有しかつ安価であ
るＳｉ基板上に、気相成長法、特に原料として有機金属
化合物を用いた有機金属化合物気相成長法により、高品
質（Ｇａ1-xＡｌx）1-yＩｎyＮ単結晶を得るべくＳｉ基
板表面処理方法を種々検討した結果、上記発明を完成し
た。INDUSTRIAL APPLICABILITY The inventors of the present invention have conducted a vapor phase growth method, particularly an organic material as a raw material, on a Si substrate which has easy control of electrical characteristics, excellent crystallographic characteristics and is inexpensive. As a result of various investigations on the surface treatment method of the Si substrate to obtain a high-quality (Ga 1-x Al x ) 1-y In y N single crystal by the metal organic compound vapor phase epitaxy method, the above-mentioned invention was completed. did.

【００１０】Ｓｉ基板上への（Ｇａ1-xＡｌx）1-yＩｎy
Ｎ層の成長における最も大きな問題点は、例えばＧａＮ
とＳｉを比較した場合、１７％ものきわめて大きな格子
定数差が存在することであった。実際、ＧａＮを直接Ｓ
ｉ基板上に成長させても、多結晶化するか、或は単結晶
であっても六角柱状の島状に成長し、平坦性のよい高品
質単結晶の作製は困難であった（例えば、T. L. Chu, J
ournal of Electrochemical Society, Solid State Sci
ence, 第118巻，1971年,1200頁、あるいはYasuo Morimo
to, Kosuke Uchiho and Shintaro Ushio, Journal of E
lectrochemicalSociety,第120巻,1973年，1783頁など
に、ＧａＮをＳｉ基板上に直接成長させた場合の報告が
あり、実際、本発明者もいろいろな検討を行ったが、直
接高品質結晶をＳｉ基板上に成長させるのは困難であっ
た）。そこで、本発明者らは、なんらかの中間層が必要
であると考え、種々の結晶を検討し、最初、３Ｃ−Ｓｉ
Ｃを候補とした。(Ga 1-x Al x ) 1-y In y on Si substrate
The biggest problem in the growth of the N layer is, for example, GaN.
When compared with Si, it was found that there was an extremely large lattice constant difference of 17%. In fact, GaN is directly converted to S
Even if grown on an i substrate, it is polycrystallized, or even if it is a single crystal, it grows in an island shape of a hexagonal column, and it is difficult to produce a high quality single crystal with good flatness (for example, TL Chu, J
ournal of Electrochemical Society, Solid State Sci
ence, Volume 118, 1971, 1200 pages, or Yasuo Morimo
to, Kosuke Uchiho and Shintaro Ushio, Journal of E
The lectrochemical Society, Volume 120, 1973, p. 1783, etc., has reported a case where GaN is directly grown on a Si substrate. In fact, the present inventor also conducted various studies. It was difficult to grow on a substrate). Therefore, the present inventors considered that some kind of intermediate layer is necessary, investigated various crystals, and first examined 3C-Si.
C was selected as a candidate.

【００１１】３Ｃ−ＳｉＣを中間層とした場合は既に、
高品質単結晶（Ｇａ1-xＡｌx）1-yＩｎyＮの成長が可能
であることを確認している（特願平2-418003号）。本発
明者らは更に、３Ｃ−ＳｉＣとほぼ同一の格子定数を持
つＡｌＮを中間層としても、同様の効果が期待できると
考え、検討を行い、上記発明に至った。表１を見ればわ
かるように３Ｃ−ＳｉＣとＡｌＮとは格子定数差が 0.9
4％と極めて小さい。When 3C-SiC is used as the intermediate layer,
It has been confirmed that a high quality single crystal (Ga 1-x Al x ) 1-y In y N can be grown (Japanese Patent Application No. 2-418003). The present inventors further considered that the same effect can be expected even when AlN having a lattice constant substantially the same as that of 3C-SiC is used as an intermediate layer, studied and made the above-mentioned invention. As can be seen from Table 1, the lattice constant difference between 3C-SiC and AlN is 0.9.
Very small at 4%.

【００１２】[0012]

【表１】 [Table 1]

【００１３】本発明の特徴は、あくまでＡｌＮを中間層
として用いることにあり、ＡｌＮを中間層として用いて
Ｓｉ基板上に（Ｇａ1-xＡｌx）1-yＩｎyＮ層を成長させ
ることにより、Ｓｉ基板上に直接成長させたものと比較
して、各段に品質が優れ、しかも平坦性の極めて優れた
（Ｇａ1-xＡｌx）1-yＩｎyＮの単結晶を得ることが出来
る。The feature of the present invention lies in the fact that AlN is used as the intermediate layer, and the growth of the (Ga 1-x Al x ) 1-y In y N layer on the Si substrate using AlN as the intermediate layer. To obtain a single crystal of (Ga 1-x Al x ) 1-y In y N which is superior in quality to each step and has extremely excellent flatness as compared with the case of directly growing on a Si substrate. Can be done.

【００１４】本発明により、（Ｇａ1-xＡｌx）1-yＩｎy
Ｎの単結晶を安価に得られるようになる。また、微細加
工が容易でかつ大電流の注入により動作できる窒化ガリ
ウム系半導体素子、特に半導体レーザダイオードを得る
ことが出来る。According to the present invention, (Ga 1-x Al x ) 1-y In y
A single crystal of N can be obtained at low cost. Further, it is possible to obtain a gallium nitride-based semiconductor element, particularly a semiconductor laser diode, which can be easily microfabricated and can be operated by injection of a large current.

【００１５】[0015]

【実施例】以下、本発明によるＳｉ基板上への（Ｇａ
1-xＡｌx）1-yＩｎyＮ（０≦ｘ≦１，０≦ｙ≦１、但
し、ｘ＝１かつｙ＝０の場合は除く）の単結晶の作製方
法の実施例を説明する。以下に説明する実施例は、本発
明を例示するに過ぎず、本発明を限定するものではな
い。Embodiments (Ga on a Si substrate according to the present invention will be described below.
Example of a method for producing a single crystal of 1-x Al x ) 1-y In y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, except for x = 1 and y = 0) To do. The examples described below are merely illustrative of the present invention and are not intended to limit the present invention.

【００１６】本実施例によれば、量産性及び膜厚制御性
に優れる有機金属化合物気相成長法を用いており、特に
発光素子の作製は容易である。図１に示すように、ウェ
ーハの低抵抗ｎ型Ｓｉ（111）面基板１上に、ＡｌＮ薄
膜の中間層２を形成の後、アンドープまたはＳｉドープ
ｎ型ＧａＮ層３を成長する。引続き、ＭｇドープＧａＮ
層４を選択的に成長したのち、成長炉よりウェーハを取
り出し、低加速電子線照射処理（特願平２−2614号）を
行い、ＭｇドープＧａＮ層４を部分的にｐ型化してｐ型
領域５とする。次に、ｎ型ＧａＮ層３及びｐ型ＧａＮ領
域５のそれぞれに金属電極６Ａ，６Ｂを蒸着し、それら
各々にリード線７Ａ，７Ｂを接続して発光ダイオードを
形成する。ｎ型ＧａＮ層３側を負、Ｍｇドープｐ型Ｇａ
Ｎ領域５側を正としてバイアスをかけることにより、室
温において電圧３．５Ｖ付近から青色及び紫外線発光を
確認できた。 （１）中間層作製プロセス ＡｌＮの中間層作製及び（Ｇａ1-xＡｌx）1-yＩｎyＮ
（０≦ｘ＜１、０≦ｙ≦１、但し、ｘ＝１かつｙ＝０の
場合は除く）の単結晶作製は、通常の横型化合物半導体
結晶成長装置を用いた。成長手順を以下に示す。まず結
晶成長用基板、即ち低抵抗Ｓｉ基板（実験では（１１
１）面を用いた）をメタノールなどの有機薬品による洗
浄の後、弗酸系エッチャントにより表面の酸化物を取り
除き、純水による洗浄の後、結晶成長部に設置する。成
長炉を真空排気後、水素を供給し、例えば1200℃程度
（400〜1300℃の範囲内）まで昇温する。本成長装置で
は成長炉内に石英を用いており、その軟化点は1300℃で
あるため、それ以上の温度での実験は困難であり、実験
を行っていない。According to this embodiment, the organic metal compound vapor phase growth method, which is excellent in mass productivity and film thickness controllability, is used, and in particular, a light emitting element can be easily manufactured. As shown in FIG. 1, after forming an intermediate layer 2 of an AlN thin film on a low-resistance n-type Si (111) plane substrate 1 of a wafer, an undoped or Si-doped n-type GaN layer 3 is grown. Subsequently, Mg-doped GaN
After the layer 4 is selectively grown, the wafer is taken out from the growth furnace and subjected to low-acceleration electron beam irradiation treatment (Japanese Patent Application No. 2-2614) to partially convert the Mg-doped GaN layer 4 into p-type and p-type. Area 5 is set. Next, metal electrodes 6A and 6B are vapor-deposited on each of the n-type GaN layer 3 and the p-type GaN region 5, and lead wires 7A and 7B are connected to each of them to form a light emitting diode. N-type GaN layer 3 side is negative, Mg-doped p-type Ga
By applying a bias with the N region 5 side being positive, blue and ultraviolet light emission could be confirmed at a room temperature from around a voltage of 3.5V. (1) Intermediate layer preparation process: AlN intermediate layer preparation and (Ga 1-x Al x ) 1-y In y N
(0 ≦ x <1, 0 ≦ y ≦ 1, except when x = 1 and y = 0) was prepared by using a normal lateral compound semiconductor crystal growth apparatus. The growth procedure is shown below. First, a substrate for crystal growth, that is, a low resistance Si substrate ((11
(1) surface is cleaned with an organic chemical such as methanol, the surface oxide is removed with a hydrofluoric acid-based etchant, and after cleaning with pure water, it is placed in the crystal growth part. After evacuation of the growth furnace, hydrogen is supplied and the temperature is raised to, for example, about 1200 ° C (within the range of 400 to 1300 ° C). In this growth apparatus, quartz is used in the growth furnace, and its softening point is 1300 ° C, so it is difficult to conduct experiments at temperatures above that, and no experiments have been conducted.

【００１７】この後、成長炉内に水素に加え、Ａｌを含
む有機金属化合物、例えばトリメチルアルミニウム（Tr
imethyl Aluminum:TMA）及び窒素化合物、例えばアンモ
ニア（Ammonia:NH3）を成長装置内に導入し、５ｎｍか
ら２００ｎｍ程度の膜厚を持つＡｌＮ薄膜をＳｉ基板上
に形成する。ＡｌＮ薄膜形成時の基板温度４００℃より
低い場合、原料ガスの分解が不十分になり、本発明の効
果は期待できなくなる。また装置の都合上、成長炉に石
英を用いているため、1300℃以上では実験できない。ま
たＡｌＮ緩衝層が２００ｎｍより厚くなると、そのＡｌ
Ｎ層上に成長する（Ｇａ1-xＡｌx）1-yＩｎyＮ層の平坦
性は悪化する。After that, in addition to hydrogen, an organometallic compound containing Al, for example, trimethylaluminum (Tr
(iMethyl Aluminum: TMA) and a nitrogen compound such as ammonia (Ammonia: NH 3 ) are introduced into the growth apparatus to form an AlN thin film having a thickness of about 5 nm to 200 nm on the Si substrate. When the substrate temperature at the time of forming the AlN thin film is lower than 400 ° C., the decomposition of the raw material gas becomes insufficient and the effect of the present invention cannot be expected. Also, because of the equipment's convenience, quartz is used in the growth furnace, so experiments cannot be performed above 1300 ° C. If the AlN buffer layer becomes thicker than 200 nm, the Al
The flatness of the (Ga 1-x Al x ) 1-y In y N layer grown on the N layer deteriorates.

【００１８】さらに、上記のＡｌＮ中間層を用いる方法
は、Ｓｉ基板上に高品質の例えばＧａＮ単結晶を作製す
るのに有効であるが、ＡｌＮ層は高抵抗であり、基板と
ＧａＮ層とは電気的に絶縁されてしまうため、基板を電
極替わりに利用することができない。この問題を解決す
るには多くの方法があるが、ここではそのうち、４つの
方法を示す。Further, the method using the above AlN intermediate layer is effective for producing a high quality GaN single crystal, for example, on a Si substrate, but the AlN layer has a high resistance and the substrate and the GaN layer are different from each other. Since it is electrically insulated, the substrate cannot be used in place of the electrode. There are many ways to solve this problem, of which four are shown here.

【００１９】（i） 選択多結晶析出技術の利用 図２の成長プロセスの概略に示すように、一部分ＳｉＯ
2などで覆ったＳｉ基板１上にＡｌＮ中間層２を形成し
（図２ａ）、一旦成長炉から取り出して、ＳｉＯ2を剥
離する。これにより、Ｓｉ基板の表面はＡｌＮ層で覆わ
れている部分とＳｉ基板の露出部分ができる（図２
ｂ）。この場合、ＡｌＮ層の部分とＳｉ基板の露出部分
は面積的に大体同程度にする。次にそれを基板として、
ＧａＮの成長を行う。ＧａＮはＡｌＮ中間層２上には単
結晶で成長し、Ｓｉ基板１上にはＧａＮ多結晶が析出す
る。Ｓｉ基板１上のＧａＮ多結晶は低抵抗ｎ型伝導性を
示し、アクセプタ不純物を添加しても高抵抗化しないた
め、Ｓｉ基板とＧａＮ単結晶とは、ＧａＮ多結晶を通し
て、電気的に接続される（図２ｃ）。図３に選択多結晶
析出技術により形成した発光素子の概略構造図を示し、
この発光素子は、順に積層されたＡｕ−Ｓｂ電極、Ｓｉ
基板、ＡｌＮ中間層、ｎ型ＧａＮ多結晶層で接続された
ｎ型ＧａＮ単結晶層、ｐ型ＧａＮ単結晶層及びＡｕ電極
からなる。(I) Utilization of Selective Polycrystal Deposition Technique As shown in the outline of the growth process in FIG.
An AlN intermediate layer 2 is formed on a Si substrate 1 covered with 2 or the like (FIG. 2a), taken out of the growth furnace, and SiO 2 is peeled off. As a result, the surface of the Si substrate has a portion covered with the AlN layer and an exposed portion of the Si substrate (see FIG. 2).
b). In this case, the area of the AlN layer and the exposed portion of the Si substrate are approximately the same in area. Then use it as a substrate,
GaN is grown. GaN grows as a single crystal on the AlN intermediate layer 2, and a GaN polycrystal is deposited on the Si substrate 1. Since the GaN polycrystal on the Si substrate 1 exhibits low resistance n-type conductivity and does not have high resistance even when an acceptor impurity is added, the Si substrate and the GaN single crystal are electrically connected through the GaN polycrystal. (Fig. 2c). Fig. 3 shows a schematic structural diagram of a light emitting device formed by the selective polycrystalline deposition technique.
This light emitting device has an Au--Sb electrode and a Si layer that are sequentially stacked.
It is composed of a substrate, an AlN intermediate layer, an n-type GaN single crystal layer connected by an n-type GaN polycrystal layer, a p-type GaN single crystal layer, and an Au electrode.

【００２０】（ii） 選択横方向技術の利用 図４の成長プロセスの概略に示すように、(1)の選択多
結晶析出技術と同様の手段を用いて（図４ａ，図４
ｂ）、Ｓｉ基板１表面にＡｌＮ中間層２の部分とＳｉ基
板の露出部分とを形成する。ここでは、ＡｌＮ中間層部
分を、Ｓｉ基板の露出部分より面積的にかなり大きくす
る。その上にＧａＮ単結晶を成長すると、最初はＡｌＮ
中間層部分にのみＧａＮ単結晶が成長する（図４ｃ）。
ＡｌＮ中間層上に成長したＧａＮ単結晶は横方向に成長
し、隣接するＡｌＮ中間層上から成長したＧａＮ層とつ
ながり、最終的にＳｉ基板全体で一つのＧａＮ単結晶が
作製される（図４ｄ）。Ｓｉ基板とＧａＮ単結晶とは横
方向に成長した部分で電気的に接続される。図５に選択
横方向技術により形成した発光素子の概略構造図を示
し、この発光素子は、順に積層されたＡｕ−Ｓｂ電極、
Ｓｉ基板、ＡｌＮ中間層、ｎ型ＧａＮ単結晶層、ｐ型Ｇ
ａＮ単結晶層及びＡｕ電極からなる。(Ii) Utilization of Selective Lateral Technique As shown in the outline of the growth process of FIG. 4, the same means as the selective polycrystalline deposition technique of (1) is used (FIGS. 4a and 4a).
b), a portion of the AlN intermediate layer 2 and an exposed portion of the Si substrate are formed on the surface of the Si substrate 1. Here, the AlN intermediate layer portion is made considerably larger in area than the exposed portion of the Si substrate. When a GaN single crystal is grown on top of it, AlN
A GaN single crystal grows only in the intermediate layer portion (FIG. 4c).
The GaN single crystal grown on the AlN intermediate layer grows laterally and is connected to the GaN layer grown on the adjacent AlN intermediate layer, and finally one GaN single crystal is produced on the entire Si substrate (FIG. 4d). ). The Si substrate and the GaN single crystal are electrically connected at the laterally grown portion. FIG. 5 is a schematic structural view of a light emitting device formed by the selective lateral direction technique. This light emitting device is composed of Au--Sb electrodes stacked in order,
Si substrate, AlN intermediate layer, n-type GaN single crystal layer, p-type G
It consists of an aN single crystal layer and an Au electrode.

【００２１】（iii） ＡｌxＧａ1-xＮ（ｘ≠１）中間
層の利用 図６の成長プロセスの概略に示すように、まず、Ｓｉ基
板１上にＡｌＮ中間層のかわりにＡｌxＧａ1-xＮ（ｘ≠
１）中間層２を一様に形成する（図６ａ）。ＡｌxＧａ
1-xＮは、ドナー不純物の添加により低抵抗化が可能で
あるため、Ｓｉ基板１と電気的に接続される。実際に
は、ＡｌxＧａ1-xＮ中でＳｉはドナーとして働き、ま
た、成長中にＳｉは基板からオートドープされることか
ら、故意に不純物を添加しなくても、ＡｌxＧａ1-xＮ中
間層２は低抵抗ｎ型になり、好都合である。混晶組成に
関してはｘが（０．１）以上が好ましく、これによりＡ
ｌxＧａ1 -xＮ中間層２は上記のＡｌＮ中間層と同程度の
効果を奏する。この中間層２上にＧａＮ単結晶が作製さ
れる（図６ｂ）。図７にＡｌＧａＮ中間層を形成した発
光素子の概略構造図を示し、この発光素子は、順に積層
されたＡｕ−Ｓｂ電極、Ｓｉ基板、ＡｌＧａＮ中間層、
ｎ型ＧａＮ単結晶層、ｐ型ＧａＮ単結晶層及びＡｕ電極
からなる。(Iii) Utilization of Al x Ga 1-x N (x ≠ 1) Intermediate Layer As shown in the outline of the growth process in FIG. 6, first, on the Si substrate 1, instead of the AlN Ga intermediate layer, Al x Ga is used. 1-x N (x ≠
1) Form the intermediate layer 2 uniformly (FIG. 6a). Al x Ga
Since 1-x N can be made low in resistance by adding a donor impurity, it is electrically connected to the Si substrate 1. In reality, Si acts as a donor in Al x Ga 1-x N, and Si is auto-doped from the substrate during growth, so that Al x Ga 1- The xN intermediate layer 2 has a low resistance n-type, which is convenient. With regard to the mixed crystal composition, x is preferably (0.1) or more, whereby A
The l x Ga 1 -x N intermediate layer 2 has the same effect as the above AlN intermediate layer. A GaN single crystal is produced on this intermediate layer 2 (FIG. 6b). FIG. 7 shows a schematic structural diagram of a light emitting device in which an AlGaN intermediate layer is formed. The light emitting device includes an Au—Sb electrode, a Si substrate, an AlGaN intermediate layer, which are sequentially stacked.
It is composed of an n-type GaN single crystal layer, a p-type GaN single crystal layer, and an Au electrode.

【００２２】（iv） 極薄膜ＡｌＮ中間層の利用 図８の成長プロセスの概略に示すように、まず、Ｓｉ基
板１上にＡｌＮ中間層２を極薄膜化すると（図８ａ）、
例えば低抵抗ｎ型Ｓｉ基板中の電子の波動関数とｎ型Ｇ
ａＮ中の電子の波動関数が重なるようになり、トンネル
電流が流れ、電気的に接続される。この効果を利用する
には、ＡｌＮ中間層２の層厚は、波動関数の広がりと同
程度、即ち厚くとも１０ｎｍ以下にする必要があり、し
かも中間層として効果があるためには少なくとも１ｎｍ
以上あることが好ましい。この方法では、極薄膜成長技
術を利用する。この中間層２上にＧａＮ単結晶が作製さ
れる（図８ｂ）。図９に極薄膜ＡｌＮ中間層を形成した
発光素子の概略構造図を示し、この発光素子は、順に積
層されたＡｕ−Ｓｂ電極、Ｓｉ基板、極薄膜ＡｌＮ中間
層、ｎ型ＧａＮ単結晶層、ｐ型ＧａＮ単結晶層及びＡｕ
電極からなる。(Iv) Utilization of Ultrathin AlN Intermediate Layer As shown in the outline of the growth process in FIG. 8, first, the AlN intermediate layer 2 is made extremely thin on the Si substrate 1 (FIG. 8a).
For example, the electron wave function and n-type G in a low-resistance n-type Si substrate
The wave functions of the electrons in the aN come to overlap each other, a tunnel current flows, and they are electrically connected. In order to utilize this effect, the layer thickness of the AlN intermediate layer 2 needs to be about the same as the spread of the wave function, that is, at least 10 nm or less, and to be effective as an intermediate layer, it is at least 1 nm.
It is preferable to have the above. This method utilizes ultrathin film growth technology. A GaN single crystal is produced on this intermediate layer 2 (FIG. 8b). FIG. 9 shows a schematic structural diagram of a light emitting device in which an ultrathin film AlN intermediate layer is formed. This light emitting device includes an Au—Sb electrode, a Si substrate, an ultrathin film AlN intermediate layer, an n-type GaN single crystal layer, which are sequentially stacked, p-type GaN single crystal layer and Au
It consists of electrodes.

【００２３】中間層作製プロセスは以上である。 （２）ｐｎ接合の形成 中間層作製プロセスの後はサファイア上に作製している
場合と同様、例えば基板温度を1040℃として、ガリウム
を含む有機金属化合物、例えばトリメチルガリウム（Tr
imethyl gallium:TMG）及びＮＨ3を供給してＧａＮ層の
成長を行う。混晶を成長させる場合には混晶組成に見合
うだけのＴＭＧ、ＴＭＡ及びトリメチルインジウム（Tr
imethyl Indium:TMI)を供給する。The intermediate layer manufacturing process is as described above. (2) Formation of pn junction After the intermediate layer manufacturing process, as in the case of manufacturing on sapphire, for example, the substrate temperature is set to 1040 ° C., and an organometallic compound containing gallium such as trimethylgallium (Tr
Immethyl gallium (TMG) and NH 3 are supplied to grow the GaN layer. When growing a mixed crystal, TMG, TMA and trimethylindium (Tr
imethyl Indium (TMI).

【００２４】（Ｇａ1-xＡｌx）1-yＩｎyＮ層が所望の成
長膜厚に達した後、ＴＭＧ、ＴＭＡ、ＴＭＩの供給を止
め降温し、基板温度が６００℃以下になったのちＮＨ3
の供給を止め、温度が室温程度に下がったとき成長装置
より取り出す。本発明は、（Ｇａ1-xＡｌx）1-yＩｎyＮ
混晶のうち、ほとんど全ての混晶組成において、中間層
上に成長させる場合、同様な効果が得られる。但し、Ａ
ｌＮ（ｘ＝１かつｙ＝０）を中間層の上に成長する場合
には、本発明の効果は期待できない。After the (Ga 1-x Al x ) 1-y In y N layer reached the desired growth film thickness, the supply of TMG, TMA, and TMI was stopped and the temperature was lowered to 600 ° C. or less. Later NH 3
Is stopped, and when the temperature drops to about room temperature, it is taken out from the growth apparatus. The present invention relates to (Ga 1-x Al x ) 1-y In y N
In almost all mixed crystal compositions among the mixed crystals, the same effect can be obtained when grown on the intermediate layer. However, A
When 1N (x = 1 and y = 0) is grown on the intermediate layer, the effect of the present invention cannot be expected.

【００２５】上記のように作製した（Ｇａ1-xＡｌx）
1-yＩｎyＮ結晶は故意に不純物を添加しなくてもｎ型伝
導性を示すため、そのまま発光素子のｎ型層に利用す
る。もちろん、上記（Ｇａ1-xＡｌx）1-yＩｎyＮ結晶作
製時に故意にドナーとして働く不純物を添加してもよ
い。次に、結晶表面の全体、または一部に、ｘ及びｙが
所望の値となるよう、原料ガスの流量を制御し、同時に
アクセプタとなる不純物、例えば亜鉛やマグネシウムな
どの原料となるガスを供給して、伝導性の異なる（Ｇａ
1-xＡｌx）1-yＩｎyＮ結晶の接合を形成する。成長を終
了し、成長炉内よりウェーハを取り出した後に、各々伝
導性の異なる層それぞれに電極を形成し、発光素子が作
製される。Produced as described above (Ga 1-x Al x ).
1-y In y N because crystals having n-type conductivity even without the addition of impurities intentionally, it uses the n-type layer of the light-emitting element. Of course, an impurity that acts as a donor may be intentionally added when the (Ga 1-x Al x ) 1-y In y N crystal is produced. Next, the flow rate of the raw material gas is controlled so that x and y have desired values, and at the same time, impurities serving as acceptors, for example, raw material gases such as zinc and magnesium are supplied to all or part of the crystal surface. And have different conductivity (Ga
1-x Al x ) 1-y In y N forming a crystal junction. After the growth is completed and the wafer is taken out from the growth furnace, electrodes are formed on the respective layers having different conductivities to manufacture a light emitting device.

【００２６】本発明により作製したＡｌＮ中間層上のＧ
ａＮ結晶の表面を顕微鏡を介し写真撮影したもの及び反
射電子線回折像を図１０（ａ）及び図１０（ｂ）にそれ
ぞれ示す。図１１（ａ）及び図１１（ｂ）に、比較例と
してＳｉ基板上に直接ＧａＮを作製した場合のＧａＮ結
晶の表面顕微鏡写真及び反射電子線回折像をそれぞれ示
す。図から明らかなように、本発明のようにＡｌＮ中間
層を用いて作製したＧａＮの表面は極めて平坦であり
（図１０（ａ））、また、反射電子回折像から、得られ
たＧａＮが単結晶であることがわかり、また菊池線や菊
池帯が観測されるなど結晶性が極めて良いことが分る
（（図１０（ｂ））。一方、比較例のＳｉ基板上に直接
成長させた場合は、島状にしか成長せず（図１１
（ａ））、また、反射電子線回折像も観測されないこと
から（（図１１（ｂ））、結晶性はきわめて悪い。G on the AlN intermediate layer prepared according to the present invention
A photograph of the surface of the aN crystal taken through a microscope and a backscattered electron diffraction image are shown in FIGS. 10 (a) and 10 (b), respectively. 11 (a) and 11 (b) respectively show a surface micrograph and a backscattered electron diffraction image of a GaN crystal in the case where GaN was directly produced on a Si substrate as a comparative example. As is clear from the figure, the surface of GaN produced by using the AlN intermediate layer as in the present invention has an extremely flat surface (FIG. 10 (a)), and the obtained GaN shows that the GaN obtained is simple. It can be seen that it is a crystal, and the crystallinity is extremely good, such as the Kikuchi line and the Kikuchi zone being observed ((FIG. 10 (b)). On the other hand, when directly grown on the Si substrate of the comparative example. Grow only like islands (Fig. 11
(A)) Moreover, since the backscattered electron diffraction image is not observed ((FIG. 11 (b))), the crystallinity is extremely poor.

【００２７】単結晶Ｘ線回折評価装置により銅のＫα線
を入射Ｘ線として、それぞれの膜を評価すると、本発明
により作製したＧａＮ層からは、Ｘ線回折強度は強く、
また、Ｋα1線とＫα2線も明瞭に分離されるなど、サフ
ァイア上に成長したものと遜色ない結晶性を有している
ことが分った。一方、比較例のＳｉ基板上に直接成長し
た膜からはＸ線回折は認められず、結晶性は悪いことが
結論づけられた。When the respective films were evaluated by the single crystal X-ray diffraction evaluation apparatus using the copper Kα rays as the incident X-rays, the X-ray diffraction intensity was strong from the GaN layer produced according to the present invention.
Further, it was found that the Kα 1 ray and the Kα 2 ray were clearly separated and had crystallinity comparable to that grown on sapphire. On the other hand, no X-ray diffraction was observed from the film directly grown on the Si substrate of the comparative example, and it was concluded that the crystallinity was poor.

【００２８】本発明は、安価なＳｉを基板として用いて
おり、今後、特に可視短波長発光素子及び近紫外光発光
素子の実用化にとって必須の技術である。The present invention uses inexpensive Si as a substrate and is an essential technology for practical use of visible short wavelength light emitting elements and near-ultraviolet light emitting elements in the future.

【００２９】[0029]

【発明の効果】以上のように、本発明によれば、窒化ガ
リウム系半導体素子において、シリコン基板と、シリコ
ン基板上に形成された少なくともアルミニウム及び窒素
を含む化合物からなる中間層と、中間層上に形成された
（Ｇａ1-xＡｌx）1-yＩｎyＮ（０≦ｘ≦１，０≦ｙ≦
１，但しｘ＝１かつｙ＝０の場合は除く）の結晶層とか
らなる構造を有しているので、大電流注入によっても動
作できかつ微細加工特に電極形成が容易にできる窒化ガ
リウム系半導体素子を得ることが出来る。As described above, according to the present invention, in the gallium nitride based semiconductor device, the silicon substrate, the intermediate layer formed on the silicon substrate and containing the compound containing at least aluminum and nitrogen, and the intermediate layer are formed. (Ga 1-x Al x ) 1-y In y N (0 ≦ x ≦ 1, 0 ≦ y ≦
1, but x = 1 and y = 0) is excluded), a gallium nitride-based semiconductor that can be operated by a large current injection and that can be easily microfabricated, especially an electrode is formed. A device can be obtained.

【００３０】また、本発明の窒化ガリウム系半導体素子
製造方法によれば、シリコンの単結晶基板を温度400〜
1300℃に保持し、少なくともアルミニウムを含む有機金
属化合物及び窒素を含む化合物が存在する雰囲気内に単
結晶基板を保持して少なくともアルミニウム及び窒素を
含む薄膜の中間層を単結晶基板の表面の一部分又は全体
に形成し、しかる後、中間層の上に（Ｇａ1-xＡｌx）
1-yＩｎyＮの単結晶層を少なくとも一層又は多層形成す
るので、得られた単結晶層の結晶欠陥の発生を抑制した
高結晶品質で平坦性の極めて優れた（Ｇａ1-xＡｌx）
1-yＩｎyＮの単結晶を有する窒化ガリウム系半導体素子
を得ることが出来る。Further, according to the method for producing a gallium nitride-based semiconductor device of the present invention, a silicon single crystal substrate is heated at a temperature of 400-400.
Hold the temperature at 1300 ° C., hold the single crystal substrate in an atmosphere in which an organometallic compound containing at least aluminum and a compound containing nitrogen are present, and form an intermediate layer of a thin film containing at least aluminum and nitrogen at a part of the surface of the single crystal substrate or Formed on the whole surface, and then on the intermediate layer (Ga 1-x Al x ).
Since at least one 1-y In y N single crystal layer is formed, a single crystal layer having high crystal quality and extremely excellent flatness (Ga 1-x Al x )
1-y In y gallium nitride-based semiconductor device having a single crystal of N can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明による窒化ガリウム系半導体素子である
Ｓｉ基板上の（Ｇａ1-xＡｌx） 1-yＩｎyＮ（０≦ｘ≦
１，０≦ｙ≦１、但し、ｘ＝１かつｙ＝０の場合は除
く）からなる発光ダイオードの概略構成断面図である。FIG. 1 is a gallium nitride based semiconductor device according to the present invention.
(Ga on Si substrate1-xAlx) 1-yInyN (0 ≦ x ≦
1,0 ≦ y ≦ 1, except when x = 1 and y = 0
FIG. 3 is a schematic cross-sectional view of a light emitting diode including

【図２】本発明による実施例の窒化ガリウム系半導体素
子製造方法におけるＳｉ基板上の各層を示す概略断面図
である。FIG. 2 is a schematic cross-sectional view showing each layer on a Si substrate in a method for manufacturing a gallium nitride-based semiconductor device according to an example of the present invention.

【図３】本発明による実施例の窒化ガリウム系半導体素
子である発光ダイオードを示すの概略構成断面図であ
る。FIG. 3 is a schematic structural cross-sectional view showing a light emitting diode which is a gallium nitride based semiconductor device according to an embodiment of the present invention.

【図４】本発明による他の実施例の窒化ガリウム系半導
体素子製造方法におけるＳｉ基板上の各層を示す概略断
面図である。FIG. 4 is a schematic cross-sectional view showing each layer on a Si substrate in a gallium nitride-based semiconductor device manufacturing method according to another embodiment of the present invention.

【図５】本発明による他の実施例の窒化ガリウム系半導
体素子である発光ダイオードを示す概略構成断面図であ
る。FIG. 5 is a schematic cross-sectional view showing a light emitting diode which is a gallium nitride based semiconductor device according to another embodiment of the present invention.

【図６】本発明による他の実施例の窒化ガリウム系半導
体素子製造方法におけるＳｉ基板上の各層を示す概略断
面図である。FIG. 6 is a schematic cross-sectional view showing each layer on a Si substrate in a gallium nitride based semiconductor device manufacturing method according to another embodiment of the present invention.

【図７】本発明による他の実施例の窒化ガリウム系半導
体素子である発光ダイオードを示す概略構成断面図であ
る。FIG. 7 is a schematic cross-sectional view showing a light emitting diode which is a gallium nitride based semiconductor device according to another embodiment of the present invention.

【図８】本発明による他の実施例の窒化ガリウム系半導
体素子製造方法におけるＳｉ基板上の各層を示す概略断
面図である。FIG. 8 is a schematic cross-sectional view showing each layer on a Si substrate in a method of manufacturing a gallium nitride based semiconductor device according to another embodiment of the present invention.

【図９】本発明による他の実施例の窒化ガリウム系半導
体素子である発光ダイオードを示す概略構成断面図であ
る。FIG. 9 is a schematic cross-sectional view showing a light emitting diode which is a gallium nitride based semiconductor device according to another embodiment of the present invention.

【図１０】本発明による窒化ガリウム系半導体素子製造
方法により作製したＧａＮの表面の様子を示す顕微鏡写
真に基づく拡大平面図（ａ）及び反射電子線回析線像を
示す図（ｂ）である。FIG. 10 is an enlarged plan view (a) based on a micrograph showing a state of the surface of GaN produced by the method for producing a gallium nitride-based semiconductor device according to the present invention, and a diagram (b) showing a reflected electron beam diffraction line image. ..

【図１１】比較例のＳｉ基板上に直接ＧａＮ成長させた
場合のＧａＮの表面の様子を示す顕微鏡写真に基づく拡
大平面図（ａ）、及び反射電子線回析線像を示す図
（ｂ）である。FIG. 11 is an enlarged plan view (a) based on a micrograph showing a state of the surface of GaN when GaN is directly grown on a Si substrate of a comparative example, and a view (b) showing a backscattered electron diffraction image. Is.

【主要部分の符号の説明】[Explanation of symbols for main parts]

１ ｎ型Ｓｉ（111)面基板 ２ ＡｌＮ中間層 ３ アンドープまたはＳｉドープｎ型（Ｇａ1-xＡｌx）
1-yＩｎyＮ単結晶層 ４ Ｍｇドープ高抵抗（Ｇａ1-xＡｌx）1-xＩｎyＮ単結
晶層 ５ 低加速電子照射処理されたＭｇドープｐ型（Ｇａ
1-xＡｌx）1-yＩｎyＮ単結晶 ６Ａ，６Ｂ 金属電極 ７Ａ，７Ｂ リード線1 n-type Si (111) plane substrate 2 AlN intermediate layer 3 undoped or Si-doped n-type (Ga 1-x Al x )
1-y In y N single crystal layer 4 Mg-doped high resistance (Ga 1-x Al x ) 1-x In y N single-crystal layer 5 Mg-doped p-type (Ga
1-x Al x ) 1-y In y N single crystal 6A, 6B metal electrode 7A, 7B lead wire

───────────────────────────────────────────────────── フロントページの続き (71)出願人 000241463 豊田合成株式会社 愛知県西春日井郡春日町大字落合字長畑１ 番地 (72)発明者 竹内 哲也 愛知県名古屋市昭和区伊勝町２丁目96番地 ラフォーレ山の手Ｂ−205 (72)発明者 天野 浩 愛知県名古屋市名東区神丘町２丁目21虹ケ 丘東団地19棟103号室 (72)発明者 赤崎 勇 愛知県名古屋市西区浄心１丁目１番38− 805 (72)発明者 渡辺 温 埼玉県鶴ヶ島市富士見６丁目１番１号パイ オニア株式会社総合研究所内 (72)発明者 真部 勝英 愛知県西春日井郡春日町大字落合字長畑１ 番地 豊田合成株式会社内 ─────────────────────────────────────────────────── ─── Continuation of front page (71) Applicant 000241463 Toyoda Gosei Co., Ltd. 1 Ochiai, Ochiai, Kasuga-cho, Nishikasugai-gun, Aichi (72) Inventor Tetsuya Takeuchi 2-96, Ikatsu-cho, Showa-ku, Nagoya, Aichi Prefecture B-205 (72) Inventor Hiroshi Amano 2-21, Kamioka-cho, Meito-ku, Aichi Prefecture Nijigaoka-higashi housing complex, Room 103, Room 103 (72) Inventor, Isamu Akasaki 1-3-1, Jyoshin, Nishi-ku, Aichi Prefecture (72) Inventor Atsushi Watanabe 6-1, 1-1 Fujimi, Tsurugashima City, Saitama Pioneer Co., Ltd. Research Institute (72) Inventor Katsuhide Mabe 1 Ochihata, Nagahata, Ochiai, Kasuga-cho, Nishikasugai-gun, Aichi Prefecture Toyoda Gosei Co., Ltd.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 シリコン（Ｓｉ）基板と、前記シリコン
基板上に形成された少なくともアルミニウム（Ａｌ）及
び窒素（Ｎ）を含む化合物からなる中間層と、前記中間
層上に形成された（Ｇａ1-xＡｌx）1-yＩｎyＮ（０≦ｘ
≦１，０≦ｙ≦１，但しｘ＝１かつｙ＝０の場合は除
く）の結晶層とからなることを特徴とする窒化ガリウム
系半導体素子。1. A silicon (Si) substrate, an intermediate layer made of a compound containing at least aluminum (Al) and nitrogen (N) formed on the silicon substrate, and formed on the intermediate layer (Ga 1 -x Al x ) 1-y In y N (0 ≦ x
≤1, 0 ≤ y ≤ 1, except where x = 1 and y = 0), and a gallium nitride based semiconductor device. 【請求項２】 前記（Ｇａ1-xＡｌx）1-yＩｎyＮ（０≦
ｘ≦１，０≦ｙ≦１，但しｘ＝１かつｙ＝０の場合は除
く）の結晶層上に形成されかつ伝導性が該結晶層のそれ
とは異なりかつｐｎ接合を形成する少なくとも１つの
（Ｇａ1-xＡｌx）1-yＩｎyＮ（０≦ｘ≦１，０≦ｙ≦
１，但し、ｘ＝１かつｙ＝０の場合は除く）の他の結晶
層を有し、各々の結晶層においてｘ及びｙは等しい場
合、あるいは異なる場合を含むことを特徴とする請求項
１記載の窒化ガリウム系半導体素子。2. The (Ga 1-x Al x ) 1-y In y N (0 ≦
x ≦ 1, 0 ≦ y ≦ 1, except where x = 1 and y = 0) and has conductivity different from that of the crystal layer and forming a pn junction. (Ga 1-x Al x ) 1-y In y N (0 ≦ x ≦ 1, 0 ≦ y ≦
1, except that x = 1 and y = 0), and x and y are equal or different in each crystal layer. The gallium nitride-based semiconductor device described. 【請求項３】 シリコン（Ｓｉ）基板と、前記シリコン
基板上に形成された少なくともアルミニウム（Ａｌ）及
び窒素（Ｎ）を含む化合物からなる中間層と、前記中間
層上に形成された（Ｇａ1-xＡｌx）1-yＩｎyＮ（０≦ｘ
≦１，０≦ｙ≦１，但しｘ＝１かつｙ＝０の場合は除
く）の結晶層とからなる窒化ガリウム系半導体素子を製
造する方法であって、シリコンの単結晶基板を温度400
〜 1300℃に保持し、少なくともアルミニウムを含む有
機金属化合物及び窒素を含む化合物が存在する雰囲気内
に前記単結晶基板を保持して少なくともアルミニウム及
び窒素を含む薄膜の中間層を前記単結晶基板の表面の一
部分又は全体に形成し、しかる後、前記中間層の上に
（Ｇａ1-xＡｌx）1-yＩｎyＮの単結晶層を少なくとも一
層又は多層形成することを特徴とする窒化ガリウム系半
導体素子の製造方法。3. A silicon (Si) substrate, an intermediate layer made of a compound containing at least aluminum (Al) and nitrogen (N) formed on the silicon substrate, and formed on the intermediate layer (Ga 1 -x Al x ) 1-y In y N (0 ≦ x
≤1, 0 ≤ y ≤ 1, except where x = 1 and y = 0), and a gallium nitride based semiconductor device having a temperature of 400
~ 1300 ℃, holding the single crystal substrate in an atmosphere containing an organometallic compound containing at least aluminum and a compound containing nitrogen, the intermediate layer of a thin film containing at least aluminum and nitrogen surface of the single crystal substrate portions or formed on the entire, thereafter, (Ga 1-x Al x ) on the intermediate layer 1-y in y gallium nitride, which comprises at least one layer or multi-layer forming a single crystal layer of N Manufacturing method of semiconductor device. 【請求項４】 前記（Ｇａ1-xＡｌx）1-yＩｎyＮの単結
晶層におけるＡｌＮモル分率ｘが０及び１を含み０から
１の範囲内で、ＩｎＮモル分率ｙが０及び１を含み０か
ら１の範囲内（但し、ｘ＝１かつｙ＝０の場合は除く）
であることを特徴とする請求項３記載の製造方法。4. The AlN mole fraction x in the single crystal layer of (Ga 1-x Al x ) 1-y In y N is in the range of 0 to 1 inclusive of 0 and 1, and the InN mole fraction y is Within 0 to 1 including 0 and 1 (except when x = 1 and y = 0)
The manufacturing method according to claim 3, wherein
JP33525591A 1991-12-18 1991-12-18 Gallium nitride based semiconductor device and method of manufacturing the same Expired - Lifetime JP3352712B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP33525591A JP3352712B2 (en) 1991-12-18 1991-12-18 Gallium nitride based semiconductor device and method of manufacturing the same
US07/971,208 US5239188A (en) 1991-12-18 1992-11-04 Gallium nitride base semiconductor device
EP92310314A EP0551721B1 (en) 1991-12-18 1992-11-12 Gallium nitride base semiconductor device and method of fabricating the same
DE69217903T DE69217903T2 (en) 1991-12-18 1992-11-12 Semiconductor device based on gallium nitride and method of manufacture
US08/046,960 US5389571A (en) 1991-12-18 1993-04-16 Method of fabricating a gallium nitride based semiconductor device with an aluminum and nitrogen containing intermediate layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33525591A JP3352712B2 (en) 1991-12-18 1991-12-18 Gallium nitride based semiconductor device and method of manufacturing the same

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Publication Number Publication Date
JPH05343741A true JPH05343741A (en) 1993-12-24
JP3352712B2 JP3352712B2 (en) 2002-12-03

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DE69217903D1 (en) 1997-04-10

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