JPH05335438A - Leadless chip carrier - Google Patents
Leadless chip carrierInfo
- Publication number
- JPH05335438A JPH05335438A JP14385392A JP14385392A JPH05335438A JP H05335438 A JPH05335438 A JP H05335438A JP 14385392 A JP14385392 A JP 14385392A JP 14385392 A JP14385392 A JP 14385392A JP H05335438 A JPH05335438 A JP H05335438A
- Authority
- JP
- Japan
- Prior art keywords
- chip carrier
- leadless chip
- external connection
- substrate
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はリードレスチップキャリ
アに関し、特に外部搭載基板への実装を容易にしたリー
ドレスチップキャリアに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a leadless chip carrier, and more particularly to a leadless chip carrier that can be easily mounted on an external mounting board.
【０００２】[0002]
【従来の技術】従来のリードレスチップキャリアは、図
３に示すように、基板１の底面には、端面スルーホール
４に形成された導体を介してＩＣチップに接続する外部
接続用電極２が形成されているのみで、外部搭載基板と
の位置合わせ用の認識マークは、特に設けていなかっ
た。2. Description of the Related Art In a conventional leadless chip carrier, as shown in FIG. 3, an external connection electrode 2 for connecting to an IC chip through a conductor formed in an end face through hole 4 is provided on a bottom surface of a substrate 1. It is only formed, and no recognition mark for alignment with the external mounting board is provided.
【０００３】したがって、自動搭載装置を使用してのリ
ードレスチップキャリアの外部搭載基板への自動搭載
は、リードレスチップキャリアの基板１の外形を利用し
た位置補正により外部搭載基板に対し位置合わせされ搭
載されていた。Therefore, when the leadless chip carrier is automatically mounted on the external mounting substrate by using the automatic mounting device, the leadless chip carrier is aligned with the external mounting substrate by the position correction using the outer shape of the substrate 1. It was installed.
【０００４】[0004]
【発明が解決しようとする課題】この従来のリードレス
チップキャリアは、その基板１の外形に対しては、±
０．１ｍｍ以下という高い位置精度で外部搭載基板上に
自動搭載することが出来る。しかし、リードレスチップ
キャリアの製造工程内の制約により、リードレスチップ
キャリアの基板１の外形と外部接続用電極２との相対位
置にずれが生じた場合、基板１の外形を利用して極めて
高位置精度に外部搭載基板上に搭載しても、外部接続用
電極２は外部搭載基板上の半田付ランドと、基板１の外
形と外部接続用電極２が相対的にずれることになる。そ
のため、搭載位置精度が±０．２〜０．３ｍｍ程度まで
低下することになっていた。この様な場合、リードレス
チップキャリアの外部接続用電極２の間隔と幅がこの搭
載位置精度に対し充分広くなければ、半田付の際電極間
のショートあるいは接続不良が生じるという問題点があ
った。This conventional leadless chip carrier has a ± 1
It can be automatically mounted on an external mounting board with a high positional accuracy of 0.1 mm or less. However, when the relative position between the external shape of the substrate 1 of the leadless chip carrier and the external connection electrode 2 is deviated due to the restriction in the manufacturing process of the leadless chip carrier, the external shape of the substrate 1 is used to make an extremely high height. Even if the external connection electrode 2 is mounted with high positional accuracy, the external connection electrode 2 is relatively displaced between the soldering land on the external mounting substrate and the external shape of the substrate 1 and the external connection electrode 2. Therefore, the mounting position accuracy has been reduced to about ± 0.2 to 0.3 mm. In such a case, unless the interval and width of the external connection electrodes 2 of the leadless chip carrier are sufficiently wide with respect to the mounting position accuracy, there is a problem that short-circuiting between electrodes or connection failure may occur during soldering. .
【０００５】近年、リードレスチップキャリアにおい
て、小型化，多ピン化が進み、ピンピッチは０．６５ｍ
ｍ〜０．５ｍｍと狭くなる傾向にあり、外部接続用電極
２の間隔，幅を基板１の外形と外部接続用電極２の相対
位置ずれに対し、充分広くすることは非常に困難になっ
ている。In recent years, leadless chip carriers have become smaller and have more pins, and the pin pitch is 0.65 m.
It tends to become narrower from m to 0.5 mm, and it becomes very difficult to make the interval and width of the external connection electrode 2 sufficiently wide with respect to the relative displacement between the outer shape of the substrate 1 and the external connection electrode 2. There is.
【０００６】本発明の目的は、外部搭載基板上の半田付
ランドと外部接続用電極との搭載位置精度が高く、半田
付の際に電極間ショートあるいは接続不良のないリード
レスチップキャリアを提供することにある。An object of the present invention is to provide a leadless chip carrier which has a high mounting position accuracy between a soldering land on an external mounting substrate and an external connection electrode and which does not cause a short circuit between electrodes or a connection failure during soldering. Especially.
【０００７】[0007]
【課題を解決するための手段】本発明のリードレスチッ
プキャリアは、電子機能素子と、ガラスエポキシとセラ
ミックスとを含む素材から成る基板と、該基板上に形成
された外部接続用電極と、外部搭載基板との位置合わせ
用の位置認識パターンとを備える。A leadless chip carrier according to the present invention includes a substrate made of a material containing an electronic functional element, glass epoxy and ceramics, an external connection electrode formed on the substrate, and an external connection. And a position recognition pattern for alignment with the mounting substrate.
【０００８】前記位置認識パターンが、少なくとも該位
置認識パターン形状を形成する材料および形成工程にお
いて、外部接続用電極の形状を形成する材料および成形
工程と同一であるか、又は、前記位置認識パターンが、
外部接続用電極形成後、外部接続用電極の位置を基準に
して位置決めされて形成される。The position recognition pattern is at least the same as the material and the forming process for forming the shape of the external connection electrode in the material and forming process for forming the position recognition pattern, or the position recognition pattern is ,
After the electrode for external connection is formed, the electrode for external connection is positioned and formed with reference to the position of the electrode for external connection.
【０００９】[0009]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１０】図１（ａ），（ｂ）は本発明の第１の実施
例の断面図及びその底面図である。1 (a) and 1 (b) are a sectional view and a bottom view of the first embodiment of the present invention.
【００１１】第１の実施例は、図１（ａ），（ｂ）に示
すように、まず、基板１の編集体である元基板にスルー
ホールおよびスルーホール導体を形成する。In the first embodiment, as shown in FIGS. 1 (a) and 1 (b), first, through holes and through hole conductors are formed in an original board which is an editing body of the board 1.
【００１２】次に、基板１の上面および下面に導体パタ
ーンを形成する。下面の導体パターンは、外部接続用電
極２および位置認識パターン３であり、これらは、導体
ペースト印刷法あるいは、あらかじめ、基板１上に成膜
された導体膜のエッチング法により一括に±０．１ｍｍ
以下の精度で形成される。Next, conductor patterns are formed on the upper and lower surfaces of the substrate 1. The conductor patterns on the lower surface are the external connection electrodes 2 and the position recognition patterns 3, which are collectively ± 0.1 mm by a conductor paste printing method or an etching method of a conductor film previously formed on the substrate 1.
It is formed with the following accuracy.
【００１３】次に、元基板をスルーホール部分で切断し
て端面スルーホール４を形成する。次に、枠５を基板１
に接着し、ＩＣチップ７を搭載してボンディングワイヤ
６でＩＣチップ７と基板１上の配線導体とを接続する。
最後に、封止樹脂８で封止して完成する。Next, the original substrate is cut at the through holes to form end face through holes 4. Next, the frame 5 is attached to the substrate 1.
Then, the IC chip 7 is mounted and the bonding wire 6 connects the IC chip 7 and the wiring conductor on the substrate 1.
Finally, it is completed by sealing with the sealing resin 8.
【００１４】位置認識パターン３は、基板１の中心位置
および角度を簡単に、算出出来るパターンとし、複数の
パターンにて形成っても良い。The position recognition pattern 3 may be a pattern in which the center position and the angle of the substrate 1 can be easily calculated, and may be formed of a plurality of patterns.
【００１５】図２（ａ），（ｂ）は本発明の第２の実施
例の断面図及びその底面図である。2A and 2B are a sectional view and a bottom view of a second embodiment of the present invention.
【００１６】第２の実施例は図２（ａ），（ｂ）に示す
ように、位地認識パターン１３を除いては、第１の実施
例と同じ工程にて製造される。位置認識パターン１３
は、外部接続用電極２が形成された後、その外部接続用
電極２の位置を高精度に位置認識の出来る高性能な認識
装置を備えたレーザー、あるいは、インク等によるマー
キング装置によって、外部接続用電極２の位置を認識し
た後その位置データにより、位置決めされて±０．１ｍ
ｍ以下の精度で位置認識パターン１３が形成される。As shown in FIGS. 2A and 2B, the second embodiment is manufactured by the same process as the first embodiment except for the position recognition pattern 13. Position recognition pattern 13
After the external connection electrode 2 is formed, the external connection is performed by a laser equipped with a high-performance recognition device capable of recognizing the position of the external connection electrode 2 with high accuracy, or a marking device using ink or the like. After recognizing the position of the working electrode 2, it is positioned ± 0.1 m according to the position data.
The position recognition pattern 13 is formed with an accuracy of m or less.
【００１７】[0017]
【発明の効果】以上説明したように本発明は、リードレ
スチップキャリアにおいて、外部接続用電極との相対位
置が高精度である位置認識パターンを設けたので、この
位置認識パターンを用いて外部搭載基板との位置合わせ
をおこなって実装することにより、外部搭載基板の半田
付ランドとチップレスリードキャリアの外部接続用電極
の位置合わせ精度が±０．１ｍｍ以下まで向上し、ショ
ート，オープンといった接続不良が低減出来る効果があ
る。As described above, according to the present invention, the leadless chip carrier is provided with the position recognition pattern whose relative position to the external connection electrode is highly accurate. By aligning with the board and mounting, the positioning accuracy of the soldering land of the external mounting board and the external connection electrode of the chipless lead carrier is improved to ± 0.1 mm or less, and the connection failure such as short or open Is effective.
【００１８】特に、小型で多ピンのリードレスチップキ
ャリアほどその効果は大きく、０．５ｍｍピッチリード
レスチップキャリアに対しても、十分な搭載位置精度が
得られるという効果がある。In particular, the smaller the leadless chip carrier with a large number of pins, the greater the effect thereof, and the effect that sufficient mounting position accuracy can be obtained even with a 0.5 mm pitch leadless chip carrier.
【図１】本発明の第１の実施例の断面図及びその底面図
である。FIG. 1 is a sectional view and a bottom view of a first embodiment of the present invention.
【図２】本発明の第２の実施例の断面図及びその底面図
である。FIG. 2 is a sectional view and a bottom view of the second embodiment of the present invention.
【図３】従来のリードレスチップキャリアの一例の底面
図である。FIG. 3 is a bottom view of an example of a conventional leadless chip carrier.
１ 基板 ２ 外部接続用電極 ３，１３ 位置認識パターン ４ 端面スルーホール ５ 枠 ６ ボンディングワイヤ ７ ＩＣチップ ８ 封止樹脂 1 substrate 2 external connection electrode 3, 13 position recognition pattern 4 end face through hole 5 frame 6 bonding wire 7 IC chip 8 sealing resin
Claims (3)
ミックスとを含む素材から成る基板と、該基板上に形成
された外部接続用電極と、外部搭載基板との位置合わせ
用の位置認識パターンとを備えたことを特徴とするリー
ドレスチップキャリア。1. An electronic functional element, a substrate made of a material containing glass epoxy and ceramics, electrodes for external connection formed on the substrate, and a position recognition pattern for alignment with an external mounting substrate. Leadless chip carrier characterized by having.
位置認識パターン形状を形成する材料および形成工程に
おいて、外部接続用電極の形状を形成する材料および成
形工程と同一であることを特徴とする請求項１記載のリ
ードレスチップキャリア。2. The position recognizing pattern is at least the same as the material and forming step for forming the shape of the external connection electrode in the material and forming step for forming the position recognizing pattern shape. 1. The leadless chip carrier according to 1.
極形成後、外部接続用電極の位置を基準にして位置決め
されて形成されたことを特徴とする請求項１記載のリー
ドレスチップキャリア。3. The leadless chip carrier according to claim 1, wherein the position recognition pattern is formed after the electrode for external connection is formed and positioned with reference to the position of the electrode for external connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14385392A JPH05335438A (en) | 1992-06-04 | 1992-06-04 | Leadless chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14385392A JPH05335438A (en) | 1992-06-04 | 1992-06-04 | Leadless chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05335438A true JPH05335438A (en) | 1993-12-17 |
Family
ID=15348488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14385392A Pending JPH05335438A (en) | 1992-06-04 | 1992-06-04 | Leadless chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05335438A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0945814A (en) * | 1995-07-31 | 1997-02-14 | Nec Corp | Semiconductor device |
| JPH09129770A (en) * | 1995-10-31 | 1997-05-16 | Nec Corp | Integrated circuit device |
| US5705851A (en) * | 1995-06-28 | 1998-01-06 | National Semiconductor Corporation | Thermal ball lead integrated package |
| US5962917A (en) * | 1997-03-31 | 1999-10-05 | Nec Corporation | Semiconductor device package having end-face halved through-holes and inside-area through-holes |
| US6693243B1 (en) | 1999-11-25 | 2004-02-17 | Murata Manufacturing Co, Ltd. | Surface mounting component and mounted structure of surface mounting component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63213989A (en) * | 1987-03-02 | 1988-09-06 | 富士通株式会社 | Method of directing mounting direction of polarized component |
| JPH03229497A (en) * | 1990-02-05 | 1991-10-11 | Hitachi Ltd | Recording method of identification code of printed circuit board, reading method thereof and applied device thereof |
-
1992
- 1992-06-04 JP JP14385392A patent/JPH05335438A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63213989A (en) * | 1987-03-02 | 1988-09-06 | 富士通株式会社 | Method of directing mounting direction of polarized component |
| JPH03229497A (en) * | 1990-02-05 | 1991-10-11 | Hitachi Ltd | Recording method of identification code of printed circuit board, reading method thereof and applied device thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5705851A (en) * | 1995-06-28 | 1998-01-06 | National Semiconductor Corporation | Thermal ball lead integrated package |
| JPH0945814A (en) * | 1995-07-31 | 1997-02-14 | Nec Corp | Semiconductor device |
| JPH09129770A (en) * | 1995-10-31 | 1997-05-16 | Nec Corp | Integrated circuit device |
| US5962917A (en) * | 1997-03-31 | 1999-10-05 | Nec Corporation | Semiconductor device package having end-face halved through-holes and inside-area through-holes |
| US6693243B1 (en) | 1999-11-25 | 2004-02-17 | Murata Manufacturing Co, Ltd. | Surface mounting component and mounted structure of surface mounting component |
| EP1755367A2 (en) * | 1999-11-25 | 2007-02-21 | Murata Manufacturing Co., Ltd. | Surface mounting component and mounted structure of surface mounting component |
| EP1755367A3 (en) * | 1999-11-25 | 2007-03-07 | Murata Manufacturing Co., Ltd. | Surface mounting component and mounted structure of surface mounting component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5643835A (en) | Process for manufacturing and mounting a semiconductor device leadframe having alignment tabs | |
| KR100556239B1 (en) | Tape Carrier and Used Carrier Devices | |
| JP3569025B2 (en) | Semiconductor device and electronic device using the same | |
| US6459149B1 (en) | Electronic component, communication device, and manufacturing method for electronic component | |
| US5406119A (en) | Lead frame | |
| JPH05335438A (en) | Leadless chip carrier | |
| US5485337A (en) | Thin film magnetic head structure and method of fabricating the same for accurately locating and connecting terminals to terminal connections | |
| JPH01119088A (en) | Printed wiring board for mounting surface mounting parts | |
| JP2833174B2 (en) | Semiconductor device and mounting method thereof | |
| JPH05259372A (en) | Hibrid ic | |
| JPH03101142A (en) | Manufacture of semiconductor device | |
| JPS6359595A (en) | Mounting method in portable medium | |
| JPH065729A (en) | Aligning method for printed circuit board and semiconductor element | |
| JP2561642B2 (en) | Method of forming positioning marks for printed wiring board components | |
| JPH0349418Y2 (en) | ||
| JPH01287937A (en) | Film carrier tape | |
| KR200243279Y1 (en) | Circuit tape for semiconductor device | |
| JPH0252495A (en) | Method of mounting flat package ic | |
| JP2757349B2 (en) | Hybrid integrated circuit substrate and method of manufacturing hybrid integrated circuit device using the same | |
| JPS6155931A (en) | Manufacture of thick film hybrid integrated circuit device | |
| JP2550219Y2 (en) | Circuit board device | |
| JPH0750724B2 (en) | Liquid crystal display | |
| JP2773707B2 (en) | Manufacturing method of hybrid integrated circuit device | |
| JP2867547B2 (en) | Method of forming conductive protrusions | |
| JPS60231383A (en) | Printed circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980217 |