JPH05304362A - Manufacture of multi-layer wiring board - Google Patents
Manufacture of multi-layer wiring boardInfo
- Publication number
- JPH05304362A JPH05304362A JP13581692A JP13581692A JPH05304362A JP H05304362 A JPH05304362 A JP H05304362A JP 13581692 A JP13581692 A JP 13581692A JP 13581692 A JP13581692 A JP 13581692A JP H05304362 A JPH05304362 A JP H05304362A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- copper
- layer
- interlayer insulating
- polyimide resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多層配線板の製造方法
に関する。具体的にいうと、本発明は、ＬＳＩ等の電子
部品を実装するための多層配線板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board. Specifically, the present invention relates to a method for manufacturing a multilayer wiring board for mounting electronic components such as LSI.
【０００２】[0002]
【背景技術】最近、ＬＳＩ等の電子部品が実装される配
線板においては、信号遅延がマシンサイクル短縮の障害
になっており、実装系における信号伝送の高速化の要請
が高まっている。2. Description of the Related Art Recently, in wiring boards on which electronic components such as LSIs are mounted, signal delay has become an obstacle to shortening machine cycles, and there is an increasing demand for faster signal transmission in mounting systems.
【０００３】そこで、多層配線板における信号伝送特性
を良好にするため、層間絶縁膜に誘電率の小さなポリイ
ミド樹脂を用い、層間絶縁膜と銅メッキ配線を積層した
多層配線板が用いられるようになっている。さらに、製
造工程を簡略化することを目的として、ネガ型の感光性
ポリイミド樹脂を層間絶縁膜として用いた多層配線板が
利用されるようになってきている。Therefore, in order to improve the signal transmission characteristics of the multilayer wiring board, a multilayer wiring board in which a polyimide resin having a small dielectric constant is used for the interlayer insulating film and the interlayer insulating film and the copper-plated wiring are laminated has come to be used. ing. Furthermore, for the purpose of simplifying the manufacturing process, a multilayer wiring board using a negative photosensitive polyimide resin as an interlayer insulating film has come to be used.
【０００４】図３（ａ）（ｂ）はネガ型の感光性ポリイ
ミドを用いて層間絶縁膜にビアホール部を開口する工程
を示している。基板３１の上に樹脂絶縁層３２を設け、
樹脂絶縁層３２の上に銅メッキ配線３３を形成し、この
上にネガ型の感光性ポリイミド樹脂を塗布して層間絶縁
膜３４を形成した後、図３（ａ）のように層間絶縁膜３
４の上にネガ型フォトマスク３５を重ね、ネガ型フォト
マスク３５を通して層間絶縁膜３４に紫外線ランプ３６
より紫外線を照射する。紫外線を照射された部分は不溶
化されるので、現像すると図３（ｂ）に示すように紫外
線を照射されなかった箇所にビアホール部３７が開口さ
れる。したがって、感光性ポリイミド樹脂を用いれば、
層間絶縁膜の上にフォトレジストを塗布して通常のフォ
トリソグラフィ工程によりビアホール部を開口する方法
に比べ、大幅に工程を簡略化できる。FIGS. 3A and 3B show a process of forming a via hole in an interlayer insulating film by using a negative type photosensitive polyimide. The resin insulating layer 32 is provided on the substrate 31,
After forming a copper-plated wiring 33 on the resin insulation layer 32 and applying a negative photosensitive polyimide resin thereon to form an interlayer insulation film 34, an interlayer insulation film 3 is formed as shown in FIG.
4 is overlaid with a negative photomask 35, and the ultraviolet lamp 36 is applied to the interlayer insulating film 34 through the negative photomask 35.
Irradiate more ultraviolet rays. Since the portion irradiated with the ultraviolet rays is insolubilized, the via hole portion 37 is opened at the portion not irradiated with the ultraviolet rays when developed, as shown in FIG. 3B. Therefore, if a photosensitive polyimide resin is used,
The process can be greatly simplified as compared with a method in which a photoresist is applied on the interlayer insulating film and a via hole portion is opened by an ordinary photolithography process.
【０００５】しかしながら、この方法にあっては、銅メ
ッキ配線上に層間絶縁膜としてネガ型の感光性ポリイミ
ド樹脂を塗布したとき、塩結合型ポリイミド樹脂である
とエステル結合型ポリイミド樹脂であると問わず、ネガ
型の感光性ポリイミド樹脂と銅メッキ配線との間で化学
反応が生じ、銅メッキ配線上に絶縁性の反応生成物が生
じている。このため、層間接続用のビアホール部におい
て、下層の銅メッキ配線と上層の銅メッキ配線の接合面
の抵抗値が著しく高くなるという欠点があった。例え
ば、ビアホール部の開口寸法を２０μｍ角とすると、ビ
アホール部における上層及び下層の銅メッキ配線間の抵
抗値は約１Ωとなり、理論計算値の１０００倍という高
い抵抗値になっていた。However, according to this method, when a negative photosensitive polyimide resin is applied as an interlayer insulating film on the copper-plated wiring, it is said that the salt bond type polyimide resin is the ester bond type polyimide resin. However, a chemical reaction occurs between the negative photosensitive polyimide resin and the copper-plated wiring, and an insulating reaction product is generated on the copper-plated wiring. Therefore, in the via hole portion for interlayer connection, there is a drawback that the resistance value of the joint surface between the lower layer copper-plated wiring and the upper layer copper-plated wiring is significantly increased. For example, when the opening size of the via hole portion is 20 μm square, the resistance value between the upper and lower copper-plated wirings in the via hole portion is about 1Ω, which is as high as 1000 times the theoretical calculated value.
【０００６】そこで、銅メッキ配線と感光性ポリイミド
樹脂との化学反応によるビアホール部の抵抗値の増大を
防止する方法として、銅メッキ配線をＣｒやＴｉ等の保
護膜で被覆し、保護膜の上から感光性ポリイミド樹脂を
積層して硬化させた後、ビアホール部のみで銅メッキ配
線から保護膜を剥離させ、保護膜から露出させた銅メッ
キ配線の表面に上層の銅メッキ配線を接合させ、ビアホ
ール部の抵抗値を小さくする方法が提案されている（特
開昭６１−２９４８９５号公報）。Therefore, as a method of preventing the resistance value of the via hole portion from increasing due to the chemical reaction between the copper-plated wiring and the photosensitive polyimide resin, the copper-plated wiring is covered with a protective film such as Cr or Ti, and After the photosensitive polyimide resin is laminated and cured, the protective film is peeled off from the copper-plated wiring only in the via-hole portion, and the upper-layer copper-plated wiring is bonded to the surface of the copper-plated wiring exposed from the protective film, and the via-hole is formed. There has been proposed a method of reducing the resistance value of a part (Japanese Patent Laid-Open No. 61-294895).
【０００７】しかしながら、銅メッキ配線の上に保護膜
を形成する方法では、銅メッキ配線の上に保護膜を形成
したり、ビアホール部で保護膜（銅メッキ配線よりも抵
抗が高い）を除去したりしなければならず、製造プロセ
スが増加して工程が繁雑化するという欠点があった。ま
た、クロムメッキ保護膜では、メッキ液原料として有毒
性のある六価クロムを使用しなければならず、衛生上危
険であった。However, in the method of forming the protective film on the copper-plated wiring, the protective film is formed on the copper-plated wiring or the protective film (having higher resistance than the copper-plated wiring) is removed at the via hole portion. However, there is a drawback that the manufacturing process is increased and the process is complicated. Further, in the chromium plating protective film, it is necessary to use toxic hexavalent chromium as a plating liquid raw material, which is a sanitary risk.
【０００８】[0008]
【０００９】本発明は、叙上の従来例の欠点に鑑みてな
されたものであり、その目的とするところは、層間絶縁
膜として感光性ポリイミド樹脂のような感光性有機高分
子材料を用いた多層配線板において、安全で簡略な方法
によりビアホール部における抵抗値を低減させることに
ある。The present invention has been made in view of the above-mentioned drawbacks of conventional examples, and its object is to use a photosensitive organic polymer material such as a photosensitive polyimide resin as an interlayer insulating film. In a multilayer wiring board, it is to reduce the resistance value in the via hole portion by a safe and simple method.
【００１０】[0010]
【課題を解決するための手段】本発明の多層配線板の製
造方法は、有機高分子材料で形成された層間絶縁膜と銅
配線を積層した多層配線板の製造方法において、前記銅
配線の上からポジ型の感光性有機高分子材料を塗布して
層間絶縁膜を形成する工程と、前記層間絶縁膜に層間接
続用ビアホール部を開口する工程と、前記層間絶縁膜を
硬化させる工程とを有することを特徴としている。A method for manufacturing a multilayer wiring board according to the present invention is a method for manufacturing a multilayer wiring board in which an interlayer insulating film formed of an organic polymer material and copper wiring are laminated, From the positive type photosensitive organic polymer material to form an interlayer insulating film, a step of opening a via hole portion for interlayer connection in the interlayer insulating film, and a step of curing the interlayer insulating film It is characterized by
【００１１】[0011]
【作用】本発明の多層配線板の製造方法にあっては、感
光性有機高分子材料を用いて層間絶縁膜を形成している
ので、層間絶縁膜のパターニング（ビアホール部の形
成）を容易に行なえ、製造プロセスを短絡化することが
できる。In the method for manufacturing a multilayer wiring board according to the present invention, since the interlayer insulating film is formed by using the photosensitive organic polymer material, it is easy to pattern the interlayer insulating film (form a via hole portion). The manufacturing process can be short-circuited.
【００１２】また、ネガ型と異なり、ポジ型の感光性有
機高分子材料は銅配線と化学反応しにくいので、ビアホ
ール部の抵抗値の増大を防止するために銅配線の上に保
護膜を形成する必要がなく、ビアホール部の抵抗値の増
大を防止しつつ多層配線板の製造工程を簡単にすること
ができる。また、クロムメッキ保護膜を形成する場合の
ように安全面での問題も生じない。Further, unlike the negative type, since the positive type photosensitive organic polymer material does not easily chemically react with the copper wiring, a protective film is formed on the copper wiring to prevent the resistance value of the via hole from increasing. Therefore, it is possible to simplify the manufacturing process of the multilayer wiring board while preventing the resistance value of the via hole portion from increasing. Further, there is no problem in safety as in the case of forming the chromium plating protective film.
【００１３】さらに、層間絶縁膜としてポジ型の感光性
有機高分子材料を用いることにより、焼成時における膜
厚の減少が小さくなるので、層間絶縁膜のパターン精度
を高めることができる。Further, since the positive type photosensitive organic polymer material is used as the interlayer insulating film, the decrease in the film thickness during firing is reduced, so that the pattern accuracy of the interlayer insulating film can be improved.
【００１４】[0014]
【実施例】図１（ａ）〜（ｉ）に本発明の一実施例によ
る多層配線板の製造方法を示す。以下、図１にしたがっ
て多層配線基板Ａの製造方法を説明する。まず、図１
（ａ）に示すように、絶縁基板としてアルミナ基板１を
用い、アルミナ基板１の上にポリイミド樹脂を塗布し、
３７０℃で加熱硬化させ、ポリイミド樹脂からなる樹脂
絶縁層２を形成し、アルミナ基板１の表面を平滑化す
る。1 (a) to 1 (i) show a method of manufacturing a multilayer wiring board according to an embodiment of the present invention. Hereinafter, a method of manufacturing the multilayer wiring board A will be described with reference to FIG. First, Fig. 1
As shown in (a), an alumina substrate 1 is used as an insulating substrate, and a polyimide resin is applied onto the alumina substrate 1,
It is heated and cured at 370 ° C. to form a resin insulating layer 2 made of a polyimide resin, and the surface of the alumina substrate 1 is smoothed.
【００１５】ついで、樹脂絶縁層２をアルカリ液中で表
面粗化させた後、樹脂絶縁層２の上に塩化スズ及び塩化
パラジウムで活性種を付け、硫酸銅無電解メッキ浴中で
樹脂絶縁層２の表面に厚さ５００Åの無電解銅メッキを
施し、図１（ｂ）に示すように下地導体層３を形成す
る。Next, after the surface of the resin insulating layer 2 is roughened in an alkaline solution, an active species is added to the resin insulating layer 2 with tin chloride and palladium chloride, and the resin insulating layer is placed in a copper sulfate electroless plating bath. The surface of 2 is subjected to electroless copper plating with a thickness of 500 Å to form a base conductor layer 3 as shown in FIG. 1 (b).
【００１６】この下地導体層３の表面上にフォトレジス
ト（ＡＺ４６２０；ヘキスト社製）を塗布し、図１
（ｃ）に示すように、露光及び現像を行って銅メッキ配
線パターンの反転パターンを有する厚さ７μｍのレジス
トパターン４を形成する。A photoresist (AZ4620; manufactured by Hoechst) is coated on the surface of the underlying conductor layer 3, and the result is shown in FIG.
As shown in (c), exposure and development are performed to form a resist pattern 4 having a thickness of 7 μm and having a reverse pattern of the copper-plated wiring pattern.
【００１７】次に、下地導体層３を電極として硫酸銅メ
ッキ浴中で電解メッキを施し、図１（ｄ）に示すよう
に、下地導体層３の上のフォトレジストパターン４で覆
われていない領域に厚さ５μｍの銅メッキ配線５を形成
する。Next, electrolytic plating is performed in a copper sulfate plating bath using the underlying conductor layer 3 as an electrode, and as shown in FIG. 1 (d), it is not covered with the photoresist pattern 4 on the underlying conductor layer 3. A copper plated wiring 5 having a thickness of 5 μm is formed in the region.
【００１８】ついで、フォトレジストパターン４をアセ
トン浴中で除去した後、過硫酸アンモニウム溶液中で下
地導体層３の不要部分をエッチング除去し、下地導体層
３及び銅メッキ配線５からなる配線パターン６を得る
〔図１（ｅ）〕。Then, after removing the photoresist pattern 4 in an acetone bath, an unnecessary portion of the underlying conductor layer 3 is removed by etching in an ammonium persulfate solution to form a wiring pattern 6 consisting of the underlying conductor layer 3 and the copper-plated wiring 5. Obtain [FIG. 1 (e)].
【００１９】この後、図１（ｆ）に示すように、ポジ型
の感光性ポリイミド樹脂（ＲＮ−９０１；日産化学製）
を配線パターン６の上からスピンコート塗布して層間絶
縁膜７を形成し、８０℃でプリベークする。Thereafter, as shown in FIG. 1 (f), a positive photosensitive polyimide resin (RN-901; manufactured by Nissan Kagaku)
Is coated on the wiring pattern 6 by spin coating to form an interlayer insulating film 7 and prebaked at 80 ° C.
【００２０】ついで、図１（ｇ）に示すように、層間絶
縁膜７の上にポジ型フォトマスク８を重ね、ポジ型フォ
トマスク８を通して層間絶縁膜７に紫外線ランプ９より
紫外線を照射する。紫外線を照射された部分は可溶化さ
れるので、現像すると図１（ｈ）に示すように紫外線を
照射された箇所に２０μｍ角の層間接続用ビアホール部
１０が開口される。この後、３７０℃で１時間ポストベ
ークして層間絶縁膜７のポリイミド樹脂を硬化させる。Then, as shown in FIG. 1G, a positive type photomask 8 is overlaid on the interlayer insulating film 7, and the interlayer insulating film 7 is irradiated with ultraviolet rays from an ultraviolet lamp 9 through the positive type photomask 8. Since the portion irradiated with the ultraviolet rays is solubilized, the via hole portion 10 for interlayer connection of 20 μm square is opened at the portion irradiated with the ultraviolet rays as shown in FIG. After that, post-baking is performed at 370 ° C. for 1 hour to cure the polyimide resin of the interlayer insulating film 7.
【００２１】こうしてビアホール部１０を開口した後、
図１（ｉ）に示すように、１層目の配線パターン６と同
様にして２層目の配線パターン１１を形成し、ビアホー
ル部１０を通して１層目及び２層目の配線パターン６，
１１を導通させる。すなわち、層間絶縁膜７上およびビ
アホール部１０内に無電解銅メッキ下地導体層を形成し
た後、フォトリソグラフィ工程及び電解メッキ工程を用
いて下地導体層の上に所定パターンの電解銅メッキ配線
を形成し、下地導体層の不要部分を除去して所望の配線
パターン１１を得る。After opening the via hole portion 10 in this manner,
As shown in FIG. 1I, a wiring pattern 11 of the second layer is formed in the same manner as the wiring pattern 6 of the first layer, and the wiring patterns 6 of the first and second layers are formed through the via hole portion 10.
11 is conducted. That is, after forming an electroless copper-plated underlying conductor layer on the interlayer insulating film 7 and in the via hole portion 10, an electrolytic copper-plated wiring of a predetermined pattern is formed on the underlying conductor layer using a photolithography process and an electrolytic plating process. Then, unnecessary portions of the underlying conductor layer are removed to obtain a desired wiring pattern 11.
【００２２】なお、ポジ型感光性ポリイミド樹脂の層間
絶縁膜を形成する工程と配線パターンを形成する工程を
必要回数だけ繰り返せば、さらに多層の多層配線板を製
作することができる。By repeating the step of forming the interlayer insulating film of the positive type photosensitive polyimide resin and the step of forming the wiring pattern as many times as necessary, a multilayer wiring board having more layers can be manufactured.
【００２３】図２は、ネガ型の感光性ポリイミドを用
いた場合と、クロム（Ｃｒ）メッキ保護膜を用いた場
合と、ポジ型の感光性ポリイミド樹脂を用いた場合の
各ビアホール部の電気抵抗を示している。すなわち、
銅メッキ配線上に直接ネガ型の感光性ポリイミド樹脂を
塗布して層間絶縁膜を形成した場合、銅メッキ配線上
にクロムメッキ保護膜を設け、この上からネガ型感光性
ポリイミド樹脂を塗布し、ビアホール部でクロムメッキ
保護膜を除去して上層の配線パターンと接続した場合、
銅メッキ配線の上に直接ポジ型の感光性ポリイミド樹
脂を塗布して層間絶縁膜を形成した場合の各電気抵抗を
示す。FIG. 2 shows the electrical resistance of each via hole when a negative photosensitive polyimide is used, when a chromium (Cr) plating protective film is used, and when a positive photosensitive polyimide resin is used. Is shown. That is,
When the negative-type photosensitive polyimide resin is applied directly on the copper-plated wiring to form the interlayer insulating film, a chromium-plated protective film is provided on the copper-plated wiring, and the negative-type photosensitive polyimide resin is applied from above. When removing the chromium plating protective film at the via hole and connecting to the upper wiring pattern,
Each electric resistance when a positive type photosensitive polyimide resin is directly applied on the copper-plated wiring to form an interlayer insulating film is shown.
【００２４】図２によれば、ポジ型感光性ポリイミド樹
脂の層間絶縁膜を形成した場合の抵抗値は、クロムメッ
キ保護膜を用いた場合と同レベルであり、ネガ型感光性
ポリイミド樹脂の層間絶縁膜を形成した場合と比較して
１〜２桁抵抗値が小さくなっている。According to FIG. 2, the resistance value when the interlayer insulating film of the positive type photosensitive polyimide resin is formed is the same level as when the chromium plating protective film is used, and the resistance value of the negative type photosensitive polyimide resin is not the same. The resistance value is 1 to 2 digits smaller than that when the insulating film is formed.
【００２５】なお、絶縁基板の材料はアルミナが一般的
であるが、これに限られるものではなく、表面平滑性の
得られる絶縁材料なら何でも良い。また、樹脂絶縁層の
材料は、ポリイミド樹脂に限るものでなく、エポキシ樹
脂等の熱硬化性樹脂でも良いし、液晶ポリマー等の熱可
塑性樹脂でも良い。また、下地導体層は無電解メッキ法
（アディティブ法）で作製しても良いし、真空蒸着法や
スパッタリング法で性膜しても良い。Alumina is generally used as the material of the insulating substrate, but the material is not limited to this, and any insulating material having surface smoothness may be used. The material of the resin insulation layer is not limited to the polyimide resin, but may be a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a liquid crystal polymer. The underlying conductor layer may be formed by an electroless plating method (additive method) or may be formed by a vacuum deposition method or a sputtering method.
【００２６】[0026]
【発明の効果】本発明によれば、感光性ポリイミド樹脂
を用いて層間絶縁膜を形成しているので、製造プロセス
を短絡化することができる。According to the present invention, since the interlayer insulating film is formed by using the photosensitive polyimide resin, the manufacturing process can be short-circuited.
【００２７】また、ポジ型の感光性有機高分子材料を用
いることによりビアホール部の抵抗値の増大を防止する
ため、銅配線の上に保護膜を形成する必要がなく、ビア
ホール部の抵抗値の増大を防止しつつ多層配線板の製造
工程を安全かつ簡単にすることができる。Further, since the positive type photosensitive organic polymer material is used to prevent the resistance value of the via hole portion from increasing, it is not necessary to form a protective film on the copper wiring, and the resistance value of the via hole portion can be reduced. It is possible to safely and simplify the manufacturing process of the multilayer wiring board while preventing the increase.
【００２８】さらに、層間絶縁膜としてポジ型の感光性
有機高分子材料を用いることにより、焼成時における膜
厚の減少が小さくなるので、層間絶縁膜のパターン精度
を高めることができ、多層配線板の品質も向上する。Further, since the positive type photosensitive organic polymer material is used as the interlayer insulating film, the reduction in the film thickness during firing is reduced, so that the pattern accuracy of the interlayer insulating film can be improved and the multilayer wiring board can be obtained. Also improves the quality of.
【図１】（ａ）（ｂ）（ｃ）（ｄ）（ｅ）（ｆ）（ｇ）
（ｈ）（ｉ）は本発明の一実施例による多層配線板の製
造方法を示す断面図である。1 (a) (b) (c) (d) (e) (f) (g)
(H) (i) is sectional drawing which shows the manufacturing method of the multilayer wiring board by one Example of this invention.
【図２】ネガ型の感光性ポリイミド樹脂を用いた場合
と、銅メッキ配線の上にクロムメッキ保護膜を形成した
場合と、ポジ型の感光性ポリイミド樹脂を用いた場合の
ビアホール部の電気抵抗を示す図である。FIG. 2 is an electrical resistance of a via hole when a negative photosensitive polyimide resin is used, when a chromium plating protective film is formed on copper-plated wiring, and when a positive photosensitive polyimide resin is used. FIG.
【図３】（ａ）（ｂ）はネガ型の感光性ポリイミド樹脂
を用いた場合のビアホール部形成工程を示す断面図であ
る。3A and 3B are cross-sectional views showing a step of forming a via hole when a negative photosensitive polyimide resin is used.
５ 銅メッキ配線 ６ 配線パターン ７ 層間絶縁膜 １０ ビアホール部 １１ 配線パターン 5 Copper plating wiring 6 Wiring pattern 7 Interlayer insulating film 10 Via hole 11 Wiring pattern
Claims (1)
と銅配線を積層した多層配線板の製造方法において、 前記銅配線の上からポジ型の感光性有機高分子材料を塗
布して層間絶縁膜を形成する工程と、 前記層間絶縁膜に層間接続用ビアホール部を開口する工
程と、 前記層間絶縁膜を硬化させる工程とを有することを特徴
とする多層配線板の製造方法。1. A method for manufacturing a multilayer wiring board in which an interlayer insulating film made of an organic polymer material and copper wiring are laminated, wherein a positive photosensitive organic polymer material is applied on the copper wiring to form an interlayer. A method of manufacturing a multilayer wiring board, comprising: a step of forming an insulating film; a step of opening a via hole portion for interlayer connection in the interlayer insulating film; and a step of curing the interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13581692A JPH05304362A (en) | 1992-04-28 | 1992-04-28 | Manufacture of multi-layer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13581692A JPH05304362A (en) | 1992-04-28 | 1992-04-28 | Manufacture of multi-layer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05304362A true JPH05304362A (en) | 1993-11-16 |
Family
ID=15160482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13581692A Pending JPH05304362A (en) | 1992-04-28 | 1992-04-28 | Manufacture of multi-layer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05304362A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007189095A (en) * | 2006-01-13 | 2007-07-26 | Fuji Electric Systems Co Ltd | Method of manufacturing silicon multilayer wiring board, and method of evaluating silicon multilayer wiring board |
| KR100797708B1 (en) * | 2006-10-24 | 2008-01-23 | 삼성전기주식회사 | Fabricating method of printed circuit board |
| US7361849B2 (en) | 1996-12-19 | 2008-04-22 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
-
1992
- 1992-04-28 JP JP13581692A patent/JPH05304362A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7361849B2 (en) | 1996-12-19 | 2008-04-22 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| US7371976B2 (en) | 1996-12-19 | 2008-05-13 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| US7385146B2 (en) | 1996-12-19 | 2008-06-10 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| US7388159B2 (en) | 1996-12-19 | 2008-06-17 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| US7449791B2 (en) | 1996-12-19 | 2008-11-11 | Ibiden Co., Ltd. | Printed circuit boards and method of producing the same |
| US7585541B2 (en) | 1996-12-19 | 2009-09-08 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| US7615162B2 (en) | 1996-12-19 | 2009-11-10 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| US7712212B2 (en) | 1996-12-19 | 2010-05-11 | Ibiden Co., Ltd. | Method for manufacturing printed wiring board |
| USRE43509E1 (en) | 1996-12-19 | 2012-07-17 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| JP2007189095A (en) * | 2006-01-13 | 2007-07-26 | Fuji Electric Systems Co Ltd | Method of manufacturing silicon multilayer wiring board, and method of evaluating silicon multilayer wiring board |
| KR100797708B1 (en) * | 2006-10-24 | 2008-01-23 | 삼성전기주식회사 | Fabricating method of printed circuit board |
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