JPH0529527A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0529527A JPH0529527A JP3200257A JP20025791A JPH0529527A JP H0529527 A JPH0529527 A JP H0529527A JP 3200257 A JP3200257 A JP 3200257A JP 20025791 A JP20025791 A JP 20025791A JP H0529527 A JPH0529527 A JP H0529527A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- lead
- leads
- suspension lead
- tab suspension
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はフラットパッケージ型の
半導体装置に関し、特に多ピン化を図った半導体装置に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat package type semiconductor device, and more particularly to a semiconductor device having a large number of pins.
【０００２】[0002]
【従来の技術】一般にフラットパッケージ型の半導体装
置はデュアルインライン型のパッケージに比較して薄型
化及び多ピン化が容易であり、しかも実装用回路基板
（プリント基板）への実装はチップキャリアパッケージ
と略同程度の実装作業でよいという利点からその需要は
増大している。この種の半導体装置は通常金属薄板を打
抜成形して得られたリードフレームに半導体素子ペレッ
トを固着しかつリードとの間に電気的接続を行った上
で、ペレットやリードとの接続部を方形（正方形、長方
形）でかつ薄肉のパッケージ形状にプラスチック封止し
た構成としている。そして、このようにパッケージの平
面形状を方形にしたときには、図１に示すようにパッケ
ージ本体１の一角部を面取り形成し、この面取り部２を
複数本のピン（リード）３のインデックスとして利用し
ているのである。2. Description of the Related Art Generally, a flat package type semiconductor device can be made thinner and have a larger number of pins than a dual inline type package, and a chip carrier package can be mounted on a mounting circuit board (printed circuit board). The demand is increasing due to the advantage that almost the same level of mounting work is required. In this type of semiconductor device, a semiconductor element pellet is usually fixed to a lead frame obtained by stamping and molding a thin metal plate, and an electrical connection is made between the lead and the lead. It is square (square, rectangular) and has a thin-walled package shape and is sealed with plastic. When the package has a rectangular planar shape as described above, one corner of the package body 1 is chamfered as shown in FIG. 1, and the chamfered portion 2 is used as an index of a plurality of pins (leads) 3. -ing
【０００３】近年の半導体装置は益々高密度化されかつ
多ピン化される傾向にある。この反面、設計、製作ある
いは実装上の理由からパッケージの本体形状や寸法を一
定に保つことが要求されることがある。したがって、こ
のような場合はリードピッチを可及的に小さくしかつパ
ッケージ本体１の四周側長を最大に利用してピン３を配
設することにより多ピン化に対応せざるを得ない。In recent years, semiconductor devices tend to have higher density and more pins. On the other hand, for designing, manufacturing, or mounting reasons, it may be required to keep the shape and size of the package body constant. Therefore, in such a case, it is inevitable to increase the number of pins by reducing the lead pitch as much as possible and arranging the pins 3 by making maximum use of the length of the package body 1 on the four circumference side.
【０００４】しかしながら、前記従来の半導体装置で
は、インデックスとしての面取り部２を設けたことによ
りこの部分にはピン３を設けておらず、このためパッケ
ージ本体の四周側の利用度が低下されて多ピン化の障害
になっている。また、面取り部２にピンを配設していな
いため、特に面取り部２に接する周側面１ａと１ｂにお
いては、ピンをパッケージ本体１の中心０に対して対称
に配列できず、これにより設計、製作や実装において不
利が生ずることがある。更に詳細に後述するが、面取り
部２にピンを設けないことからこれに対応するリードフ
レームの相当部位には当然リードを設けておらず、これ
がためプラスチックの洩れが生じて外観の低下やパッケ
ージの欠けを誘発し、商品価値を低下させるという問題
もある。However, in the conventional semiconductor device, since the chamfered portion 2 as an index is provided, the pin 3 is not provided in this portion, and therefore the utilization on the four sides of the package body is reduced, which is often a problem. It is an obstacle to pinning. In addition, since the pins are not provided in the chamfered portion 2, the pins cannot be arranged symmetrically with respect to the center 0 of the package body 1 particularly on the peripheral side surfaces 1a and 1b which are in contact with the chamfered portion 2. Disadvantages may occur in manufacturing and implementation. As will be described in more detail later, since the chamfered portion 2 is not provided with a pin, the corresponding portion of the lead frame corresponding thereto is not provided with a lead, which causes leakage of the plastic and deteriorates the appearance and the package. There is also the problem of inducing chipping and reducing the commercial value.
【０００５】[0005]
【発明が解決しようとする課題】本願発明の目的は半導
体装置の多ピン化を可能とすると共にその設計、製作、
実装を容易にすることにある。SUMMARY OF THE INVENTION An object of the present invention is to enable a semiconductor device to have a large number of pins, and to design, manufacture,
It is to facilitate the implementation.
【０００６】[0006]
【課題を解決するための手段】図５に記載されるようタ
ブ１４の角部から離れてその近くにタブ吊りリード２１
を設け、このタブ吊りリード２１の終端をタブの角部に
対応した封止体の角部近傍に連結することによりタブ１
４を支持させる。更に、このリードフレーム１８は、タ
ブ吊りリード２１にリードを近接して配置させることに
よりリードとタブ吊りリードとの隙間を可及的に小さく
させる。そして、タブ吊りリードに近接され、かつタブ
吊りリードとタブの角部との間から延びるリードが、タ
ブ吊りリードが設けられる一辺に対して縦方向に延びる
タブの一辺から延びる複数のリードとその終端が同一方
向になるようにリードを設けた。As shown in FIG. 5, tab suspension leads 21 are spaced apart from and close to the corners of the tab 14.
Is provided and the end of the tab suspension lead 21 is connected near the corner of the sealing body corresponding to the corner of the tab.
Support 4. Further, in the lead frame 18, by disposing the lead close to the tab suspension lead 21, the gap between the lead and the tab suspension lead is made as small as possible. A lead that is adjacent to the tab suspension lead and that extends from between the tab suspension lead and the corner of the tab is a plurality of leads that extend from one side of the tab that extends in the longitudinal direction with respect to one side where the tab suspension lead is provided, and The leads were provided so that the ends were in the same direction.
【０００７】[0007]
【作用】本発明のリードフレーム１８では、リードとタ
ブ吊りリード２１との間の隙間が小さいので、半導体装
置の多ピン化を可能とすると共にその設計、製作、実装
を容易にすることができる。また、レジンがこの隙間２
２を通ってダム１９に流れ出ること、つまり図５Ａ部に
おけるレジン流れ（はみ出し）を少なく抑えることがで
きる。In the lead frame 18 of the present invention, since the gap between the lead and the tab suspension lead 21 is small, it is possible to increase the number of pins of the semiconductor device and facilitate its design, manufacture and mounting. . In addition, the resin is this gap 2
It is possible to suppress the flow of the resin through the dam 2 to the dam 19, that is, the resin flow (protrusion) in the portion of FIG. 5A.
【０００８】[0008]
【実施例】以下、本発明を図示の実施例により説明す
る。The present invention will be described below with reference to the illustrated embodiments.
【０００９】図２は本発明のリードフレームを用いた半
導体装置の全体斜視図、図３はその一部断面図であり、
１０はパッケージ本体、１１はその四周囲側面に突設し
たリード（ピン）である。前記パッケージ本体１０はレ
ジン（プラスチック）材をモールド成形する等して全体
を偏平にかつその平面形状を長方形等の方計に形成して
おり、前記リード１１の内端部、すなわちインナーリー
ド１２や半導体素子ペレット１３を内装封止している。
半導体素子ペレット１３は略正方形のタブ１４上面に固
着し、その電極パッドと前記各リード１１のインナーリ
ード１２とをワイヤ１５にて接続している。また前記パ
ッケージ本体１０は一角部を面取りした形状としてこれ
をインデックス１６として構成している。一方、前記リ
ード１１は夫々等しいピッチにてパッケージ本体１０の
四周囲側面に並設しかつそのアウターリード１７を四周
外方に向けて突設している。この場合、アウターリード
１７は段上に折曲し、図外の実装用プリント基盤上にパ
ッケージ本体１０を載置したときにアウターリード１７
先端部がプリント基盤の配線に接触できるようにしてい
る。また、このリード１７はパッケージ本体１０の中心
位置に対して対称形となるように配設すると共にパッケ
ージ本体１０の四周囲を最大限に有効利用するように配
設しており、したがって前記リード１１の一部、本例で
はリード１１ａと１１ｂは前記パッケージ本体１０の面
取りされた側面、つまりインデックス１６面に配設し、
この面から各アウターリド１７ａ、１７ｂを夫々直角方
向に突設させている。FIG. 2 is an overall perspective view of a semiconductor device using the lead frame of the present invention, and FIG. 3 is a partial sectional view thereof.
Reference numeral 10 is a package body, and 11 is leads (pins) projectingly provided on the four peripheral side surfaces thereof. The package main body 10 is formed into a flat shape by molding a resin (plastic) material or the like into a plan shape such as a rectangle, and the inner end portion of the lead 11, that is, the inner lead 12 or The semiconductor element pellet 13 is internally sealed.
The semiconductor element pellet 13 is fixed to the upper surface of the tab 14 having a substantially square shape, and its electrode pad and the inner lead 12 of each lead 11 are connected by a wire 15. Further, the package body 10 has a chamfered corner, and is formed as an index 16. On the other hand, the leads 11 are arranged side by side on the four peripheral side surfaces of the package body 10 at equal pitches, and the outer leads 17 thereof are provided so as to project outward four rounds. In this case, the outer leads 17 are bent upward, and when the package main body 10 is placed on a mounting print board (not shown), the outer leads 17 are bent.
The tip is designed to contact the wiring of the printed circuit board. Further, the leads 17 are arranged so as to be symmetrical with respect to the center position of the package body 10, and are arranged so as to make the most effective use of the four circumferences of the package body 10. , A lead 11a and 11b in this example are arranged on the chamfered side surface of the package body 10, that is, the index 16 surface,
From this surface, the outer lids 17a and 17b are respectively provided so as to project in a right angle direction.
【００１０】図４は前記半導体装置に適用されたリード
フレーム１８を示す。このリードフレーム１８は４２ア
ロイ等からなる知冊状の金属薄版を打抜成形あるいはエ
ッチング等に多連形成しており、本例では５個のパッケ
ージに相当するリード等を連設した多連フレームとして
構成している。各パッケージ相当箇所は、その要部を図
５に合わせて示すように、中央に形成された方形のタブ
１４の周囲に複数本のリード１１の各インナーリード１
２を放射状に配設すると共に各リード１１は枠上のダム
１９により一体に連結し、かつ各リード１１のアウター
リード１７は当ピッチ間隔で四周囲方向に延設してフレ
ーム部２０に連結している。また、前記タブ１４はその
四角部にタブ吊りリード２１を設け、このタブ吊りリー
ド２１を前記ダム１９に連結することによりタブ１４を
フレーム部２０に支持している。更に、このリードフレ
ーム１８は、前記インデックス１６に配設するリード11
a、１１ｂとタブ吊りリード２１に近接配置し、リード１
１ａ、１１ｂとタブ吊りリード２１との間の隙間２２を
可及的に小さくしている。因みに、図７に示す本願発明
に先だって考えられたリードフレーム１８ａではリード
１１ａ、１１ｂに相当するものが存在していないため、
タブ吊りリード２１と近接するリード１１との間の隙間
２２Ａが大きなものとなっている。FIG. 4 shows a lead frame 18 applied to the semiconductor device. The lead frame 18 is formed by punching or etching a thin metal plate in the form of a plate made of 42 alloy or the like, and in this example, a lead is formed corresponding to five packages. It is configured as a frame. Each package-corresponding portion has a plurality of inner leads 1 of a plurality of leads 11 around a rectangular tab 14 formed in the center, as shown in FIG.
2, the leads 11 are integrally connected by the dam 19 on the frame, and the outer leads 17 of each lead 11 are extended at four pitch intervals in the circumferential direction and are connected to the frame portion 20. ing. The tab 14 is provided with tab suspension leads 21 on its square portion, and the tab suspension leads 21 are connected to the dam 19 to support the tabs 14 on the frame portion 20. Further, the lead frame 18 is provided with the leads 11 arranged on the index 16.
a, 11b and the tab suspension lead 21 are arranged close to each other, and the lead 1
The gap 22 between the tabs 1a and 11b and the tab suspension lead 21 is made as small as possible. By the way, in the lead frame 18a considered prior to the present invention shown in FIG. 7, there is no one corresponding to the leads 11a and 11b,
The gap 22A between the tab suspension lead 21 and the adjacent lead 11 is large.
【００１１】尚、前記リードフレーム１８の各パッケー
ジの一隅部には、打ち抜きを行わないゲート上面板部２
９を設け、後述するようにレジンモールドの際のレジン
流を規制するようにしている。２９Ａは従来のゲート上
面板部である。また、図４のようにリードフレーム１８
の内側には複数個のガイド孔２３を形成し、自動組立の
際の送りに利用される。In addition, at one corner of each package of the lead frame 18, the gate upper surface plate portion 2 which is not punched out.
9 is provided to regulate the resin flow at the time of resin molding as described later. 29A is a conventional gate top plate. In addition, as shown in FIG.
A plurality of guide holes 23 are formed on the inner side of, and used for feeding at the time of automatic assembly.
【００１２】以上の構成のリードフレーム１８では、タ
ブ１４やインナーリード１２に金等のめつきを施した
後、タブ１４表面には半導体素子ペレット１３を公知の
金シリコン共晶等により固着し、かつペレット１３とイ
ンナーリード１２間にワイヤ１５を接続して電気的接続
を行う。しかる後、図６に示すように、リードフレーム
１８を上、下のレジンモールド型２４、２５内にセット
してそのキャビティ２６内にタブ１４、インナーリード
１２、ペレット１３、ワイヤ１５を配置し、下モールド
型２５内に形成したゲート２７から封止用レジン２８を
キャビティ２６内に圧送する。このとき、リードフレー
ム１８に設けたゲート上面板部２９をゲート２７の直上
位置に配置し、ゲート２７から吐き出されたレジンをキ
ャビティ奥方へ誘導させる。また、キャビティ内へ圧送
されたレジンはリードフレーム１８の隙間を通って全キ
ャビティ内に充填され、所定のモールドが完成されるの
である。In the lead frame 18 having the above structure, after the tab 14 and the inner lead 12 are plated with gold or the like, the semiconductor element pellet 13 is fixed to the surface of the tab 14 by a known gold-silicon eutectic crystal or the like. In addition, a wire 15 is connected between the pellet 13 and the inner lead 12 for electrical connection. Thereafter, as shown in FIG. 6, the lead frame 18 is set in the upper and lower resin molds 24 and 25, and the tab 14, the inner lead 12, the pellet 13, and the wire 15 are placed in the cavity 26 thereof. The sealing resin 28 is pressure fed into the cavity 26 from the gate 27 formed in the lower mold 25. At this time, the gate upper surface plate portion 29 provided on the lead frame 18 is arranged at a position directly above the gate 27, and the resin discharged from the gate 27 is guided to the inside of the cavity. Further, the resin pressure-fed into the cavities is filled in the entire cavities through the gaps of the lead frame 18, and a predetermined mold is completed.
【００１３】そしてこのとき、本発明のリードフレーム
１８では、リード１１ａ、１１ｂとタブ吊りリード２１
との間の隙間２２が小さいので前記レジンがこの隙間２
２を通ってダム１９方向に流れ出ること、つまり図５Ａ
部におけるレジン洩れ（はみ出し）を少なく抑えること
ができる。これに対し、図７の本願発明に先だって考え
られたリードフレーム１８Ａでは隙間２２Ａが大きいた
め、同図Ａ部において図８に符号３０で示すレジン洩れ
が生じやすく、成形固化後にこの洩れた部位を削除しよ
うとするとパッケージ本体１０のその部分に欠けが生じ
るという不利がある。At this time, in the lead frame 18 of the present invention, the leads 11a and 11b and the tab suspension lead 21 are provided.
Since the gap 22 between the resin and the
2 toward the dam 19 direction, that is, FIG. 5A
It is possible to minimize resin leakage (protrusion) in the part. On the other hand, in the lead frame 18A considered prior to the present invention of FIG. 7, since the gap 22A is large, resin leakage shown by reference numeral 30 in FIG. There is a disadvantage in that a portion of the package body 10 is chipped when the package body 10 is deleted.
【００１４】なお、モールド封止の完了後はリードフレ
ーム１８のフレーム部２０やダム１９、更にはタブ吊り
リード２１を切り離しかつプレス加工によってアウタリ
ード１７を段上に折曲すれば前述した半導体装置を得る
ことができるのである。After the completion of the mold sealing, the frame portion 20 of the lead frame 18, the dam 19, and the tab suspension lead 21 are separated and the outer lead 17 is bent upward by press working to obtain the above-mentioned semiconductor device. You can get it.
【００１５】したがって、以上のリードフレームにて形
成した前記半導体装置では、パッケージ本体１０の面取
りされた側面部（インデックス１６部）にリード11a、11
bが設けられるのでその分リード数を増加でき装置の高
密度化、多ピン化に対応できる。また、各リードをパッ
ケージ本体の中心に対して対称に配置でき、装置や実装
用回路基板等の設計、製作や実装を行い易いものにでき
る。Therefore, in the semiconductor device formed by the above lead frame, the leads 11a, 11 are provided on the chamfered side surface portion (index 16 portion) of the package body 10.
Since b is provided, the number of leads can be increased correspondingly, and the device can be made higher in density and have more pins. Further, the leads can be arranged symmetrically with respect to the center of the package body, which makes it easy to design, manufacture, and mount the device and the mounting circuit board.
【００１６】ここで、本発明の半導体装置は図示のもの
に限定されるものではなく種々の変形例が考えられる。Here, the semiconductor device of the present invention is not limited to the one shown in the drawing, and various modifications can be considered.
【００１７】[0017]
【発明の効果】本発明の半導体装置では、リードとタブ
吊りリード２１との間の隙間が小さいので、半導体装置
の多ピン化を可能とすると共にその設計、製作、実装を
容易にすることができる。また、レジンがこの隙間２２
を通ってダム１９に流れ出ること、つまり図５Ａ部にお
けるレジン流れ（はみ出し）を少なく抑えることができ
る。In the semiconductor device of the present invention, since the gap between the lead and the tab suspension lead 21 is small, it is possible to increase the number of pins of the semiconductor device and facilitate its design, manufacture and mounting. it can. In addition, the resin is
It is possible to suppress the flow through the dam 19 to the dam 19, that is, the resin flow (protrusion) in the portion of FIG. 5A.
【００１８】[0018]
【図１】従来の半導体装置の概略平面図。FIG. 1 is a schematic plan view of a conventional semiconductor device.
【図２】本発明のリードフレームを適応した半導体装置
の斜視図。FIG. 2 is a perspective view of a semiconductor device to which the lead frame of the present invention is applied.
【図３】本発明のリードフレームを適応した半導体装置
の破断斜視図。FIG. 3 is a cutaway perspective view of a semiconductor device to which the lead frame of the present invention is applied.
【図４】本発明の実施例にしたがったリードフレームの
全体を概略的に示す平面図。FIG. 4 is a plan view schematically showing the entire lead frame according to the embodiment of the present invention.
【図５】図４に示したリードフレームの要部の拡大図。5 is an enlarged view of a main part of the lead frame shown in FIG.
【図６】本発明のリードフレームを用いたモールド状態
の断面図。FIG. 6 is a cross-sectional view of a molded state using the lead frame of the present invention.
【図７】本願発明に先だって考えられたリードフレーム
の部分拡大図。FIG. 7 is a partially enlarged view of a lead frame considered prior to the present invention.
【図８】従来のリードフレームを用いたモールド状態の
断面図。FIG. 8 is a cross-sectional view of a molded state using a conventional lead frame.
１０…パッケージ本体、１１…リード、１２…インナリ
ード、１３…ペレット、１４…タブ、１５…ワイヤ、１
６…インデックス、１７…アウタリード、１８、１８Ａ
…リードフレーム、１９…ダム、２０…フレーム部、２
２、２２Ａ…隙間、２４、２５…モールド型、２６…キ
ャビティ、２８…レジン、２９…ゲート上面板。10 ... Package body, 11 ... Lead, 12 ... Inner lead, 13 ... Pellet, 14 ... Tab, 15 ... Wire, 1
6 ... Index, 17 ... Outer lead, 18, 18A
… Lead frame, 19… Dam, 20… Frame part, 2
2, 22A ... Gap, 24, 25 ... Mold type, 26 ... Cavity, 28 ... Resin, 29 ... Gate top plate.
Claims (2)
のタブと、前記タブと一体的に形成されたタブ吊りリー
ドと、前記タブの近くから遠い方へ延びる複数本のリー
ドと、前記リードの一端近傍と前記半導体素子の電極と
を電気的に接続したワイヤと、前記タブ、前記タブ吊り
リード、前記ワイヤ及び前記リードの少なくとも一部を
レジンでモールドすることにより形成した封止体とを有
する半導体装置において、前記略方形のタブの角部から
離れてその近くから該タブの角部に対応した前記封止体
の角部近傍に向かってタブ吊りリードが設けられてな
り、前記リードのうち前記タブ吊りリードに近接配置さ
れるリードとタブ吊りリードの隙間を可及的に小さく
し、かつ前記タブ吊りリードに近接配置されるリードの
うちタブ吊りリードと前記タブの角部との間から延びる
リードが、前記タブ吊りリードが設けられるタブの一辺
に対して縦方向に延びるタブの一辺から延びる複数本の
リードとその終端が同一方向になるように設けられてな
ることを特徴とする半導体装置。1. A substantially rectangular tab to which a semiconductor element is fixed on its main surface, a tab suspension lead integrally formed with the tab, and a plurality of leads extending from near the tab to a far side. A wire electrically connecting between one end of the lead and an electrode of the semiconductor element, the tab, the tab suspension lead, and a sealing body formed by molding at least a part of the wire and the lead with a resin. In a semiconductor device having: a tab suspension lead provided away from a corner of the substantially rectangular tab toward the corner of the sealing body corresponding to the corner of the tab. Of the leads, the gap between the tab suspension lead and the tab suspension lead is made as small as possible, and the tab suspension lead among the leads disposed in the proximity of the tab suspension lead is A lead extending from between the corners of the tab is provided such that a plurality of leads extending from one side of the tab extending in the vertical direction and the ends thereof are in the same direction with respect to one side of the tab on which the tab suspension lead is provided. A semiconductor device characterized by being formed.
端の両角部から離れてその近くにそれぞれタブ吊りリー
ドが設けられてなることを特徴とする請求項第１項記載
の半導体装置。2. The semiconductor device according to claim 1, wherein one side of the substantially rectangular tab is provided with tab suspension leads respectively apart from both corners of both ends thereof. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3200257A JPH079960B2 (en) | 1991-08-09 | 1991-08-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3200257A JPH079960B2 (en) | 1991-08-09 | 1991-08-09 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57016233A Division JPS58134453A (en) | 1982-02-05 | 1982-02-05 | Lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0529527A true JPH0529527A (en) | 1993-02-05 |
| JPH079960B2 JPH079960B2 (en) | 1995-02-01 |
Family
ID=16421362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3200257A Expired - Lifetime JPH079960B2 (en) | 1991-08-09 | 1991-08-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH079960B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5952710A (en) * | 1996-10-09 | 1999-09-14 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of manufacturing same |
| WO2001078147A1 (en) * | 2000-04-05 | 2001-10-18 | Advanced Micro Devices, Inc. | Lead frame design for reduced wire sweep |
| JP2002176131A (en) * | 2000-12-08 | 2002-06-21 | Hitachi Ltd | Manufacturing method for semiconductor device |
| KR20180078965A (en) * | 2016-12-30 | 2018-07-10 | 스템코 주식회사 | Flexible printed circuit boards and method of manufacturing electronic product including the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5517382U (en) * | 1978-07-19 | 1980-02-04 | ||
| JPS5521128A (en) * | 1978-08-02 | 1980-02-15 | Hitachi Ltd | Lead frame used for semiconductor device and its assembling |
| JPS569756U (en) * | 1979-06-30 | 1981-01-27 | ||
| JPS5646265U (en) * | 1979-09-17 | 1981-04-24 |
-
1991
- 1991-08-09 JP JP3200257A patent/JPH079960B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5517382U (en) * | 1978-07-19 | 1980-02-04 | ||
| JPS5521128A (en) * | 1978-08-02 | 1980-02-15 | Hitachi Ltd | Lead frame used for semiconductor device and its assembling |
| JPS569756U (en) * | 1979-06-30 | 1981-01-27 | ||
| JPS5646265U (en) * | 1979-09-17 | 1981-04-24 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5952710A (en) * | 1996-10-09 | 1999-09-14 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of manufacturing same |
| WO2001078147A1 (en) * | 2000-04-05 | 2001-10-18 | Advanced Micro Devices, Inc. | Lead frame design for reduced wire sweep |
| JP2002176131A (en) * | 2000-12-08 | 2002-06-21 | Hitachi Ltd | Manufacturing method for semiconductor device |
| KR20180078965A (en) * | 2016-12-30 | 2018-07-10 | 스템코 주식회사 | Flexible printed circuit boards and method of manufacturing electronic product including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH079960B2 (en) | 1995-02-01 |
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