JPS6351542B2 - - Google Patents

Info

Publication number
JPS6351542B2
JPS6351542B2 JP57016232A JP1623282A JPS6351542B2 JP S6351542 B2 JPS6351542 B2 JP S6351542B2 JP 57016232 A JP57016232 A JP 57016232A JP 1623282 A JP1623282 A JP 1623282A JP S6351542 B2 JPS6351542 B2 JP S6351542B2
Authority
JP
Japan
Prior art keywords
lead
tab
semiconductor device
package body
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57016232A
Other languages
Japanese (ja)
Other versions
JPS58134452A (en
Inventor
Masachika Masuda
Hajime Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP57016232A priority Critical patent/JPS58134452A/en
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to DE3303165A priority patent/DE3303165C2/en
Priority to GB08302730A priority patent/GB2115220B/en
Priority to IT19414/83A priority patent/IT1161869B/en
Priority to KR1019830000433A priority patent/KR900001989B1/en
Publication of JPS58134452A publication Critical patent/JPS58134452A/en
Priority to SG362/87A priority patent/SG36287G/en
Priority to HK707/87A priority patent/HK70787A/en
Priority to MY616/87A priority patent/MY8700616A/en
Publication of JPS6351542B2 publication Critical patent/JPS6351542B2/ja
Priority to KR1019900000785A priority patent/KR900001988B1/en
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明はフラツトパツケージ型の半導体装置に
関し、特に多ピン化を図つた半導体装置およびそ
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flat package type semiconductor device, and particularly to a semiconductor device with a large number of pins and a method for manufacturing the same.

一般にフラツトパツケージ型の半導体装置はデ
ユアルインライン型のパツケージに比較して薄型
化および多ピン化が容易であり、しかも実装用回
路基板（プリント基板）への実装はチツプキヤリ
アパツケージと略同程度の実装作業でよいという
利点からその需要は増大している。この種の半導
体装置は通常金属薄板を打抜成形して得られたリ
ードフレームに半導体素子ペレツトを固着しかつ
リードとの間に電気的接続を行なつた上で、ペレ
ツトやリードとの接続部を方形（正方形、長方
形）でかつ薄肉のパツケージ形状にプラスチツク
封止した構成としている。そして、このようにパ
ツケージの平面形状を方形にしたときには、第１
図に示すようにパツケージ本体１の一角度を面取
り形成し、この面取り部２を複数本のピン（リー
ド）３のインデツクスとして利用しているのであ
る。 In general, flat package type semiconductor devices can be made thinner and have more pins than dual-in-line type packages, and mounting on a mounting circuit board (printed circuit board) is approximately the same as that of a chip carrier package. Its demand is increasing due to the advantage that it only requires implementation work. This type of semiconductor device usually involves fixing semiconductor element pellets to a lead frame obtained by stamping and forming a thin metal plate, making electrical connections with the leads, and then attaching the connecting parts between the pellets and the leads. It has a square (square, rectangular) and thin-walled package shape and is sealed with plastic. When the planar shape of the package is made rectangular in this way, the first
As shown in the figure, one angle of the package body 1 is chamfered, and this chamfered portion 2 is used as an index for a plurality of pins (leads) 3.

ところで、近年の半導体装置は増々高密度化さ
れかつ多ピン化される傾向にある。この反面、設
計、製作あるいは実装上の理由からパツケージの
本体形状や寸法を一定に保つことが要求されるこ
とがある。したがつて、このような場合はリード
ピツチを可及的に小さくしかつパツケージ本体１
の四周側長を最大に利用してピン３を配設するこ
とにより多ピン化に対応せざるを得ない。 Incidentally, semiconductor devices in recent years tend to be increasingly denser and have more pins. On the other hand, for design, manufacturing, or mounting reasons, it is sometimes required to keep the shape and dimensions of the package body constant. Therefore, in such cases, the lead pitch should be made as small as possible and the package body 1 should be
By arranging the pins 3 by maximizing the length of the four circumferences, it is necessary to cope with the increase in the number of pins.

しかしながら、前記従来の半導体装置では、イ
ンデツクスとしての面取り部２を設けたことによ
りこの部分にはピン３を設けておらず、このため
パツケージ本体の四周側の利用度が低下されて多
ピン化の障害になつている。また、面取り部２に
ピンを配設していないため、特に面取り部２に接
する周側面１ａと１ｂにおいては、ピンをパツケ
ージ本体１の中心０に対して対称に配列できず、
これにより設計、製作や実装において不利が生ず
ることがある。更に詳細は後述するが、面取り部
２にピンを設けないことからこれに対応するリー
ドフレームの相当部位には当然リードを設けてお
らず、これがためプラスチツクのモールド成形時
にプラスチツクの洩れが生じて外観の低下やパツ
ケージの欠けを誘発し、商品価値を低下させると
いう問題もある。 However, in the conventional semiconductor device, since the chamfered portion 2 is provided as an index, the pin 3 is not provided in this portion, which reduces the utilization of the four circumferential sides of the package body and makes it difficult to increase the number of pins. It's becoming a hindrance. In addition, since no pins are provided on the chamfered portion 2, the pins cannot be arranged symmetrically with respect to the center 0 of the package body 1, especially on the peripheral surfaces 1a and 1b that contact the chamfered portion 2.
This may result in disadvantages in design, fabrication, and implementation. Further details will be described later, but since no pin is provided on the chamfered portion 2, the corresponding portion of the lead frame is naturally not provided with a lead, and this results in leakage of plastic during plastic molding, resulting in poor appearance. There is also the problem that it induces a decrease in the quality of the product and chipping of the package, which reduces the product value.

したがつて本発明の目的は、全体を方形にしか
つその一つの角部にインデツクスを有するパツケ
ージ本体の四周囲側面に配設するピンの一部を前
記インデツクス部位にも配設することにより、多
ピン化を図ると共にピンの対称配置を可能にして
従来の不利を解消し、かつプラスチツクの成形時
の洩れを防止して商品価値の低下防止を図ること
ができる半導体装置を提供することにある。 Therefore, an object of the present invention is to provide a package main body which is rectangular as a whole and has an index at one corner thereof, and by disposing some of the pins disposed on the four peripheral sides of the package body also in the index portion. To provide a semiconductor device which eliminates the disadvantages of the conventional device by making it possible to form pins and to arrange the pins symmetrically, and which prevents leakage during plastic molding and prevents a decrease in commercial value.

本発明の第１の要旨は、偏平でかつ全体を略方
形にしたパツケージ本体の四周囲側面から複数個
のリードを突設してなるフラツトパツケージ型の
半導体装置において、前記パツケージ本体の角部
に面取り部（インデツクス）を設け、前記リード
の一部を前記面取り部に突設したことを特徴とす
る半導体装置にある。 A first aspect of the present invention is to provide a flat package type semiconductor device in which a plurality of leads are provided protruding from the four peripheral sides of a flat, generally rectangular package body. The semiconductor device is characterized in that a chamfered portion (index) is provided on the semiconductor device, and a portion of the lead is provided to protrude from the chamfered portion.

本発明の第２の要旨は、その内部に半導体素子
ペレツトを固着するタブと、前記タブを吊るため
のタブ吊りリードを有し、その外観が偏平でかつ
全体を略方形にしたパツケージ本体の四周囲側面
から複数個のリードを突設してなるフラツトパツ
ケージ型の半導体装置において、前記パツケージ
本体の角部に面取り部を設け、前記リードの一部
を前記面取り部に突設し、前記タブ吊りリードの
一端が前記面取り部近傍に延在していることを特
徴とする半導体装置にある。 A second aspect of the present invention is that the package body has a flat outer appearance and a generally rectangular shape, and has a tab for fixing a semiconductor chip pellet therein, and a tab hanging lead for hanging the tab. In a flat package type semiconductor device having a plurality of leads protruding from a peripheral side surface, a chamfered portion is provided at a corner of the package body, a portion of the lead is protruded from the chamfered portion, and the tab The semiconductor device is characterized in that one end of the hanging lead extends near the chamfered portion.

本発明の第３の要旨は、その中央にタブを設
け、前記タブの周辺に複数本のリードを設け、前
記タブを吊るタブ吊りリードを有するリードフレ
ームを準備し、前記タブ、前記リードの一部及び
前記タブ吊りリードの少なくとも一部をレジンモ
ールドすることにより、その角部に面取り部を有
するフラツトパツケージ本体を形成する半導体装
置の製造方法において、前記面取り部より前記リ
ードの一部が突設され、かつ、前記タブ吊りリー
ドの一端が前記面取り部近傍に延在するように前
記レジンモールドする工程を有することを特徴と
する半導体装置の製造方法にある。 A third aspect of the present invention is to provide a lead frame with a tab at the center, a plurality of leads around the tab, a tab hanging lead for hanging the tab, and one of the tabs and the leads. In the method of manufacturing a semiconductor device, a flat package body having a chamfered part at a corner thereof is formed by resin molding at least a part of the tab suspension lead and a part of the lead protrudes from the chamfered part. The method for manufacturing a semiconductor device is characterized by comprising the step of resin-molding the tab suspension lead so that one end of the tab suspension lead extends near the chamfered portion.

以下、本発明を図示の実施例により説明する。 Hereinafter, the present invention will be explained with reference to illustrated embodiments.

第２図は本発明の半導体装置の全体斜視図、第
３図はその一部破断図であり、１０はパツケージ
本体、１１はこのパツケージ本体１０の四周囲側
面に突設したリード（ピン）である。前記パツケ
ージ本体１０はレジン（プラスチツク）材をモー
ルド成形する等して全体を偏平にかつその平面形
状を長方形等の方形に形成しており、前記リード
１１の内端部、即ちインナリード１２や半導体素
子ペレツト１３を内装封止している。半導体素子
ペレツト１３は略正方形のタブ１４上面に固着
し、その電極パツドと前記各リード１１のインナ
リード１２とをワイヤ１５にて接続している。ま
た前記パツケージ本体１０は一角部を面取りした
形状としてこれをインデツクス１６として構成し
ている。一方、前記リード１１は夫々等しいピツ
チにてパツケージ本体１０の四周囲側面に並設し
かつそのアウタリード１７を四周外方に向けて突
設している。この場合、アウタリード１７は段状
に折曲し、図外の実装用プリント基板上にパツケ
ージ本体１０を載置したときにアウタリード１７
先端部がプリント基板の配線に接触できるように
している。また、このリード１７はパツケージ本
体１０の中心位置に対して対称形となるように配
設すると共にパツケージ本体１０の四周囲を最大
限に有効利用するように配設しており、したがつ
て前記リード１１の一部、本例ではリード１１ａ
と１１ｂは前記パツケージ本体１０の面取りの部
位、つまりインデツクス１６面に配設し、この面
から各アウタリード１７ａ，１７ｂを夫々直角方
向に突設させている。 FIG. 2 is an overall perspective view of the semiconductor device of the present invention, and FIG. 3 is a partially cutaway view thereof. Reference numeral 10 indicates a package body, and 11 indicates leads (pins) protruding from the four peripheral sides of the package body 10. be. The package main body 10 is made flat as a whole by molding a resin (plastic) material and has a rectangular planar shape such as a rectangle. The element pellet 13 is internally sealed. The semiconductor element pellet 13 is fixed on the upper surface of a substantially square tab 14, and its electrode pad and the inner lead 12 of each lead 11 are connected by wires 15. The package body 10 has one corner chamfered to form an index 16. On the other hand, the leads 11 are arranged at equal pitches on the four circumferential side surfaces of the package body 10, and their outer leads 17 are provided to protrude outward on the four circumferences. In this case, the outer leads 17 are bent in a stepped manner, and when the package body 10 is placed on a mounting printed circuit board (not shown), the outer leads 17
The tip can come into contact with the wiring on the printed circuit board. Further, the leads 17 are arranged symmetrically with respect to the center position of the package body 10, and are arranged so as to make maximum effective use of the four peripheries of the package body 10. A part of the lead 11, in this example, the lead 11a
and 11b are arranged on the chamfered portion of the package body 10, that is, on the index 16 surface, and the outer leads 17a and 17b are respectively projected from this surface in a right angle direction.

次に以上の構成の半導体装置の製造方法を説明
する。 Next, a method of manufacturing the semiconductor device having the above configuration will be explained.

先ず第４図に示すように42アロイ等の金属薄板
を打抜成形してリードフレーム１８を形成する。
このリードフレーム１８は本例では５個のパツケ
ージに相当するリード等を連設した多連フレーム
として構成しており、各パツケージ相当分は中央
に形成した方形のタブ１４の周囲に複数本のリー
ド１１の各インナリード１２を第５図に合わせて
示すように放射状に配設すると共に、各リード１
１は枠状のダム１９により一体に連結しかつ各リ
ード１１のアウタリード１７は等ピツチ間隔で四
周囲方向に延設してフレーム部２０に連結してい
る。また、前記タブ１４はその四角部にタブ吊り
リード２１を設け、このタブ吊りリード２１を前
記ダム１９に連結することによりタブ１４をフレ
ーム部２０に支持している。２３はガイド孔であ
る。この場合、本発明では前記インデツクス１６
に配設するリード１１ａ，１１ｂは前記タブ吊り
リード２１に近接配置されリード１１ａ，１１ｂ
とタブ吊りリード２１との間の隙間２２を可及的
に小さくしている。因みに第７図に示す従来のリ
ードフレーム１８Ａはリード１１ａ，１１ｂが存
在していないため、タブ吊りリード２１と隣接す
るリード１１との間の隙間２２Ａが大きなものと
なつている。 First, as shown in FIG. 4, a lead frame 18 is formed by stamping a thin metal plate such as 42 alloy.
In this example, the lead frame 18 is configured as a multi-frame frame in which leads etc. corresponding to five package cages are arranged in series, and each package cage is composed of a plurality of leads arranged around a rectangular tab 14 formed in the center. The 11 inner leads 12 are arranged radially as shown in FIG.
1 are integrally connected by a frame-shaped dam 19, and the outer leads 17 of each lead 11 extend in the circumferential direction at equal pitch intervals and are connected to the frame portion 20. Further, the tab 14 is provided with a tab suspension lead 21 in its square portion, and the tab 14 is supported on the frame portion 20 by connecting the tab suspension lead 21 to the dam 19. 23 is a guide hole. In this case, in the present invention, the index 16
The leads 11a and 11b are arranged close to the tab suspension lead 21.
The gap 22 between the tab suspension lead 21 and the tab suspension lead 21 is made as small as possible. Incidentally, since the conventional lead frame 18A shown in FIG. 7 does not have the leads 11a and 11b, the gap 22A between the tab suspension lead 21 and the adjacent lead 11 is large.

次いで、前記リードフレーム１８のタブ１４や
インナリード１２には金等のめつきを施した後、
タブ１４表面には半導体素子ペレツト１３を公知
の金シリコン共晶等により固着しかつペレツト１
３とインナリード１２間にワイヤ１５を接続して
電気的接続を行なう。しかる後、第６図に示すよ
うに、リードフレーム１８を上下のレジンモール
ド型２４，２５内にセツトしてそのキヤビテイ２
６内にタブ１４、インナリード１２、ペレツト１
３、ワイヤ１５を配置し、下モールド型２５に形
成したゲート２７から封止用レジン２８をキヤビ
テイ２６内に圧送する。このとき、リードフレー
ム１８の一隅部に設けたゲート上面板部２９（２
９Ａ）をゲート２７の直上位置に配置し、ゲート
２７から吐出されたレジンを奥方へ誘導させる。
また、キヤビテイ内へ圧送されたレジンは、リー
ドフレーム１８の隙間を通つて全キヤビテイ内に
充填される。したがつて、前記した本発明に係る
リードフレームでは、リード１１ａ，１１ｂとタ
ブ吊りリード２１との間の隙間が小さいので第５
図Ａ部におけるレジンの洩れ（はみ出し）を少な
く抑えることができる。これに対し、第７図に示
した従来のリードフレーム１８Ａでは隙間２２Ａ
が大きいため、同図Ａ部において第８図に示すよ
うにレジン洩れ３０が生じ易く、成形固化後にこ
の洩れ部を削除しようとするとパツケージ本体１
０の欠けを招くという不利がある。 Next, after plating the tabs 14 and inner leads 12 of the lead frame 18 with gold or the like,
A semiconductor element pellet 13 is fixed to the surface of the tab 14 using a known gold-silicon eutectic or the like.
A wire 15 is connected between the wire 3 and the inner lead 12 to establish an electrical connection. After that, as shown in FIG. 6, the lead frame 18 is set in the upper and lower resin molds 24 and 25, and the cavity 2 is closed.
Tab 14, inner lead 12, pellet 1 inside 6
3. The wire 15 is placed, and the sealing resin 28 is pumped into the cavity 26 from the gate 27 formed in the lower mold 25. At this time, the gate top plate portion 29 (2
9A) is placed directly above the gate 27, and the resin discharged from the gate 27 is guided to the back.
Further, the resin force-fed into the cavity passes through the gap in the lead frame 18 and fills all the cavities. Therefore, in the lead frame according to the present invention described above, since the gap between the leads 11a, 11b and the tab suspension lead 21 is small, the fifth
Leakage (protrusion) of the resin in the part A in the figure can be suppressed to a minimum. On the other hand, in the conventional lead frame 18A shown in FIG.
Because of this, resin leakage 30 is likely to occur in part A of the same figure as shown in FIG.
This has the disadvantage of causing missing 0's.

以上のようにしてモールド封止を完成すれば、
後はリードフレーム１８のフレーム部２０やダム
１９、更にはタブ吊りリード２１を切離しかつプ
レス加工によつてアウタリード１７を段状に折曲
すれば前述した半導体装置を得ることができるの
である。 Once the mold sealing is completed as described above,
After that, the above-described semiconductor device can be obtained by cutting off the frame portion 20 of the lead frame 18, the dam 19, and further the tab suspension lead 21, and bending the outer lead 17 into steps by pressing.

したがつて、前述した本例の半導体装置によれ
ば、パツケージ本体１０には一部を面取り形成し
たインデツクス１６を設けているので、従来と同
様にリード１１の認識を行なうことができるのは
勿論のこと、このインデツクス１６にもリード１
１ａ，１１ｂを配設しているのでその分リード数
の増加を図り高密度化、多ピン化に対応できる。
また、インデツクスへのリードの配設によつてリ
ードをパツケージ本体の中心に対して対称に配設
することが可能になり、これにより半導体装置や
実装用回路基板等の設計、製作や実装を行ない易
いものにできる。 Therefore, according to the semiconductor device of this example described above, since the package body 10 is provided with the index 16 which is partially chamfered, the leads 11 can of course be recognized in the same way as in the conventional case. Also, this index 16 also has lead 1.
1a and 11b, the number of leads can be increased correspondingly, making it possible to cope with higher density and increased number of pins.
In addition, by placing the leads in the index, it becomes possible to arrange the leads symmetrically with respect to the center of the package body, which makes it possible to design, manufacture, and mount semiconductor devices and circuit boards for mounting. It can be made easy.

また、本発明方法によれば、形成されるパツケ
ージ本体のインデツクス相当部位にリードを配設
したリードフレームを用いてペレツト付、ワイヤ
接続およびレジンモールドを行なつているので、
レジンモールドの洩れを抑制してレジンのはみ出
しおよびこれに伴なう欠け等を防止して商品価値
の高い半導体装置を製造することができる。 Furthermore, according to the method of the present invention, pellet attachment, wire connection, and resin molding are carried out using a lead frame in which leads are arranged at the portion corresponding to the index of the package body to be formed.
Semiconductor devices with high commercial value can be manufactured by suppressing leakage of the resin mold and preventing the resin from extruding and the resulting chipping.

ここで、図示した半導体装置やリードフレーム
の構成は一例にすぎず、種々の変形例が考えられ
ることは言うまでもない。 Here, the configurations of the semiconductor device and lead frame illustrated are merely examples, and it goes without saying that various modifications can be considered.

以上のように本発明の半導体装置によれば、パ
ツケージ本体のインデツクス部位にもリードを配
設しているので半導体装置の高密度化や多ピン化
に有効になると共に、リードの対称配列を可能に
して設計、製作、実装の容易化を図ることができ
る。また本発明の製造方法によれば、隙間の小さ
いリードフレームを用いているのでレジンのはみ
出しを抑止でき、これにより欠け等を防止して外
観の向上および商品価値の向上を達成できるとい
う効果を奏する。 As described above, according to the semiconductor device of the present invention, the leads are also provided at the index portion of the package body, which is effective for increasing the density and increasing the number of pins in the semiconductor device, and also enables a symmetrical arrangement of the leads. This makes it easier to design, manufacture, and implement. Further, according to the manufacturing method of the present invention, since a lead frame with a small gap is used, it is possible to prevent the resin from protruding, thereby preventing chipping, etc., and improving the appearance and product value. .

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置の概略平面図、第２
図は本発明の一実施例に従つた半導体装置の斜視
図、第３図は第２図で示した半導体装置の一部を
破断した図、第４図は本発明に従つた半導体装置
を製造するために用いられるリードフレームの全
体概略平面図、第５図は第４図で示したリードフ
レームの要部拡大図、第６図は上記第５図に示し
たリードフレームをモールドする時のモールド状
態の断面図、第７図は第５図に対応する従来リー
ドフレームの部分拡大図、第８図は従来のモール
ド状態の断面図である。 １０……パツケージ本体、１１……リード、１
２……インナリード、１３……ペレツト、１４…
…タブ、１５……ワイヤ、１６……インデツク
ス、１７……アウタリード、１８，１８Ａ……リ
ードフレーム、２２，２２Ａ……隙間、２４，２
５……モールド型、２６……キヤビテイ、２７…
…ゲート、２８……レジン、２９，２９Ａ……ゲ
ート上面板、３０……はみ出し。 Figure 1 is a schematic plan view of a conventional semiconductor device, Figure 2 is a schematic plan view of a conventional semiconductor device;
The figure is a perspective view of a semiconductor device according to an embodiment of the present invention, FIG. 3 is a partially cutaway view of the semiconductor device shown in FIG. 2, and FIG. 4 is a manufactured semiconductor device according to the present invention. FIG. 5 is an enlarged view of the main parts of the lead frame shown in FIG. 4, and FIG. 6 is a mold for molding the lead frame shown in FIG. 5 above. 7 is a partially enlarged view of a conventional lead frame corresponding to FIG. 5, and FIG. 8 is a sectional view of a conventional molded state. 10...Package body, 11...Lead, 1
2...Inner lead, 13...Pellet, 14...
...Tab, 15...Wire, 16...Index, 17...Outer lead, 18,18A...Lead frame, 22,22A...Gap, 24,2
5...Mold type, 26...Cavity, 27...
...Gate, 28...Resin, 29, 29A...Gate top plate, 30...Protrusion.

Claims (1)

【特許請求の範囲】 １ 偏平でかつ全体を略方形にしたパツケージ本
体の四周囲側面から複数個のリードを突設してな
るフラツトパツケージ型の半導体装置において、
前記パツケージ本体の角部に面取り部を設け、前
記リードの一部を前記面取り部に突設したことを
特徴とする半導体装置。 ２ 前記リードを前記パツケージ本体の中心に対
して対称となるように配設したことを特徴とする
特許請求の範囲第１項記載の半導体装置。 ３ その内部に半導体素子ペレツトを固着するタ
ブと、前記タブを吊るためのタブ吊りリードを有
し、その外観が偏平でかつ全体を略方形にしたパ
ツケージ本体の四周囲側面から複数個のリードを
突設してなるフラツトパツケージ型の半導体装置
において、前記パツケージ本体の角部に面取り部
を設け、前記リードの一部を前記面取り部に突設
し、前記タブ吊りリードの一端が前記面取り部近
傍に延在していることを特徴とする半導体装置。 ４ 前記リードを前記パツケージ本体の中心に対
して対称となるように配設したことを特徴とする
特許請求の範囲第３項記載の半導体装置。 ５ その中央にタブを設け、前記タブの周辺に複
数本のリードを設け、前記タブを吊るタブ吊りリ
ードを有するリードフレームを準備し、前記タ
ブ、前記リードの一部及び前記タブ吊りリードの
少なくとも一部をレジンモールドすることによ
り、その角部に面取り部を有するフラツトパツケ
ージ本体を形成する半導体装置の製造方法におい
て、前記面取り部より前記リードの一部が突設さ
れ、かつ、前記タブ吊りリードの一端が前記面取
り部近傍に延在するように前記レジンモールドす
る工程を有することを特徴とする半導体装置の製
造方法。[Scope of Claims] 1. A flat package type semiconductor device in which a plurality of leads are provided protruding from the four peripheral sides of a flat package body having a generally rectangular shape,
A semiconductor device characterized in that a chamfer is provided at a corner of the package body, and a part of the lead is provided protruding from the chamfer. 2. The semiconductor device according to claim 1, wherein the leads are arranged symmetrically with respect to the center of the package body. 3. The package body has a tab for fixing a semiconductor chip pellet therein and a tab suspension lead for hanging the tab, and a plurality of leads are inserted from the four peripheral sides of the package body, which has a flat appearance and is generally rectangular in appearance. In a flat package type semiconductor device having a protruding part, a chamfered part is provided at a corner of the package body, a part of the lead is protruded from the chamfered part, and one end of the tab hanging lead is provided in the chamfered part. A semiconductor device characterized by extending in the vicinity. 4. The semiconductor device according to claim 3, wherein the leads are arranged symmetrically with respect to the center of the package body. 5. A lead frame is provided with a tab in the center thereof, a plurality of leads are provided around the tab, a tab hanging lead for hanging the tab is prepared, and at least one of the tab, a part of the lead, and the tab hanging lead is provided. In a method for manufacturing a semiconductor device in which a flat package body having a chamfered portion at a corner thereof is formed by resin molding a portion thereof, a portion of the lead protrudes from the chamfered portion and the tab hanger is provided. A method of manufacturing a semiconductor device, comprising the step of resin molding so that one end of the lead extends near the chamfer.
JP57016232A 1982-02-05 1982-02-05 Semiconductor device and manufacture thereof Granted JPS58134452A (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP57016232A JPS58134452A (en) 1982-02-05 1982-02-05 Semiconductor device and manufacture thereof
DE3303165A DE3303165C2 (en) 1982-02-05 1983-01-31 Semiconductor device with housing body and connecting conductors
GB08302730A GB2115220B (en) 1982-02-05 1983-02-01 Semiconductor device and method of producing the same
IT19414/83A IT1161869B (en) 1982-02-05 1983-02-03 SEMICONDUCTOR DEVICE AND PROCEDURE FOR ITS MANUFACTURE
KR1019830000433A KR900001989B1 (en) 1982-02-05 1983-02-04 Semiconductor device
SG362/87A SG36287G (en) 1982-02-05 1987-04-23 Semiconductor device and method of producing the same
HK707/87A HK70787A (en) 1982-02-05 1987-10-01 Semiconductor device and method of producing the same
MY616/87A MY8700616A (en) 1982-02-05 1987-12-30 Semiconductor device and method of producing the same
KR1019900000785A KR900001988B1 (en) 1982-02-05 1990-01-24 Leadframe for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57016232A JPS58134452A (en) 1982-02-05 1982-02-05 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS58134452A JPS58134452A (en) 1983-08-10
JPS6351542B2 true JPS6351542B2 (en) 1988-10-14

Family

ID=11910801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57016232A Granted JPS58134452A (en) 1982-02-05 1982-02-05 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS58134452A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0464982U (en) * 1990-10-12 1992-06-04
JPH08502389A (en) * 1992-10-13 1996-03-12 オリン コーポレイション Metal electronic package with reduced seal width

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0464982U (en) * 1990-10-12 1992-06-04
JPH08502389A (en) * 1992-10-13 1996-03-12 オリン コーポレイション Metal electronic package with reduced seal width

Also Published As

Publication number Publication date
JPS58134452A (en) 1983-08-10

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