JPH0526350B2 - - Google Patents
Info
- Publication number
- JPH0526350B2 JPH0526350B2 JP59227320A JP22732084A JPH0526350B2 JP H0526350 B2 JPH0526350 B2 JP H0526350B2 JP 59227320 A JP59227320 A JP 59227320A JP 22732084 A JP22732084 A JP 22732084A JP H0526350 B2 JPH0526350 B2 JP H0526350B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- boron
- phosphorus
- oxide film
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 19
- 229910052796 boron Inorganic materials 0.000 claims description 19
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 17
- 229910052698 phosphorus Inorganic materials 0.000 claims description 17
- 239000011574 phosphorus Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 17
- 238000009792 diffusion process Methods 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 239000001257 hydrogen Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し特にシリコンゲート
型電界効果半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a silicon gate field effect semiconductor device.
多結晶シリコンを用いる電界効果トランジスタ
（以下MOSと称す）は通称シリコンゲートMOS
として知られており、この多結晶シリコンは特別
な場合を除き不純物を含まない絶縁体であり、必
要に応じて不純物としてリン、ボロンさらにはヒ
素、ガリウムなどが拡散もしくはドーピングなど
の技術により、又はイオン注入技術等により多結
晶シリコン中に添加され導電体として使用され
る。一般にこの不純物の選択としてＮチヤンネル
シリコンゲートMOSにはリンが、そしてＰチヤ
ンネルシリコンゲートにはボロンが常識であり、
ほとんどの場合がシリコン基板への不純物拡散の
時に同時に多結晶シリコン中へ拡散される。 Field effect transistors (hereinafter referred to as MOS) using polycrystalline silicon are commonly known as silicon gate MOS
This polycrystalline silicon is an insulator that does not contain impurities except in special cases, and if necessary, impurities such as phosphorus, boron, arsenic, gallium, etc. can be added by diffusion or doping techniques, or It is added to polycrystalline silicon using ion implantation technology and used as a conductor. In general, it is common knowledge that phosphorus is selected as this impurity for N-channel silicon gate MOS, and boron is selected for P-channel silicon gate.
In most cases, when impurities are diffused into a silicon substrate, they are simultaneously diffused into polycrystalline silicon.
本発明の目的は特性の安定な半導体装置とくに
安定なシリコンゲートMOSを提供することであ
る。 An object of the present invention is to provide a semiconductor device with stable characteristics, particularly a stable silicon gate MOS.
本発明はゲート絶縁膜に二種類の不純物、特に
ボロン及びリンが同時に含まれた時の各不純物の
挙動についてゲート絶縁膜としてシリコン酸化膜
を用いた場合の新たな実験結果にもとづくもので
ある。 The present invention is based on new experimental results regarding the behavior of two types of impurities, especially boron and phosphorus, simultaneously contained in the gate insulating film when a silicon oxide film is used as the gate insulating film.
ＰチヤンネルシリコンゲートMOSを例にとる
と水素を含む雰囲気、スチームを含む雰囲気でそ
れぞれ熱処理するとMOSトランジスターのスレ
ツシユホールド電圧VTが第１図ａ，ｂに示す如
く、負に大きくなる現像が生じる。第１図におい
てVTOはVTの初期値、ｔは熱処理時間を示す。こ
の現像は多結晶シリコン中に添加されている不純
物のボロンがシリコン酸化膜中に熱的に拡散しこ
れを水素により加速されるためである。一方Ｎチ
ヤンネルシリコンゲートMOSを例にとるとＰチ
ヤンネルシリコンゲートMOSに比べてはるかに
安定であり熱処理中のMOSトランジスターのス
レツシユホールド電圧の変化は見られない。これ
を第２図に示す。一般にシリコン酸化膜にボロン
が入るとガラス層をつくるがボロンの存在により
シリコン酸化膜は結晶化し易くなり膜密度が疎に
なり、一方リンを含んだシリコン酸化膜はより無
定形になり膜密度が密になり上記現像もその効果
として理解できる。 Taking a P-channel silicon gate MOS as an example, when it is heat-treated in an atmosphere containing hydrogen and an atmosphere containing steam, the threshold voltage V T of the MOS transistor becomes negative as shown in Figure 1a and b. . In FIG. 1, V TO represents the initial value of V T and t represents the heat treatment time. This development occurs because boron, an impurity added to polycrystalline silicon, thermally diffuses into the silicon oxide film and is accelerated by hydrogen. On the other hand, taking an N-channel silicon gate MOS as an example, it is much more stable than a P-channel silicon gate MOS, and no change in the threshold voltage of the MOS transistor is observed during heat treatment. This is shown in FIG. Generally, when boron enters a silicon oxide film, it forms a glass layer, but the presence of boron makes the silicon oxide film easier to crystallize and the film density becomes sparse.On the other hand, a silicon oxide film containing phosphorus becomes more amorphous and has a lower film density. The above-mentioned development can be understood as an effect of the increased density.
そこでボロンが拡散されたシリコン酸化膜にリ
ンを拡散したらどうなるかを第３図に示す。図に
おいて、t′，t″，ｔはリン拡散の開始時間を示
し、a′，a″，ａはそれに対応したVTをそれぞ
れ示す。即ちリン拡散時を境として、その前でＰ
チヤンネルシリコンゲートMOSの不安定さそし
てその後でＮチヤンネルシリコンゲートMOSの
安定さが備つている。これは前記した様に一度ボ
ロンにより疎になつてシリコン酸化膜がリンによ
り再び密に変つたと考えて理解される。本発明は
第３図に示したこの新たな現像を半導体装置に適
用したものである。 FIG. 3 shows what happens when phosphorus is diffused into a silicon oxide film in which boron has been diffused. In the figure, t', t'', and t indicate the start time of phosphorus diffusion, and a', a'', and a indicate the corresponding V T , respectively. In other words, after the time of phosphorus diffusion, P
It has the instability of a channel silicon gate MOS and then the stability of an N channel silicon gate MOS. This can be understood by considering that the silicon oxide film, which was once made sparse by boron, becomes dense again by phosphorus, as described above. The present invention applies this new development shown in FIG. 3 to a semiconductor device.
ＰチヤンネルシリコンゲートMOSを例にとる
と多結晶シリコンゲートにはソース及びドレイン
への拡散と同時にボロンが添加される。その後シ
リコンゲートMOSの特徴である多層配線技術を
生かすために多結晶シリコンと他の配線電極との
分離のため多結晶シリコン上に絶縁被膜を形成し
なければならない。このため熱酸化を行うとボロ
ンが多結晶シリコンよりシリコン酸化膜へ侵入し
酸化膜質を劣化せしめ電荷トラツプをつくり高温
バイアス処理での不安定さを助長し、ついには
MOSトランジスターのスレツシユホールド電圧
の値を変化させてしまう事が知られている。この
効果は水素を含む雰囲気で行うとより顕著にあら
われる。そこで現実には多結晶シリコンとシリコ
ン酸化膜との間にシリコン窒化膜などのボロンの
不透明な膜をはさみ込んだり低温で気相成長法で
の絶縁被膜の成長を行うなどしている。 Taking a P-channel silicon gate MOS as an example, boron is added to the polycrystalline silicon gate at the same time as it is diffused into the source and drain. After that, in order to take advantage of the multilayer wiring technology that is a feature of silicon gate MOS, an insulating film must be formed on the polycrystalline silicon to separate the polycrystalline silicon from other wiring electrodes. For this reason, when thermal oxidation is performed, boron invades the silicon oxide film from polycrystalline silicon, deteriorates the oxide film quality, creates charge traps, and promotes instability in high temperature bias processing, and finally
It is known that the value of the threshold voltage of a MOS transistor can be changed. This effect becomes more pronounced when the process is carried out in an atmosphere containing hydrogen. In practice, therefore, an opaque boron film such as a silicon nitride film is sandwiched between polycrystalline silicon and a silicon oxide film, or an insulating film is grown by vapor phase growth at low temperatures.
多結晶シリコンへのボロン拡散前の工程、例え
ば多結晶シリコン成長中もしくは成長直後にドー
ピング技術や拡散技術でリンを多結晶シリコン中
に添加しその後上記通りのボロン拡散を行うと前
もつて添加してあるリンがシリコン酸化膜を密な
構造にすることもできるのでその後の酸化工程で
のボロンのシリコン酸化膜への侵入が抑制され
る。したがつて前述したＰチヤンネルシリコンゲ
ートMOSの不安定さが克服される。多結晶中に
添加するリン濃度は1019／cm3程度が効果的である
が酸化工程の温度を低くおさえるとこれ以下のリ
ン濃度でも効果はみとめられる。ここで酸化工程
の温度を低くできるのも多結晶シリコンへのリン
の添加の効果でもある。 In the step before boron diffusion into polycrystalline silicon, for example, during or immediately after polycrystalline silicon growth, phosphorous is added to polycrystalline silicon by doping technology or diffusion technology, and then boron diffusion as described above is performed, the previously added. Since the phosphorus present in the silicon oxide film can form a dense structure in the silicon oxide film, boron is prevented from penetrating into the silicon oxide film in the subsequent oxidation process. Therefore, the instability of the P-channel silicon gate MOS mentioned above is overcome. It is effective to add phosphorus to the polycrystal at a concentration of about 10 19 /cm 3 , but if the temperature of the oxidation step is kept low, the effect can be seen even at a phosphorus concentration lower than this. It is also an effect of adding phosphorus to polycrystalline silicon that the temperature of the oxidation step can be lowered.
この様にボロンが熱処理でシリコン酸化膜を突
き抜けるとMOSトランジスターのスレツシユホ
ールド電圧が変化する。この現象を利用して
MOSトランジスターのスレツシユホールド電圧
制御が可能である事が知られている。しかしボロ
ン添加だけでは前述したMOSトランジスターの
不安定性のため実用化が困難である。 In this way, when boron penetrates the silicon oxide film through heat treatment, the threshold voltage of the MOS transistor changes. Taking advantage of this phenomenon
It is known that threshold voltage control of MOS transistors is possible. However, it is difficult to put it into practical use by adding boron alone due to the instability of the MOS transistor mentioned above.
従つて本発明の−実施例によれば、多結晶シリ
コン成長時もしくは成長後に各々ドービング拡散
で1018〜1019／cm3の濃度でボロンを多結晶シリコ
ン中へ添加し続いて水素を含む雰囲気で900℃〜
1100℃の温度で熱処理するボロンはMOSトラン
ジスターのチヤンネルとなるべき基板表面にシリ
コン酸化膜を通して拡散される。適当な時間の後
に1020／cm3程度の濃度で多結晶シリコンにリン拡
散を行うとMOSトランジスターのスレツシユホ
ールド電圧は熱処理時間の平方根に比例して変化
してリン拡散以後の熱処理では変化しない。この
様に安定性のよい任意のMOSトランジスターが
得られる。この方法はＰチヤンネルシリコンゲー
トMOSでも可能であるがＮチヤンネルシリコン
ゲートMOSに適用すると効果的である。 According to an embodiment of the invention, therefore, boron is added to polycrystalline silicon at a concentration of 10 18 to 10 19 /cm 3 by doping diffusion during or after the growth of polycrystalline silicon, followed by hydrogen-containing atmosphere. at 900℃~
Boron, which is heat-treated at a temperature of 1100°C, is diffused through a silicon oxide film onto the surface of the substrate that will become the channel of the MOS transistor. When phosphorus is diffused into polycrystalline silicon at a concentration of about 10 20 /cm 3 after an appropriate period of time, the threshold voltage of the MOS transistor changes in proportion to the square root of the heat treatment time, and does not change with heat treatment after phosphorus diffusion. . In this way, any MOS transistor with good stability can be obtained. Although this method is possible with a P-channel silicon gate MOS, it is effective when applied to an N-channel silicon gate MOS.
第１図はＰチヤンネルシリコンゲートMOSの、
そして第２図はＮチヤンネルシリコンゲート
MOSの熱処理時間の平方根とスレツシユホール
ド電圧の関係を示したもので、ａ，ｂ、そしてＣ
は各図において各々水素雰囲気、スチーム雰囲
気、そして不活性ガス雰囲気を示す。第３図では
第１図において一定時間後でリン拡散を行つた場
合のスレツシユホールド電圧の変化を示したもの
でt′，t″そしてｔはリン拡散時間、さらにa′，
a″そしてａはそれに対応したストツシユホール
ド電圧の変化曲線である。
Figure 1 shows a P-channel silicon gate MOS.
Figure 2 shows an N-channel silicon gate.
This shows the relationship between the square root of the heat treatment time of MOS and the threshold voltage, and a, b, and C
In each figure, represent a hydrogen atmosphere, a steam atmosphere, and an inert gas atmosphere, respectively. Figure 3 shows the change in threshold voltage when phosphorus diffusion is performed after a certain period of time in Figure 1, where t', t'' and t are the phosphorus diffusion time, and a',
a″ and a is the corresponding change curve of the stock hold voltage.
Claims (1)
ウムがチヤンネル領域およびシリコン酸化膜から
なるゲート絶縁膜中に含まれており、かつ該ゲー
ト絶縁膜にはリンが含まれていることを特徴とす
るシリコンゲート電界効果型の半導体装置。1. A silicon gate having a silicon gate electrode, boron or gallium being contained in a channel region and a gate insulating film consisting of a silicon oxide film, and phosphorus being contained in the gate insulating film. A field-effect semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22732084A JPS60121770A (en) | 1984-10-29 | 1984-10-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22732084A JPS60121770A (en) | 1984-10-29 | 1984-10-29 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13587275A Division JPS593869B2 (en) | 1975-11-12 | 1975-11-12 | Method for manufacturing silicon gate field effect semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60121770A JPS60121770A (en) | 1985-06-29 |
| JPH0526350B2 true JPH0526350B2 (en) | 1993-04-15 |
Family
ID=16858954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22732084A Granted JPS60121770A (en) | 1984-10-29 | 1984-10-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60121770A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006520450A (en) * | 2003-03-20 | 2006-09-07 | ルーカス・オートモーティブ・ゲーエムベーハー | Disc brake |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582465A (en) * | 1991-09-24 | 1993-04-02 | Victor Co Of Japan Ltd | Semiconductor device and mos fet |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5020669A (en) * | 1973-06-22 | 1975-03-05 |
-
1984
- 1984-10-29 JP JP22732084A patent/JPS60121770A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5020669A (en) * | 1973-06-22 | 1975-03-05 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006520450A (en) * | 2003-03-20 | 2006-09-07 | ルーカス・オートモーティブ・ゲーエムベーハー | Disc brake |
| JP4658920B2 (en) * | 2003-03-20 | 2011-03-23 | ルーカス・オートモーティブ・ゲーエムベーハー | Disc brake |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60121770A (en) | 1985-06-29 |
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