JPH05259376A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05259376A JPH05259376A JP4054072A JP5407292A JPH05259376A JP H05259376 A JPH05259376 A JP H05259376A JP 4054072 A JP4054072 A JP 4054072A JP 5407292 A JP5407292 A JP 5407292A JP H05259376 A JPH05259376 A JP H05259376A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor element
- semiconductor
- opening
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、複数層に半導体素子を
実装した半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having semiconductor elements mounted on a plurality of layers.
【０００２】[0002]
【従来の技術】プリント配線板を実装基板としてＩＣ素
子等の半導体素子を実装した半導体装置が提供されてい
る。そしてこのような半導体装置において、半導体素子
の実装密度を高めるために半導体素子を複数層に実装す
ることがおこなわれている。図３（ａ）はその一例を示
すものであり、プリント配線板Ａの両面にそれぞれ半導
体素子４を実装するようにしたものである。図３（ａ）
において、１０はプリント配線板Ａに形成した回路、１
１は半導体素子４と回路１０との間にボンディングされ
る金線等のワイヤー、１２は半導体素子４を封止する封
止樹脂である。図３（ｂ）は他の例を示すものであり、
半導体素子４を実装したプリント配線板Ａを複層にして
各プリント配線板Ａを端子ピン等の外部リード１３によ
って一体的に接続するようにしたものである。2. Description of the Related Art There is provided a semiconductor device in which a semiconductor element such as an IC element is mounted using a printed wiring board as a mounting board. In such a semiconductor device, semiconductor elements are mounted in a plurality of layers in order to increase the mounting density of the semiconductor elements. FIG. 3A shows an example thereof, in which the semiconductor elements 4 are mounted on both surfaces of the printed wiring board A, respectively. Figure 3 (a)
In the figure, 10 is a circuit formed on the printed wiring board A, and 1 is
Reference numeral 1 is a wire such as a gold wire bonded between the semiconductor element 4 and the circuit 10, and 12 is a sealing resin for sealing the semiconductor element 4. FIG. 3B shows another example,
The printed wiring board A on which the semiconductor element 4 is mounted is formed into a multi-layer structure, and the respective printed wiring boards A are integrally connected by external leads 13 such as terminal pins.
【０００３】[0003]
【発明が解決しようとする課題】しかし、図３（ａ）の
ものは、半導体素子４はプリント配線板Ａの表裏に２層
で実装できるだけであって、実装密度に限界があるとい
う問題があり、また図３（ｂ）のものは複数枚のプリン
ト配線板Ａを複層に積み上げるために小型化することが
難しいという問題があった。However, the one shown in FIG. 3A has a problem that the semiconductor element 4 can be mounted in two layers on the front and back of the printed wiring board A, and the mounting density is limited. In addition, the structure shown in FIG. 3B has a problem that it is difficult to reduce the size because a plurality of printed wiring boards A are stacked in multiple layers.
【０００４】本発明は上記の点に鑑みてなされたもので
あり、半導体素子の実装密度を高めることができると共
に小型化することもできる半導体装置を提供することを
目的とするものである。The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device which can increase the mounting density of semiconductor elements and can be miniaturized.
【０００５】[0005]
【課題を解決するための手段】本発明に係る半導体装置
は、回路基板１に表裏に開口する開口部２を設け、絶縁
基板３に半導体素子４を実装して作成した素子実装板５
を開口部２内に取着し、開口部２を覆うように回路基板
１の表裏両面に絶縁層６を積層すると共に絶縁層６の表
面に半導体素子４を実装して成ることを特徴とするもの
である。In a semiconductor device according to the present invention, a circuit board 1 is provided with openings 2 open to the front and back, and a semiconductor element 4 is mounted on an insulating substrate 3 to form an element mounting plate 5.
Is attached to the inside of the opening 2, the insulating layer 6 is laminated on both front and back surfaces of the circuit board 1 so as to cover the opening 2, and the semiconductor element 4 is mounted on the surface of the insulating layer 6. It is a thing.
【０００６】[0006]
【作用】回路基板１に表裏に開口する開口部２を設け、
絶縁基板３に半導体素子４を実装して作成した素子実装
板５を開口部２内に取着するようにしているために、回
路基板１内にこのように実装する半導体素子４と回路基
板１の表裏面に実装する半導体素子４とで３層に半導体
素子４を実装することが可能になる。[Function] The circuit board 1 is provided with openings 2 that open to the front and back,
Since the element mounting plate 5 formed by mounting the semiconductor element 4 on the insulating substrate 3 is attached in the opening 2, the semiconductor element 4 and the circuit board 1 thus mounted in the circuit board 1 are mounted. With the semiconductor element 4 to be mounted on the front and back surfaces, the semiconductor element 4 can be mounted on three layers.
【０００７】[0007]
【実施例】以下本発明を実施例によって詳述する。回路
基板１はガラス基材エポキシ樹脂積層板等の樹脂積層板
など絶縁板で形成されるものであり、回路基板１には図
１（ａ）のように表裏に貫通して開口するように開口部
２が設けてある。また、素子実装板５を形成する絶縁基
板３も同様に樹脂積層板などの絶縁板で作成されるもの
であり、その表面に積層した銅箔など金属箔のエッチン
グ加工等によってパターンニングされた内層用回路１５
が形成してある。この絶縁基板３の表面にＩＣ素子等の
半導体素子４を搭載して半導体素子４と内層用回路１５
との間に金線等のワイヤー１１をボンディングすること
によって、絶縁基板３に半導体素子４を実装した素子実
装板５を作成することができるものである。EXAMPLES The present invention will be described in detail below with reference to examples. The circuit board 1 is formed of an insulating plate such as a resin laminated plate such as a glass base epoxy resin laminated plate, and the circuit substrate 1 is opened so as to penetrate through the front and back as shown in FIG. Part 2 is provided. Similarly, the insulating substrate 3 forming the element mounting plate 5 is also made of an insulating plate such as a resin laminated plate, and an inner layer patterned by etching or the like of a metal foil such as a copper foil laminated on the surface thereof. Circuit 15
Is formed. A semiconductor element 4 such as an IC element is mounted on the surface of the insulating substrate 3 and the semiconductor element 4 and the inner layer circuit 15 are mounted.
By bonding a wire 11 such as a gold wire between and, the element mounting plate 5 in which the semiconductor element 4 is mounted on the insulating substrate 3 can be created.
【０００８】このように作成した素子実装板５を図１
（ｂ）のように回路基板１の開口部２内にはめ込んで取
着し、必要に応じて開口部２内にエポキシ樹脂等の封止
樹脂１２を流し込んで封止する。また素子実装板５は必
要に応じて開口部２の内周に接着しておいてもよい。次
に、図１（ｃ）のように、ガラス基材にエポキシ樹脂等
の熱硬化性樹脂を含浸乾燥して調製した所要枚数のプリ
プレグ１６を回路基板１の表面と裏面に重ねると共にさ
らにその外側に銅箔等の金属箔１７を重ね、これを加熱
加圧して積層成形することによって、図１（ｄ）のよう
にプリプレグ１６による絶縁層６を接着層として金属箔
１７を回路基板１の両面に積層する。The element mounting plate 5 thus prepared is shown in FIG.
As shown in (b), the circuit board 1 is fitted into the opening 2 and attached, and a sealing resin 12 such as an epoxy resin is poured into the opening 2 as needed to seal the circuit board 1. The element mounting plate 5 may be adhered to the inner circumference of the opening 2 as required. Next, as shown in FIG. 1C, a required number of prepregs 16 prepared by impregnating and drying a glass substrate with a thermosetting resin such as an epoxy resin are stacked on the front surface and the back surface of the circuit board 1 and further outside thereof. By laminating a metal foil 17 such as a copper foil on the above, and heating and pressurizing the metal foil 17 to form a laminate, the metal foil 17 is formed on both surfaces of the circuit board 1 using the insulating layer 6 formed by the prepreg 16 as an adhesive layer as shown in FIG. To stack.
【０００９】この後に金属箔１７をエッチング加工等す
ることによって、図１（ｅ）のように回路基板１の表裏
面に絶縁層６を介して外層用回路１８を設けると共に、
回路基板１を貫通して設けたスルーホール１９の内周に
スルーホールメッキ層２０を形成することによってプリ
ント配線板Ａを作成する。このスルーホール１９は内層
用回路１５を通るように設けられるものであり、従って
スルーホールメッキ層２０を介して内層用回路１５は外
層用回路１８に導通接続されるようにしてある。Thereafter, the metal foil 17 is subjected to an etching process or the like to provide the outer layer circuit 18 on the front and back surfaces of the circuit board 1 with the insulating layer 6 interposed therebetween, as shown in FIG.
The printed wiring board A is prepared by forming the through hole plating layer 20 on the inner circumference of the through hole 19 penetrating the circuit board 1. The through hole 19 is provided so as to pass through the inner layer circuit 15. Therefore, the inner layer circuit 15 is electrically connected to the outer layer circuit 18 through the through hole plating layer 20.
【００１０】そしてプリント配線板Ａの絶縁層６の表面
に図１（ｆ）に示すようにＩＣ素子等の半導体素子４を
搭載すると共に半導体素子４と外層用回路１８との間に
金線等のワイヤー１１をボンディングし、必要に応じて
この半導体素子４を封止樹脂１２で封止することによっ
て、半導体素子４をプリント配線板Ａの表面に実装して
半導体装置を得ることができるものである。半導体素子
４はプリント配線板Ａの片側の表面にのみ実装して、回
路基板１の内部と片面とで２層に半導体素子４を実装す
る他に、表面の他に回路基板１の裏面にも半導体素子４
を実装して回路基板１の内部と両面とで３層に半導体素
子４を実装することができるものである。Then, as shown in FIG. 1F, a semiconductor element 4 such as an IC element is mounted on the surface of the insulating layer 6 of the printed wiring board A, and a gold wire or the like is provided between the semiconductor element 4 and the outer layer circuit 18. The semiconductor element 4 can be mounted on the surface of the printed wiring board A to obtain a semiconductor device by bonding the wire 11 of the above and sealing the semiconductor element 4 with the sealing resin 12 if necessary. is there. The semiconductor element 4 is mounted only on the surface of one side of the printed wiring board A, and the semiconductor element 4 is mounted in two layers inside and on one side of the circuit board 1, and also on the back surface of the circuit board 1 in addition to the front surface. Semiconductor element 4
And the semiconductor element 4 can be mounted in three layers inside the circuit board 1 and on both sides.
【００１１】このようにして作成される半導体装置にあ
って、回路基板１の表面側に実装された半導体素子４は
外層用回路１８に直接導通接続されており、また回路基
板１の開口部２内に実装された半導体素子４は内層用回
路１５及びスルーホールメッキ層２０を介して外層用回
路１８に導通接続されている。図２（ａ）は回路基板１
にスルーホール２１を設けると共に外層用回路１８に接
続してスルーホール２１の内周にスルーホールメッキ層
２２を設け、このスルーホール２１に端子ピン２３の頭
部を圧入して取り付けることによって、半導体装置をＰ
ＧＡなどとして作成するようにしたものである。また図
２（ｂ）は外層用回路１５にリードフレーム等のリード
２４を半田付け等して取着することによって、半導体装
置をＱＦＰなどとして作成するようにしたものである。In the semiconductor device thus manufactured, the semiconductor element 4 mounted on the front surface side of the circuit board 1 is directly conductively connected to the outer layer circuit 18, and the opening 2 of the circuit board 1 is connected. The semiconductor element 4 mounted therein is electrically connected to the outer layer circuit 18 through the inner layer circuit 15 and the through-hole plating layer 20. FIG. 2A shows a circuit board 1.
A through hole 21 is formed on the inner surface of the through hole 21 by connecting to the outer layer circuit 18, and the head of the terminal pin 23 is press-fitted into the through hole 21 to attach the semiconductor pin Device is P
It is created as a GA or the like. Further, FIG. 2B shows that the semiconductor device is produced as a QFP or the like by attaching leads 24 such as a lead frame to the outer layer circuit 15 by soldering or the like.
【００１２】[0012]
【発明の効果】上記のように本発明は、回路基板に表裏
に開口する開口部を設け、絶縁基板に半導体素子を実装
して作成した素子実装板を開口部内に取着し、開口部を
覆うように回路基板の表裏両面に絶縁層を積層すると共
に絶縁層の表面に半導体素子を実装するようにしたの
で、回路基板の開口部内に実装する半導体素子と回路基
板の表裏に実装する半導体素子とで３層に半導体素子を
実装することが可能になって、半導体素子の実装密度を
高めることができるものであり、しかも１枚の回路基板
にこのように半導体素子を実装することができるもので
あって、小型化することが可能になるものである。As described above, according to the present invention, the circuit board is provided with the openings which are opened on the front and back sides, and the element mounting plate prepared by mounting the semiconductor element on the insulating substrate is attached to the inside of the opening, and the opening is opened. Since the insulating layers are laminated on both front and back surfaces of the circuit board so as to cover and the semiconductor element is mounted on the surface of the insulating layer, the semiconductor element mounted inside the opening of the circuit board and the semiconductor element mounted on the front and back surfaces of the circuit board With this, it is possible to mount semiconductor elements on three layers, and it is possible to increase the mounting density of semiconductor elements, and moreover, it is possible to mount semiconductor elements in this way on a single circuit board. However, it is possible to reduce the size.
【図１】本発明の一実施例を示すものであり、（ａ）乃
至（ｅ）はそれぞれ製造の各工程部分の一部の断面図、
（ｆ）は半導体装置の一部の断面図である。FIG. 1 shows an embodiment of the present invention, in which (a) to (e) are cross-sectional views of a part of each process step of manufacturing,
(F) is a partial cross-sectional view of the semiconductor device.
【図２】同上の完成状態を示すものであり、（ａ），
（ｂ）はそれぞれ断面図である。FIG. 2 shows a completed state of the above, (a),
(B) is a sectional view, respectively.
【図３】従来例を示すものであり、（ａ），（ｂ）はそ
れぞれ断面図である。FIG. 3 shows a conventional example, and (a) and (b) are cross-sectional views, respectively.
１ 回路基板 ２ 開口部 ３ 絶縁基板 ４ 半導体素子 ５ 素子実装板 ６ 絶縁層 1 circuit board 2 opening 3 insulating substrate 4 semiconductor element 5 element mounting plate 6 insulating layer
Claims (1)
け、絶縁基板に半導体素子を実装して作成した素子実装
板を開口部内に取着し、開口部を覆うように回路基板の
表裏両面に絶縁層を積層すると共に絶縁層の表面に半導
体素子を実装して成ることを特徴とする半導体装置。1. A circuit board is provided with openings that open on the front and back sides, and an element mounting plate made by mounting a semiconductor element on an insulating substrate is attached to the inside of the opening. A semiconductor device comprising: an insulating layer laminated on a substrate, and a semiconductor element mounted on the surface of the insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4054072A JPH05259376A (en) | 1992-03-13 | 1992-03-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4054072A JPH05259376A (en) | 1992-03-13 | 1992-03-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05259376A true JPH05259376A (en) | 1993-10-08 |
Family
ID=12960418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4054072A Withdrawn JPH05259376A (en) | 1992-03-13 | 1992-03-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05259376A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151702A (en) * | 1992-11-09 | 1994-05-31 | Nec Corp | Multichip module |
| JPH08213543A (en) * | 1994-10-20 | 1996-08-20 | Hughes Aircraft Co | Multidie package device |
| JP2015084434A (en) * | 2010-07-23 | 2015-04-30 | テッセラ，インコーポレイテッド | Microelectronic element with post-assembly planarization |
-
1992
- 1992-03-13 JP JP4054072A patent/JPH05259376A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151702A (en) * | 1992-11-09 | 1994-05-31 | Nec Corp | Multichip module |
| JPH08213543A (en) * | 1994-10-20 | 1996-08-20 | Hughes Aircraft Co | Multidie package device |
| JP2015084434A (en) * | 2010-07-23 | 2015-04-30 | テッセラ，インコーポレイテッド | Microelectronic element with post-assembly planarization |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |