JPH0629393A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0629393A JPH0629393A JP10865593A JP10865593A JPH0629393A JP H0629393 A JPH0629393 A JP H0629393A JP 10865593 A JP10865593 A JP 10865593A JP 10865593 A JP10865593 A JP 10865593A JP H0629393 A JPH0629393 A JP H0629393A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- clock
- clock signal
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路に関し、
特に信号配線の配置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to the arrangement of signal wiring.
【０００２】[0002]
【従来の技術】従来例を図４を参照して説明する。2. Description of the Related Art A conventional example will be described with reference to FIG.
【０００３】図４はスタンダードセル方式の半導体集積
回路におけるクロック信号の分配を説明するための図で
ある。半導体チップのセル列領域１００に、第１のクロ
ックφ１を受けるラッチ回路セル１ａ，１ｂ…，第２の
クロックφ２を受けるラッチ回路セル２ａ，２ｂ，…，
その他の機能セル３１，３２，…が設けられている。セ
ル列１００間の配線チャネル領域２００に、第１，第２
のクロック信号配線４１，４２（例えば第１層アルミニ
ウム膜でできている）が互いに隣接して平行に配置さ
れ、ラッチ回路セルには例えば第２層アルミニウム膜か
らなる第１，第２のクロック信号配線の枝４１ａ，４１
ｂ，…，４２ａ，４２ｂ…が接続されている。FIG. 4 is a diagram for explaining distribution of clock signals in a standard cell type semiconductor integrated circuit. In the cell column region 100 of the semiconductor chip, the latch circuit cells 1a, 1b ... Receiving the first clock .phi.1, the latch circuit cells 2a, 2b ,.
Other functional cells 31, 32, ... Are provided. In the wiring channel region 200 between the cell rows 100, the first and second
Clock signal wirings 41, 42 (made of, for example, a first layer aluminum film) are arranged in parallel with each other, and the first and second clock signals made of, for example, a second layer aluminum film are provided in the latch circuit cells. Wiring branches 41a, 41
, 42a, 42b ... Are connected.
【０００４】[0004]
【発明が解決しようとする課題】この従来例では、前述
したように第１のクロックφ１と第２のクロックφ２は
スキューを小さくするために、各々隣接し平行して配置
された信号配線により供給されるので隣接して配置され
る距離が長いと、クロストークにより誤動作する問題が
あった。In this conventional example, as described above, the first clock .phi.1 and the second clock .phi.2 are supplied by the signal wirings arranged adjacent to each other in order to reduce the skew. Therefore, if the distances arranged adjacent to each other are long, there is a problem that malfunction occurs due to crosstalk.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体集積回路
は、所定層次の導電膜からなる接地配線または電源配線
のいずれか一方と隣接して平行に設けられた同一層次の
信号配線を有するというものである。A semiconductor integrated circuit of the present invention has a signal wiring of the same layer which is provided in parallel adjacent to either one of a ground wiring and a power supply wiring made of a conductive film of a predetermined layer. It is a thing.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【０００７】図１は本発明の第１の実施例のスタンダー
ドセル方式の半導体集積回路を概略的に示す図である。FIG. 1 is a diagram schematically showing a standard cell type semiconductor integrated circuit according to a first embodiment of the present invention.
【０００８】半導体チップの層間絶縁膜上、配線チャネ
ル領域２００に幅１μｍの第１層アルミニウム膜が３
本、間隔１μｍで平行に配置されて第１のクロック信号
配線４１（第１のクロックφ１が供給される）接地配線
５，第２のクロック信号配線４２（第２のクロックφ２
が供給される）を構成している。第１（または第２）の
クロック信号配線４１（または４２）とラッチ回路１
ａ，１ｂ，１ｃ，…（または２ａ，２ｂ，…）とは第２
層アルミニウム膜からなるクロック信号配線４１（また
は４２）の枝４１ａ，４１ｂ，４１ｃ，…（または４２
ａ，４２ｂ，…）で結ばれている。第１のクロック信号
配線４１と第２のクロック信号配線４２との間に接地配
線５が設けらているので、第１のクロックφ１と第２の
クロックφ２のとクロクトークが抑制される。なお、接
地配線５は、各種回路に接地電位を供給する本来の接地
配線とは異なり、単にφ１とφ２のクロストークを抑制
するために設けられた配線である。On the inter-layer insulation film of the semiconductor chip, the wiring channel region 200 is provided with three first-layer aluminum films each having a width of 1 μm.
The first clock signal wiring 41 (to which the first clock φ1 is supplied) ground wiring 5 and the second clock signal wiring 42 (second clock φ2) which are arranged in parallel at intervals of 1 μm
Is supplied). First (or second) clock signal wiring 41 (or 42) and latch circuit 1
a, 1b, 1c, ... (or 2a, 2b, ...) is the second
(Or 42) branches 41a, 41b, 41c, ... (or 42) of the clock signal wiring 41 (or 42) made of a single layer aluminum film
a, 42b, ...). Since the ground wiring 5 is provided between the first clock signal wiring 41 and the second clock signal wiring 42, crosstalk between the first clock φ1 and the second clock φ2 is suppressed. The ground wiring 5 is different from the original ground wiring that supplies a ground potential to various circuits, and is simply a wiring provided to suppress crosstalk between φ1 and φ2.
【０００９】図２は本発明の第２の実施例を示す図であ
る。FIG. 2 is a diagram showing a second embodiment of the present invention.
【００１０】第１層信号配線を２つの接地配線５１，５
２で挾んで配置する。接地配線５１，５２の幅は各１０
μｍとする。本来、接地配線としては幅２０μｍが必要
な場合、これを２分割して平行配置し、雑音に弱いクロ
ック信号線の一部をその間に例えば幅１μｍの第１層信
号配線６１として設ける。第２層信号配線６２は例えば
クロック信号を個別の回路に供給するための分枝であ
り、層間絶縁膜に設けられたスルーホール７で下層の第
１層信号配線６１と接続される。信号配線の両側に接地
配線を配置してあるのでシールドがよく行なわれる。The first layer signal wiring is connected to two ground wirings 51, 5
Place it in between. The width of each of the ground wirings 51 and 52 is 10
μm. Originally, when the ground wiring needs to have a width of 20 μm, it is divided into two and arranged in parallel, and a part of the clock signal line vulnerable to noise is provided between them as the first-layer signal wiring 61 having a width of 1 μm, for example. The second-layer signal wiring 62 is, for example, a branch for supplying a clock signal to an individual circuit, and is connected to the lower-layer first-layer signal wiring 61 through the through hole 7 provided in the interlayer insulating film. Since the ground wiring is arranged on both sides of the signal wiring, shielding is often performed.
【００１１】接地配線５１，５２のいずれか一方または
双方を電源配線に置換えても同様の効果がある。Even if either or both of the ground wirings 51 and 52 are replaced with power supply wirings, the same effect can be obtained.
【００１２】図３に第３の実施例を示す。FIG. 3 shows a third embodiment.
【００１３】集積回路を構成する各種の回路に接地電位
を供給する幅２０μｍの接地配線５Ａ（電源配線でもよ
い）の両側に、これと同層の幅１μｍの第１のクロック
信号配線４１Ａ，第２のクロック信号線４２Ａを配置し
たものである。第１の実施例のように、単にシールドす
るための接地配線を設けなくてもよいので、集積度上、
好都合である。On both sides of a ground wiring 5A having a width of 20 μm (which may be a power supply wiring) for supplying a ground potential to various circuits forming the integrated circuit, a first clock signal wiring 41A having a width of 1 μm, which is the same layer as the ground wiring 5A, is provided. Two clock signal lines 42A are arranged. Unlike the first embodiment, it is not necessary to simply provide the ground wiring for shielding, so that in terms of integration,
It is convenient.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、任意の信
号配線、特にクロック信号配線を接地配線または電源配
線と隣接して平行に配置することにより信号配線相互間
のクロストークを抑制し、半導体集積回路の誤動作を防
ぐ効果を有する。As described above, the present invention suppresses crosstalk between signal wirings by arranging arbitrary signal wirings, particularly clock signal wirings, adjacent to and in parallel with ground wirings or power supply wirings. It has an effect of preventing malfunction of the semiconductor integrated circuit.
【図１】本発明の第１の実施例を示す半導体チップ上の
配置図である。FIG. 1 is a layout view on a semiconductor chip showing a first embodiment of the present invention.
【図２】第２の実施例を示す半導体チップの平面図であ
る。FIG. 2 is a plan view of a semiconductor chip showing a second embodiment.
【図３】第３の実施例を示す半導体チップの平面図であ
る。FIG. 3 is a plan view of a semiconductor chip showing a third embodiment.
【図４】従来の例を示す半導体チップ上の配置図であ
る。FIG. 4 is a layout diagram on a semiconductor chip showing a conventional example.
１ａ，１ｂ，１ｃ ラッチ回路セル ２ａ，２ｂ ラッチ回路セル ３１〜３８ 機能セル ４１，４１Ａ 第１のクロック信号配線 ４１ａ〜４１ｃ ４１の分枝配線 ４２，４２Ａ 第２のクロック信号配線 ４２ａ，４２ｂ ４２の分枝配線 ５，５Ａ，５１，５２ 接地配線 １００ セル列領域 ２００ 配線チャネル領域 1a, 1b, 1c Latch circuit cell 2a, 2b Latch circuit cell 31-38 Functional cell 41, 41A First clock signal wiring 41a-41c 41 Branch wiring 42, 42A Second clock signal wiring 42a, 42b 42 Branch wiring 5,5A, 51,52 Ground wiring 100 Cell row area 200 Wiring channel area
Claims (2)
は電源配線のいずれか一方と隣接して平行に設けられた
同一層次の信号配線を有することを特徴とする半導体集
積回路。1. A semiconductor integrated circuit having signal wirings of the same layer which are provided in parallel adjacent to either one of a ground wiring and a power supply wiring made of a conductive film of a predetermined layer.
項１記載の半導体集積回路。2. The semiconductor integrated circuit according to claim 1, wherein the signal wiring is a clock signal wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10865593A JPH0629393A (en) | 1992-05-12 | 1993-05-11 | Semiconductor integrated circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11863392 | 1992-05-12 | ||
| JP4-118633 | 1992-05-12 | ||
| JP10865593A JPH0629393A (en) | 1992-05-12 | 1993-05-11 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0629393A true JPH0629393A (en) | 1994-02-04 |
Family
ID=26448488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10865593A Pending JPH0629393A (en) | 1992-05-12 | 1993-05-11 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0629393A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7339250B2 (en) | 2000-12-20 | 2008-03-04 | Fujitsu Limited | Semiconductor integrated circuit having reduced cross-talk noise |
| US9359048B2 (en) | 2013-01-18 | 2016-06-07 | Technische Universiteit Delft | Fast ship |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59136948A (en) * | 1983-01-18 | 1984-08-06 | エイ・ティ・アンド・ティ・コーポレーション | Integrated circuit chip |
| JPH0251252A (en) * | 1988-08-15 | 1990-02-21 | Toshiba Corp | Wiring structure of integrated circuit |
-
1993
- 1993-05-11 JP JP10865593A patent/JPH0629393A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59136948A (en) * | 1983-01-18 | 1984-08-06 | エイ・ティ・アンド・ティ・コーポレーション | Integrated circuit chip |
| JPH0251252A (en) * | 1988-08-15 | 1990-02-21 | Toshiba Corp | Wiring structure of integrated circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7339250B2 (en) | 2000-12-20 | 2008-03-04 | Fujitsu Limited | Semiconductor integrated circuit having reduced cross-talk noise |
| US7361975B2 (en) | 2000-12-20 | 2008-04-22 | Fujitsu Limited | Semiconductor integrated circuit having reduced cross-talk noise |
| US7913212B2 (en) | 2000-12-20 | 2011-03-22 | Fujitsu Semiconductor Limited | Method for determining a length of shielding of a semiconductor integrated circuit wiring |
| US9359048B2 (en) | 2013-01-18 | 2016-06-07 | Technische Universiteit Delft | Fast ship |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5309015A (en) | Clock wiring and semiconductor integrated circuit device having the same | |
| JP3179800B2 (en) | Semiconductor integrated circuit device | |
| KR930009024B1 (en) | Semicondcutro ic device | |
| JPH073840B2 (en) | Semiconductor integrated circuit | |
| KR970063679A (en) | A method of wiring metal interconnect lines in an integrated circuit, and the integrated circuit manufactured thereby | |
| JP3154650B2 (en) | Semiconductor device | |
| JPH0629393A (en) | Semiconductor integrated circuit | |
| US5434436A (en) | Master-slice type semiconductor integrated circuit device having multi-power supply voltage | |
| JP3353397B2 (en) | Semiconductor integrated circuit | |
| JP3186715B2 (en) | Semiconductor integrated circuit device | |
| JPH0590427A (en) | Semiconductor ic device | |
| JPH0621225A (en) | Semiconductor integrated circuit device | |
| US6734547B2 (en) | Semiconductor wiring structure having divided power lines and ground lines on the same layer | |
| JP2551499B2 (en) | Semiconductor integrated circuit device | |
| JPH0680670B2 (en) | Semiconductor integrated circuit device | |
| JP2000164696A (en) | Multilayer interconnection structure | |
| JPH08124928A (en) | Semiconductor integrated circuit | |
| JPH0645566A (en) | Semiconductor integrated circuit device | |
| JPH06196665A (en) | Semiconductor integrated circuit | |
| JPH05109913A (en) | Wiring structure of semiconductor integrated circuit | |
| JP2000232103A (en) | Semiconductor device | |
| JPH0774252A (en) | Semiconductor integrated circuit | |
| JPH0536946A (en) | Master slice type semiconductor integrated circuit device | |
| JPH06334157A (en) | Integrated circuit and manufacture thereof | |
| JPH09148545A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19971216 |