JPH05243482A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH05243482A JPH05243482A JP4042933A JP4293392A JPH05243482A JP H05243482 A JPH05243482 A JP H05243482A JP 4042933 A JP4042933 A JP 4042933A JP 4293392 A JP4293392 A JP 4293392A JP H05243482 A JPH05243482 A JP H05243482A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- integrated circuit
- semiconductor integrated
- pads
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は，半導体集積回路，とく
に，メモリセルを備えた半導体集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having memory cells.
【０００２】[0002]
【従来の技術】半導体集積回路の高性能化および高密度
化にともなって，その内部配線は，レイアウトがますま
す複雑になりかつ幅が縮小の一途をたどっている。2. Description of the Related Art As the performance and density of semiconductor integrated circuits have increased, the internal wiring has become more and more complicated in layout and its width has been reduced.
【０００３】[0003]
【発明が解決しようとする課題】細線化にともなう抵抗
の増大およびストレスマイグレーションあるいはエレク
トロマイグレーションによる信頼性の低下等の問題は，
高融点金属やシリサイド等の導入による解決が図られて
いる。細線化は，一方で，高アスペクト比のリソグラフ
技術を必要とする。したがって, 将来の高密度半導体集
積回路の内部配線における問題は，レイアウトの設計，
材料の選択，リソグラフィを含めて総合的な観点からの
解決が要求され，ますます困難性が高まりつつある。Problems such as an increase in resistance due to thinning and a decrease in reliability due to stress migration or electromigration are caused by the following problems.
The solution is attempted by introducing refractory metal, silicide, and the like. Thinning, on the other hand, requires high aspect ratio lithographic techniques. Therefore, the problems in the internal wiring of future high-density semiconductor integrated circuits are
Difficulties are increasing with the selection of materials and the solution from a comprehensive perspective including lithography.
【０００４】本発明は，現状の材料技術およびリソグラ
フ技術によってもなおかつ上記のような問題点を解決可
能とし，より高密度化された半導体集積回路を提供可能
とすることを目的とする。It is an object of the present invention to solve the above problems with the current material technology and lithographic technology, and to provide a semiconductor integrated circuit having a higher density.
【０００５】[0005]
【課題を解決するための手段】上記目的は，第１の半導
体集積回路が形成され且つ該第１の半導体集積回路の入
出力端に接続された複数の電極が表出する表面を有する
第１のチップと, 第２の半導体集積回路が形成され且つ
該第１のチップより小面積であるチップであって，該第
２の半導体集積回路の入出力端に接続されるとともに各
々が該第１のチップ表面における該複数の電極と面対称
の関係に配置された複数の電極が表出した表面を有し且
つ該表面が該第１のチップの表面に対向するようにして
該第１のチップ上に配置された第２のチップと, 該第１
のチップ表面における該複数の電極と該第２のチップ表
面における該複数の電極とを互いに接続するための接続
手段とを備えたことを特徴とする本発明に係る半導体集
積回路，または，上記において，前記第１のチップの周
辺領域に前記第１の半導体集積回路の入出力端または前
記接続手段を介して前記第２の半導体集積回路の入出力
端に接続され且つ外部回路に対して接続可能な電極が設
けられているか，あるいは，前記第１のチップ表面上に
複数の前記第２のチップが配置されていることを特徴と
する本発明に係る半導体集積回路によって達成される。A first semiconductor integrated circuit is formed, and a first surface having a plurality of electrodes connected to input / output terminals of the first semiconductor integrated circuit is exposed. And the second semiconductor integrated circuit are formed and have a smaller area than that of the first chip. The chip is connected to the input / output terminal of the second semiconductor integrated circuit and each of the first and second chips is connected to the first semiconductor chip. Of the first chip having a surface on which a plurality of electrodes arranged in plane symmetry with the plurality of electrodes on the surface of the first chip are exposed and the surface facing the surface of the first chip. A second chip disposed above the first chip and the first chip
The semiconductor integrated circuit according to the present invention, further comprising: connecting means for connecting the plurality of electrodes on the chip surface and the plurality of electrodes on the second chip surface to each other. , Is connected to the peripheral region of the first chip to the input / output end of the first semiconductor integrated circuit or the input / output end of the second semiconductor integrated circuit via the connecting means, and is connectable to an external circuit This is achieved by the semiconductor integrated circuit according to the present invention, characterized in that various electrodes are provided or a plurality of the second chips are arranged on the surface of the first chip.
【０００６】[0006]
【作用】本発明の基本的は，一つの半導体集積回路を構
成する回路ブロックを，機能別あるいは共通の内部配線
を多く有するものどうし別に分け，それぞれを別のチッ
プに形成し，これらのチップを積み重ねてそれぞれの入
出力端子を相互接続することによって，集積回路全体と
しての専有面積を増加させることなく，各チップにおけ
る内部配線のレイアウトを単純にするとともに，配線密
度を低くする。これによって，従来の材料技術およびリ
ソグラフ技術によって，内部配線の抵抗を低く維持しか
つ信頼性を高めることが可能となる。The basic feature of the present invention is that the circuit blocks constituting one semiconductor integrated circuit are divided into functional blocks or those having a large number of common internal wirings, each of which is formed on a separate chip. By stacking and interconnecting the respective input / output terminals, the layout of internal wiring in each chip is simplified and the wiring density is lowered without increasing the area occupied by the integrated circuit as a whole. As a result, the resistance of the internal wiring can be kept low and the reliability can be improved by the conventional material technology and lithographic technology.
【０００７】[0007]
【実施例】図１は本発明の第１の実施例説明図であっ
て，例えば複数のメモリセル（図示省略）が形成された
チップ10を, 同図(a) に示すように, これらメモリセル
を駆動するための周辺回路（図示省略）が形成されたチ
ップ20の上に積み重ね, チップ10の周辺に形成されてい
るパッド11と, チップ20の表面にパッド11に対応するよ
うに形成されているパッド12との間を, 同図(b) に示す
ように, 例えばパッド11または12上にあらかじめ形成さ
れている半田から成るバンプ13によって接続する。パッ
ド11は, チップ10に形成されているメモリセルの入出力
端に, パッド12は, チップ20に形成されている周辺回路
の入出力端に, それぞれ接続されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining a first embodiment of the present invention. For example, a chip 10 having a plurality of memory cells (not shown) is formed in such a memory as shown in FIG. It is stacked on a chip 20 on which peripheral circuits (not shown) for driving cells are formed, and pads 11 formed on the periphery of the chip 10 are formed on the surface of the chip 20 so as to correspond to the pads 11. As shown in FIG. 2B, the bumps 13 made of solder and formed in advance on the pads 11 or 12 are connected to the pads 12 that are formed. The pad 11 is connected to the input / output terminal of the memory cell formed on the chip 10, and the pad 12 is connected to the input / output terminal of the peripheral circuit formed on the chip 20.
【０００８】前記周辺回路は, チップ20表面に形成され
ている図示しない配線によって, チップ20の周辺に形成
されている外部接続用のパッド15に接続されている。こ
れにより, 前記メモリセルは, 同一チップにメモリセル
と周辺回路とが形成された通常の半導体メモリ装置とま
ったく同様に使用することができる。なお, 図１(b)に
おける符号16は, パッド15に接続された例えばアルミニ
ウムから成るボンディングワイヤである。The peripheral circuit is connected to an external connection pad 15 formed around the chip 20 by a wiring (not shown) formed on the surface of the chip 20. Accordingly, the memory cell can be used in exactly the same way as a normal semiconductor memory device in which the memory cell and the peripheral circuit are formed on the same chip. Reference numeral 16 in FIG. 1 (b) is a bonding wire connected to the pad 15 and made of, for example, aluminum.
【０００９】図１の構造によれば, 前記メモリセルおよ
び周辺回路はチップ10および20に個別に形成されるため
に, それぞれの内部配線のレイアウトは簡単かつ大きな
設計の自由度を有する。また, その線幅を大きく設定す
ることができるために, 低抵抗となり, かつ, 信頼性が
向上する。このような効果は, 内部配線のみならず,メ
モリセルや周辺回路を構成する拡散領域や層間絶縁層に
形成されるコンタクトホールに対する面積上の制約を緩
和する上でも有効であることは言うまでもない。According to the structure of FIG. 1, since the memory cell and the peripheral circuit are individually formed in the chips 10 and 20, the layout of the internal wirings is simple and has a large degree of freedom in design. Also, since the line width can be set large, the resistance becomes low and the reliability is improved. It goes without saying that such an effect is effective not only for relaxing the internal wiring but also for relaxing the restriction on the area of the contact hole formed in the diffusion region forming the memory cell and the peripheral circuit and the interlayer insulating layer.
【００１０】図２は本発明の第２の実施例説明図であっ
て, 第１の実施例におけるチップ10の他に, 論理回路が
形成された第３のチップ30をチップ20上にさらに積み重
ねた場合である。チップ30表面に形成されたパッドと,
チップ20表面に形成された対応するパッドとが前記実施
例と同様にして接続され, これによって, 前記論理回路
は, チップ20に形成されている周辺回路を通じて, チッ
プ10に形成されているメモリセルにアクセス可能とさ
れ, また, チップ20の周辺に形成されているパッド15を
通じて外部回路に接続される。FIG. 2 is a diagram for explaining a second embodiment of the present invention. In addition to the chip 10 in the first embodiment, a third chip 30 having a logic circuit formed thereon is further stacked on the chip 20. That is the case. A pad formed on the surface of the chip 30,
The corresponding pads formed on the surface of the chip 20 are connected in the same manner as in the above embodiment, so that the logic circuit is connected to the memory cells formed on the chip 10 through the peripheral circuits formed on the chip 20. To the external circuit through the pad 15 formed in the periphery of the chip 20.
【００１１】図３は, 前記チップ10またはチップ30とチ
ップ20との間の別の接続方法の説明図である。すなわ
ち，本実施例においては，チップ10またはチップ30にお
けるパッド11に対して，いわゆるTAB(tape automated b
onding) 法による銅箔状のリード線18の一端を接続して
おき, リード線18を所定形状に整形・切断したのち, そ
れぞれの他端を, チップ20上のパッド12に接続する。FIG. 3 is an explanatory view of another connection method between the chip 10 or the chip 30 and the chip 20. That is, in the present embodiment, so-called TAB (tape automated b) is applied to the chip 10 or the pad 11 on the chip 30.
One end of the copper foil lead wire 18 by the onding method is connected in advance, the lead wire 18 is shaped and cut into a predetermined shape, and then the other end is connected to the pad 12 on the chip 20.
【００１２】上記説明から分かるように, チップ10およ
び30におけるパッド11の配置と, チップ20におけるパッ
ド12の配置とを標準化しておけば, 本発明の主旨は, チ
ップ10に形成されるメモリセル, チップ20上に形成され
る周辺回路, チップ30上に形成される論理回路のそれぞ
れの種類によって限定されない。つまり, メモリセルの
容量の異なるチップ, 機能の異なる論理回路を有するチ
ップ, および, これらメモリセルおよび論理回路の制御
に必要な周辺回路を有するチップを任意に組み合わるこ
とができる。As can be seen from the above description, if the arrangement of the pads 11 in the chips 10 and 30 and the arrangement of the pads 12 in the chip 20 are standardized, the gist of the present invention is to realize the memory cell formed in the chip 10. The peripheral circuit formed on the chip 20 and the logic circuit formed on the chip 30 are not limited. That is, chips having different memory cell capacities, chips having logic circuits having different functions, and chips having peripheral circuits necessary for controlling these memory cells and logic circuits can be arbitrarily combined.
【００１３】[0013]
【発明の効果】上記のように, 本発明は ,一つの半導体
集積回路を構成する回路ブロックを，機能別あるいは共
通の内部配線を多く有するものどうし別に分け，それぞ
れを別のチップに形成し，これらのチップを積み重ねて
それぞれの入出力端子を相互接続する。これにより，集
積回路全体としての専有面積を増加させることなく，各
チップにおける内部配線のレイアウトを単純にするとと
もに，配線密度を低くすることができる。その結果, 低
抵抗の高信頼性の配線を必要とする高性能・高密度半導
体集積回路の開発促進, 製造歩留まりおよび信頼性の向
上に効果がある。As described above, according to the present invention, the circuit blocks constituting one semiconductor integrated circuit are divided according to their function or those having a large number of common internal wirings, and they are formed on different chips. These chips are stacked and their input / output terminals are interconnected. As a result, the layout of the internal wiring in each chip can be simplified and the wiring density can be reduced without increasing the area occupied by the entire integrated circuit. As a result, it is effective in promoting the development of high-performance / high-density semiconductor integrated circuits that require low-resistance and highly reliable wiring, and improving the manufacturing yield and reliability.
【００１４】さらに, 本発明によれば, 所望の容量を有
するメモリセルが形成されたチップまたは所望の機能を
有する論理回路が形成されたチップを所要の周辺回路を
有するチップ上に積み重ねて相互接続を行うだけで, 様
々な仕様の半導体集積回路を作製することができる。し
たがって, ユーザーの要求に最適な半導体集積回路を低
コストかつ短納期で提供可能とする効果がある。Further, according to the present invention, a chip in which a memory cell having a desired capacity is formed or a chip in which a logic circuit having a desired function is formed is stacked on a chip having a required peripheral circuit and interconnected. It is possible to fabricate semiconductor integrated circuits of various specifications simply by performing. Therefore, there is an effect that it is possible to provide a semiconductor integrated circuit most suitable for the user's request at low cost and in a short delivery time.
【図１】 本発明の第１の実施例説明図FIG. 1 is an explanatory diagram of a first embodiment of the present invention.
【図２】 本発明の第２の実施例説明図FIG. 2 is an explanatory diagram of a second embodiment of the present invention.
【図３】 本発明の第３の実施例説明図FIG. 3 is an explanatory diagram of a third embodiment of the present invention.
10, 20, 30 チップ 16 ボンディングワイヤ 11, 12, 15 パッド 18 リード線 13 バンプ 10, 20, 30 Chip 16 Bonding wire 11, 12, 15 Pad 18 Lead wire 13 Bump
Claims (4)
第１の半導体集積回路の入出力端に接続された複数の電
極が表出する表面を有する第１のチップと, 第２の半導体集積回路が形成され且つ該第１のチップよ
り小面積であるチップであって，該第２の半導体集積回
路の入出力端に接続されるとともに各々が該第１のチッ
プ表面における該複数の電極と面対称の関係に配置され
た複数の電極が表出した表面を有し且つ該表面が該第１
のチップの表面に対向するようにして該第１のチップ上
に配置された第２のチップと, 該第１のチップ表面における該複数の電極と該第２のチ
ップ表面における該複数の電極とを互いに接続するため
の接続手段とを備えたことを特徴とする半導体集積回
路。1. A first chip having a surface on which a first semiconductor integrated circuit is formed and a plurality of electrodes connected to input / output terminals of the first semiconductor integrated circuit are exposed, and a second semiconductor. A chip having an integrated circuit formed thereon and having a smaller area than the first chip, the chip being connected to the input / output terminal of the second semiconductor integrated circuit and each of the plurality of electrodes on the surface of the first chip. Has a surface exposed by a plurality of electrodes arranged in plane symmetry with respect to the first electrode.
A second chip disposed on the first chip so as to face the surface of the first chip, the plurality of electrodes on the surface of the first chip, and the plurality of electrodes on the surface of the second chip And a connecting means for connecting the two together.
の半導体集積回路の入出力端または前記接続手段を介し
て前記第２の半導体集積回路の入出力端に接続され且つ
外部回路に対して接続可能な電極が設けられていること
を特徴とする請求項１記載の半導体集積回路。2. The first region is provided in a peripheral region of the first chip.
2. An electrode is provided which is connected to the input / output end of the semiconductor integrated circuit or the input / output end of the second semiconductor integrated circuit through the connecting means and is connectable to an external circuit. Item 2. The semiconductor integrated circuit according to item 1.
２のチップが配置されていることを特徴とする請求項１
または２記載の半導体集積回路。3. The plurality of second chips are arranged on the surface of the first chip.
Alternatively, the semiconductor integrated circuit according to the item 2.
を含み且つ前記第１の半導体集積回路は該メモリセルを
駆動するための周辺回路を含むことを特徴とする請求項
１，２または３記載の半導体集積回路。4. The second semiconductor integrated circuit includes a memory cell, and the first semiconductor integrated circuit includes a peripheral circuit for driving the memory cell. The semiconductor integrated circuit described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4042933A JPH05243482A (en) | 1992-02-28 | 1992-02-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4042933A JPH05243482A (en) | 1992-02-28 | 1992-02-28 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05243482A true JPH05243482A (en) | 1993-09-21 |
Family
ID=12649816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4042933A Withdrawn JPH05243482A (en) | 1992-02-28 | 1992-02-28 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05243482A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640049A (en) * | 1995-08-18 | 1997-06-17 | Lsi Logic Corporation | Metal interconnect structures for use with integrated circuit devices to form integrated circuit structures |
| US5726500A (en) * | 1994-04-08 | 1998-03-10 | Thomson-Csf | Semiconductor hybrid component |
| KR100401501B1 (en) * | 2001-04-19 | 2003-10-17 | 주식회사 하이닉스반도체 | Chip stack package |
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| US7126226B2 (en) | 1999-02-03 | 2006-10-24 | Rohm Co., Ltd. | Semiconductor device and semiconductor chip for use therein |
| US7760573B2 (en) | 2005-02-10 | 2010-07-20 | Elpida Memory, Inc. | Semiconductor memory device and stress testing method thereof |
| US9240405B2 (en) | 2011-04-19 | 2016-01-19 | Macronix International Co., Ltd. | Memory with off-chip controller |
| US11289130B2 (en) | 2020-08-20 | 2022-03-29 | Macronix International Co., Ltd. | Memory device |
-
1992
- 1992-02-28 JP JP4042933A patent/JPH05243482A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5726500A (en) * | 1994-04-08 | 1998-03-10 | Thomson-Csf | Semiconductor hybrid component |
| US5640049A (en) * | 1995-08-18 | 1997-06-17 | Lsi Logic Corporation | Metal interconnect structures for use with integrated circuit devices to form integrated circuit structures |
| US5756395A (en) * | 1995-08-18 | 1998-05-26 | Lsi Logic Corporation | Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures |
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| US7126226B2 (en) | 1999-02-03 | 2006-10-24 | Rohm Co., Ltd. | Semiconductor device and semiconductor chip for use therein |
| KR100401501B1 (en) * | 2001-04-19 | 2003-10-17 | 주식회사 하이닉스반도체 | Chip stack package |
| US7760573B2 (en) | 2005-02-10 | 2010-07-20 | Elpida Memory, Inc. | Semiconductor memory device and stress testing method thereof |
| US9240405B2 (en) | 2011-04-19 | 2016-01-19 | Macronix International Co., Ltd. | Memory with off-chip controller |
| US11289130B2 (en) | 2020-08-20 | 2022-03-29 | Macronix International Co., Ltd. | Memory device |
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