JPH0521763A - Semiconductor substrate, device and its manufacturing method - Google Patents

Abstract

PURPOSE:To diminish resistance in heat radiation, by forming an insulating layer thinly in an SOI structure, and by using a supporting substrate made of a material having thermal conductivity larger than that of an Si substrate. CONSTITUTION:A silicon oxide film is formed on the surface of an Si substrate 1 in a thermal oxidation step. On the other hand, a silicon film 4 is deposited on an aluminum nitride substrate 3, and the residual strain is attenuated in thermal treatment, and moreover the main face is abraded with a wafer lapping apparatus. In a dust-free condition, the abraded face of the aluminum nitride substrate 3 is directly bonded to the silicon oxide film of the Si substrate 1, and then the substrate is ground and abraded from the Si-substrate side. According to the measurement in heat radiation, the temperature of a semiconductor substrate prepared in this way rises only by 3 deg.C, and the result of effective heat radiation can be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体基板及び半導体
装置とその製造方法に係り、特に、放熱特性に優れ、動
作時の発熱に起因する配線抵抗の増大や信頼性の低下を
防ぎ、半導体装置の大電流動作化、高速化、高集積化を
可能にする構成の半導体基板及び半導体装置とその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate, a semiconductor device, and a method of manufacturing the same, and more particularly to a semiconductor substrate having excellent heat dissipation characteristics, preventing an increase in wiring resistance and a decrease in reliability due to heat generation during operation. The present invention relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing the same, which are configured to enable high current operation, high speed, and high integration of the device.

【０００２】[0002]

【従来の技術】半導体装置を構成すべき半導体層の底部
に絶縁膜を設けた構造はいわゆる SOI(Silicon on Insu
lator)として公知であり、その製造方法についても固相
成長法または液相成長法、酸素イオン注入法およびウエ
ーハ貼り合わせ法などが知られている(例えば、昭和61
年度精密工学会秋季大会学術講演会論文集 219「Siウエ
ハの研磨技術」、Proceedings of 4th International Sy
mposium on Silicon‐on‐Insulator Technology and D
evices, May 6‐11,1990,Montreol所載の“SILICON WAF
ER‐BONDING PROCESS TECHNOLOGY FOR SOI STRUCTURE
S”など)。SOI 層の無欠陥性の観点からはウエーハ貼り
合わせ法が最も実用的であり、図２に示したような構成
及び製造手順からなっている。すなわち、a) まず、平
坦な主表面に酸化膜２を有する第１のシリコン(Si)基板
１と、同じく平坦な主表面を有する第２の Si 基板５と
を準備し、b) 次いで、これらを、無塵状態で、接着剤
等を用いることなく、主表面同士で直接結合させ、結合
強度を強化するための熱処理を施し、c) 最後に、Si 基
板１の裏面を研削と鏡面研磨とにより薄化することによ
って内部にシリコン酸化膜２を有する半導体基板１が得
られる。このような製造手順によって得られる SOI 構
造は、半導体装置を構成すべき半導体層１が完全結晶で
ある点に最大の特徴がある。また、SOI構造の特徴とし
て、絶縁性の膜２の上に半導体装置が構成されるため、
集積回路を構成する各半導体装置間が、底部の半導体基
板を介する経路を含めて、絶縁膜で完全に素子分離を行
い得る点を挙げることができる。従って、α線照射に起
因する誤動作、ラッチアップ現象と呼ばれる隣接素子間
干渉等を完全に防止することができる。2. Description of the Related Art A structure in which an insulating film is provided on the bottom of a semiconductor layer which constitutes a semiconductor device is called a SOI (Silicon on Insu
known as a solid phase growth method or a liquid phase growth method, an oxygen ion implantation method, a wafer bonding method, etc. (for example, Showa 61).
Proceedings of 4th International Sy, Procedings of 4th International Sy
mposium on Silicon‐on‐Insulator Technology and D
evices, May 6-11, 1990, Montreol "SILICON WAF"
ER‐BONDING PROCESS TECHNOLOGY FOR SOI STRUCTURE
S) etc .. From the viewpoint of defect-free SOI layer, the wafer bonding method is the most practical method and has the structure and manufacturing procedure shown in FIG. A first silicon (Si) substrate 1 having an oxide film 2 on the main surface and a second Si substrate 5 having the same flat main surface are prepared, and b) these are bonded in a dust-free state. Without using a chemical agent, etc., the main surfaces are directly bonded to each other, and heat treatment is performed to strengthen the bonding strength. C) Finally, the back surface of the Si substrate 1 is thinned by grinding and mirror polishing so that A semiconductor substrate 1 having a silicon oxide film 2 can be obtained.The SOI structure obtained by such a manufacturing procedure is most characterized in that the semiconductor layer 1 which constitutes a semiconductor device is a perfect crystal. As a structural feature, a semiconductor device is formed on the insulating film 2. Is constructed,
It can be pointed out that between the respective semiconductor devices forming the integrated circuit, the element can be completely separated by the insulating film, including the path through the bottom semiconductor substrate. Therefore, malfunctions due to α-ray irradiation, interference between adjacent elements called a latch-up phenomenon, etc. can be completely prevented.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、SOI 構
造の最大の問題点は、絶縁膜としてシリコン酸化膜を用
いていることにある。すなわち、シリコン酸化膜の熱伝
導率が小さく、単結晶Siと比較して２桁も小さいため
に、超高速、超高集積半導体集積回路等、発熱の著しい
半導体装置への SOI 構造の適用は信頼性等の点で問題
が生じる恐れがある。しかし、シリコン酸化膜は半導体
プロセス材料として最も優れたものであり、現時点でこ
れに代る高熱伝導でかつ高品質の材料は見出されていな
い。この問題に対応するために、シリコン酸化膜２の膜
厚を薄く構成して放熱抵抗を低減する手法も考えられる
が、この場合、半導体層１と半導体基板５との間の静電
容量が増加して、超高速半導体装置の高速動作を阻害す
るという欠点が新たに生じる。However, the biggest problem of the SOI structure is that the silicon oxide film is used as the insulating film. In other words, the thermal conductivity of the silicon oxide film is small, and it is two orders of magnitude smaller than that of single crystal Si. Therefore, it is reliable to apply the SOI structure to semiconductor devices that generate heat significantly, such as ultra-high speed and ultra high integration semiconductor integrated circuits. Problems may occur in terms of sex. However, the silicon oxide film is the most excellent as a semiconductor process material, and at present, no alternative material having high heat conductivity and high quality has been found. In order to deal with this problem, a method of reducing the heat radiation resistance by making the film thickness of the silicon oxide film 2 thin may be considered, but in this case, the capacitance between the semiconductor layer 1 and the semiconductor substrate 5 increases. As a result, there is a new defect that the high speed operation of the ultra high speed semiconductor device is hindered.

【０００４】本発明の目的は、上記従来技術の有してい
た課題を解決して、放熱特性に優れ、動作時の発熱に起
因する配線抵抗の増大や信頼性の低下を防ぎ、半導体装
置の大電流動作化、高速化、高集積化を可能にする構成
の半導体基板及び半導体装置とその製造方法を提供する
ことにある。The object of the present invention is to solve the problems of the prior art described above, to provide excellent heat dissipation characteristics, to prevent an increase in wiring resistance and a decrease in reliability due to heat generation during operation, and It is an object of the present invention to provide a semiconductor substrate and a semiconductor device having a configuration that enables high current operation, high speed, and high integration, and a manufacturing method thereof.

【０００５】[0005]

【課題を解決するための手段】上記目的は、第１の基板
と、該基板の少なくとも主表面を被覆するように設けた
第１の薄膜と、該薄膜上に設けた第１の絶縁膜と、該絶
縁膜上に設けた単結晶半導体層とから構成される半導体
基板において、上記第１の基板の熱伝導率を上記単結晶
半導体層の熱伝導率よりも大とした半導体基板とするこ
とによって達成することができる。The above object is to provide a first substrate, a first thin film provided so as to cover at least the main surface of the substrate, and a first insulating film provided on the thin film. A semiconductor substrate composed of a single crystal semiconductor layer provided on the insulating film, wherein the first substrate has a thermal conductivity higher than that of the single crystal semiconductor layer. Can be achieved by

【０００６】本発明の基本的な考え方は、半導体プロセ
ス材料として必須のシリコン酸化膜を SOI 構成用の絶
縁膜として用いるが、放熱抵抗を低減するようにシリコ
ン酸化膜の膜厚を薄く構成し、かつ、静電容量も低減す
る方法を導入し、さらに、単結晶 Si による半導体基板
の代りに熱伝導率の大きな材料を支持基板として用いる
ことによって、従来の SOI 型半導体基板のみならず、
通常の単結晶基板よりも放熱効果に優れた半導体基板を
実現するということにある。The basic idea of the present invention is to use a silicon oxide film, which is essential as a semiconductor process material, as an insulating film for SOI structure. However, the silicon oxide film is made thin so as to reduce the heat radiation resistance. In addition, by introducing a method of reducing the capacitance and using a material with a large thermal conductivity as a supporting substrate instead of the semiconductor substrate made of single crystal Si, not only the conventional SOI type semiconductor substrate but also
It is to realize a semiconductor substrate having a heat dissipation effect superior to that of an ordinary single crystal substrate.

【０００７】なお、上記の熱伝導率の大きな支持基板材
料としては、窒化アルミニウム、炭化珪素、酸化ベリリ
ウム等を挙げることができる。これらの材料の半導体製
造工程適合化については、それらの材料を用いた基板の
表面を薄いシリコン膜で覆った後、保護安定化しておけ
ば良い。Examples of the above-mentioned supporting substrate material having a large thermal conductivity include aluminum nitride, silicon carbide, beryllium oxide and the like. In order to adapt these materials to the semiconductor manufacturing process, the surface of the substrate using these materials may be covered with a thin silicon film and then protected and stabilized.

【０００８】[0008]

【作用】SOI を構成する絶縁膜の薄膜化と、Si 基板よ
りも熱伝導率の大きな材料からなる支持基板とを採用す
ることによって放熱抵抗を大幅に低減することができる
ため、バイポーラトランジスタのように発熱の激しい超
高速半導体装置においても、超高集積化が可能となる。
また、発熱による配線抵抗の増大も避けることができ、
さらに超高速の動作の追及が可能となる。また、絶縁膜
を薄膜化した場合に従来構造で問題となっていた空乏化
による寄生容量の発生は、絶縁性支持基板の採用によっ
て根本的に解消される。本発明構成の場合、絶縁膜は単
にウエハ貼り合わせ面を構成するために必要であるに過
ぎない。なお、絶縁性支持基板を採用する際、耐酸化特
性で Si よりも劣る基板材料の場合には、予めシリコン
薄膜あるいはシリコン窒化膜等で被覆しておくことによ
って、半導体製造工程で必須の高温酸化工程も不活性雰
囲気中における熱処理工程と等価となる。シリコン窒化
膜による被覆は、支持基板に含有される可能性のある有
害不純物が SOI 層即ち半導体装置に拡散するのを阻止
する作用がある。[Function] By adopting a thinner insulating film that constitutes SOI and a supporting substrate made of a material having a higher thermal conductivity than that of a Si substrate, the heat radiation resistance can be greatly reduced. Even in an ultra-high-speed semiconductor device that generates a lot of heat, ultra-high integration is possible.
Also, it is possible to avoid an increase in wiring resistance due to heat generation,
Furthermore, it becomes possible to pursue ultra-high speed operation. Further, the occurrence of parasitic capacitance due to depletion, which has been a problem in the conventional structure when the insulating film is made thin, is basically eliminated by adopting an insulating support substrate. In the case of the structure of the present invention, the insulating film is merely necessary for forming the wafer bonding surface. When using an insulating support substrate, if it is a substrate material whose oxidation resistance is inferior to that of Si, it is necessary to coat it with a silicon thin film or a silicon nitride film in advance, so that The process is also equivalent to the heat treatment process in an inert atmosphere. The coating with the silicon nitride film has a function of preventing harmful impurities that may be contained in the supporting substrate from diffusing into the SOI layer, that is, the semiconductor device.

【０００９】[0009]

【実施例】以下、本発明の内容について、実施例によっ
てさらに詳細に説明する。説明の都合上、図面を用いて
説明するが、図面では要部を拡大して示してあるので注
意を要する。また、説明を簡単にするために、実施例中
では各部の材質、半導体層の導電型、製造条件等を具体
的に例示して説明するが、本発明はこれらの例示内容に
限定されるものではない。EXAMPLES The contents of the present invention will be described in more detail below with reference to examples. For convenience of description, the description will be made with reference to the drawings, but it should be noted that the drawings show enlarged main parts. Further, in order to simplify the description, the material of each part, the conductivity type of the semiconductor layer, the manufacturing conditions and the like will be specifically illustrated and described in the examples, but the present invention is limited to these examples. is not.

【００１０】[0010]

【実施例１】図１及び図３は本発明半導体基板の一実施
例の構成及び製造工程を示した断面図である。まず、面
方位(100)、抵抗率 10Ωcm、p 導電型、厚さ525μmの直
径４インチの単結晶 Si基板１の表面に公知の熱酸化法
により 50nm厚さのシリコン酸化膜を形成した。一方、
厚さ525μmで直径４インチの窒化アルミニウム(AlN)基
板３にモノシラン(SiH₄)の620℃における化学気相反応
を施してシリコン膜４を5μmの厚さで堆積した後、1000
℃ ２時間の条件で熱処理を行い残留歪を緩和し、さら
に、公知のウエハ研磨装置に設置して平均二乗表面粗さ
0.5nm以下となるように主表面の研磨を行った。(なお、
上記熱処理後のシリコン膜４は粒径50nm程度の多結晶膜
であった)。続いて、上記研磨面と前記単結晶 Si基板の
シリコン酸化膜との直接貼り合わせを無塵状態で行い、
さらに、接着性を強化するための熱処理を1000℃ ２時
間の条件で行った後、公知の研削法及び機械的・化学的
研磨法によって、Si 基板１側から該基板の厚さが１μm
となるように制御して研削・研磨を行った。この時、面
内のSi 厚さのバラツキは±0.5μmの範囲にあった。[Embodiment 1] FIGS. 1 and 3 are cross-sectional views showing a structure and a manufacturing process of an embodiment of a semiconductor substrate of the present invention. First, a silicon oxide film having a thickness of 50 nm was formed on the surface of a 4-inch diameter single crystal Si substrate 1 having a plane orientation (100), a resistivity of 10 Ωcm, ap conductivity type and a thickness of 525 μm and a diameter of 4 inches. on the other hand,
After a chemical vapor phase reaction of monosilane (SiH ₄ ) at 620 ° C. on an aluminum nitride (AlN) substrate 3 having a thickness of 525 μm and a diameter of 4 inches, a silicon film 4 is deposited to a thickness of 5 μm, and then 1000
Heat treatment is performed under the condition of 2 ° C. for 2 hours to reduce the residual strain, and further, it is installed in a well-known wafer polishing apparatus to measure the mean square surface roughness.
The main surface was polished to have a thickness of 0.5 nm or less. (Note that
The silicon film 4 after the heat treatment was a polycrystalline film having a grain size of about 50 nm). Subsequently, the polishing surface and the silicon oxide film of the single crystal Si substrate are directly bonded in a dust-free state,
Furthermore, after heat treatment for strengthening the adhesiveness is performed at 1000 ° C. for 2 hours, the thickness of the substrate is 1 μm from the Si substrate 1 side by a known grinding method and mechanical / chemical polishing method.
Grinding / polishing was performed by controlling so that At this time, the variation in in-plane Si thickness was within ± 0.5 μm.

【００１１】上記により作成した半導体基板について、
放熱効果を検討するために、Si 基板１上に公知の半導
体製造方法により抵抗素子を形成し、通電による温度上
昇を赤外線顕微鏡により測定した。測定は水冷した試料
台に該基板を載置、真空吸引した状態で行い、なお、比
較のために、厚さ１μmのシリコン酸化膜を内部に有す
る通常の SOI 基板上に抵抗素子を形成した試料につい
ても測定を行った。その結果、70mWの消費電力で、上記
比較試料については温度上昇が27℃に達するのに対し、
本実施例試料の場合には僅か３℃の温度上昇に止まり、
優れた放熱効果を示すことが知られた。Regarding the semiconductor substrate prepared as described above,
In order to examine the heat radiation effect, a resistance element was formed on the Si substrate 1 by a known semiconductor manufacturing method, and the temperature rise due to energization was measured by an infrared microscope. The measurement is performed with the substrate placed on a water-cooled sample table and vacuum suctioned. For comparison, a sample with a resistance element formed on a normal SOI substrate having a silicon oxide film with a thickness of 1 μm inside. Was also measured. As a result, with the power consumption of 70 mW, the temperature rise of the comparative sample reaches 27 ° C.,
In the case of the sample of this example, the temperature rise was only 3 ° C.,
It has been known that it exhibits an excellent heat dissipation effect.

【００１２】[0012]

【実施例２】実施例１における窒化アルミニウム(AlN)
基板３の代りに炭化珪素(SiC)基板を用い、実施例１の
場合と同様にして半導体基板を作成した。Example 2 Aluminum nitride (AlN) in Example 1
A silicon carbide (SiC) substrate was used instead of the substrate 3, and a semiconductor substrate was prepared in the same manner as in Example 1.

【００１３】該半導体基板について実施例１の場合と同
様条件で抵抗素子の温度上昇を測定した結果、温度上昇
は10℃以下であり、従来の SOI 基板に比べて優れた放
熱特性を示す結果が得られた。なお、炭化珪素基板の代
りに熱伝導率の同等な酸化ベリリウム(ベリリア；BeO)
を用いた場合にも同様の結果が得られた。As a result of measuring the temperature rise of the resistance element on the semiconductor substrate under the same conditions as in Example 1, the temperature rise was 10 ° C. or less, and the result showing excellent heat dissipation characteristics as compared with the conventional SOI substrate was obtained. Was obtained. Note that beryllium oxide (beryria; BeO) having similar thermal conductivity is used instead of the silicon carbide substrate.
Similar results were obtained with.

【００１４】[0014]

【実施例３】図４は本発明の他の実施例の製造手順を示
す断面図で、本実施例は、単結晶Si基板１上に熱酸化膜
を形成する前に、該基板上に所望半導体装置の構成に合
わせたパターニングを施した場合の例を示す。この場
合、a) まず、パターニング深さを0.2μmとし、パター
ニングを施した後、熱酸化膜２及び21を0.1μm厚さで形
成し、さらにジシラン(Si₂H₆)を用いた化学気相反応を
温度525℃で施して、熱酸化膜21上に２μm厚さの非晶質
Si膜６を堆積させてから800℃の熱処理を施した。この
状態で、非晶質Si膜６の表面粗さは極めて良好な平坦性
を示していた。次いで、該表面を機械的研磨により平均
二乗粗さで0.5nm以下となるようにさらに平坦化し、続
いて、780℃の化学気相反応により該表面に50nm厚さの
シリコン窒化膜７を堆積した。b) 続いて、上記で得ら
れた基板を、別途準備しておいたシリコン膜４で被覆さ
れた窒化アルミニウム支持基板３と直接貼り合わせ、さ
らに接着強化熱処理を施した。c) さらに、実施例１の
場合と同様、研削と機械的・化学的研磨により Si 基板
１の薄化を行ったが、機械的・化学的研磨方法として熱
酸化膜の研磨速度がシリコンのそれに比べて桁違いに遅
い公知の選択研磨法を用いて、熱酸化膜21が露出した段
階で研磨を停止させ、選択的に Si 基板の島１を残置さ
せた。[Embodiment 3] FIG. 4 is a cross-sectional view showing a manufacturing procedure of another embodiment of the present invention. In this embodiment, before a thermal oxide film is formed on a single crystal Si substrate 1, a desired oxide film is formed on the substrate. An example of patterning according to the configuration of the semiconductor device is shown. In this case, a) First, the patterning depth is set to 0.2 μm, patterning is performed, and then thermal oxide films 2 and 21 are formed to a thickness of 0.1 μm, and chemical vapor deposition using disilane (Si ₂ H ₆ ) is performed. The reaction is performed at a temperature of 525 ° C. to form a 2 μm thick amorphous film on the thermal oxide film 21.
After depositing the Si film 6, a heat treatment at 800 ° C. was performed. In this state, the surface roughness of the amorphous Si film 6 showed extremely good flatness. Next, the surface was further planarized by mechanical polishing so that the mean square roughness was 0.5 nm or less, and then a silicon nitride film 7 having a thickness of 50 nm was deposited on the surface by chemical vapor phase reaction at 780 ° C. . b) Subsequently, the substrate obtained above was directly bonded to the separately prepared aluminum nitride supporting substrate 3 covered with the silicon film 4, and further subjected to an adhesion strengthening heat treatment. c) Further, as in the case of Example 1, the Si substrate 1 was thinned by grinding and mechanical / chemical polishing. As a mechanical / chemical polishing method, the polishing rate of the thermal oxide film was set to that of silicon. By using a well-known selective polishing method that is orders of magnitude slower than that, polishing was stopped when the thermal oxide film 21 was exposed, and the islands 1 of the Si substrate were selectively left.

【００１５】上記手順の製造方法を適用することによっ
て、図４c)に示したように、相互に酸化膜21で絶縁分離
された極薄(0.15μm)の単結晶 Si 基板１を所望個所に
予め配置して構成された半導体基板を得ることができ
た。なお、単結晶 Si 基板の島１の厚さはパターニング
深さ及び熱酸化膜の膜厚を所定値に設定することによっ
て制御することができる。なお、上記により得られた単
結晶 Si 基板の島１に形成した抵抗素子により発熱試験
を行ったが、10℃以下の温度上昇しか示さず、従来 SOI
構造の場合に比較して格段に優れた放熱特性を示し
た。By applying the manufacturing method of the above procedure, as shown in FIG. 4c), the ultra-thin (0.15 μm) single crystal Si substrate 1 which is insulated and isolated from each other by the oxide film 21 is previously formed at a desired position. It was possible to obtain a semiconductor substrate arranged and configured. The thickness of the island 1 of the single crystal Si substrate can be controlled by setting the patterning depth and the film thickness of the thermal oxide film to predetermined values. A heat resistance test was conducted using the resistance element formed on the island 1 of the single crystal Si substrate obtained above, but it showed only a temperature rise of 10 ° C or less, and the conventional SOI
Compared with the case of the structure, it showed significantly better heat dissipation characteristics.

【００１６】[0016]

【実施例４】図５は本発明のさらに他の実施例の製造手
順を示す断面図で、実施例３の場合には単結晶 Si 基板
１に所望半導体装置の構成に合わせたパターニングを施
し、全面に熱酸化膜21を形成したが、本実施例では、所
望半導体装置の構成に合わせて選択的に酸化膜21を形成
して素子間分離絶縁膜とした場合の例を示す。酸化膜21
の形成については、MOS トランジスタ領域の単結晶 Si
基板１を予め所望深さ選択的にエッチングしておき、そ
の後選択的に酸化膜21を形成しても良い。[Embodiment 4] FIG. 5 is a cross-sectional view showing a manufacturing procedure of still another embodiment of the present invention. In the case of Embodiment 3, the single crystal Si substrate 1 is patterned according to the structure of a desired semiconductor device. Although the thermal oxide film 21 is formed on the entire surface, this embodiment shows an example in which the oxide film 21 is selectively formed in accordance with the configuration of the desired semiconductor device to form the element isolation insulating film. Oxide film 21
For the formation of the
The substrate 1 may be selectively etched to a desired depth in advance, and then the oxide film 21 may be selectively formed.

【００１７】a) まず、選択的に酸化膜21を形成した
後、選択酸化に用いたシリコン窒化膜を除去し、次いで
７nm厚さのシリコン熱酸化膜を形成し、第１のゲート酸
化膜22とした。次に、バイポーラトランジスタ領域の該
ゲート酸化膜22を選択的に除去し、Si 基板１の表面を
部分的に露出させ、砒素を高濃度に添加した150nm厚の
多結晶シリコン膜８と200nm厚のタングステン珪化膜９
を全面に堆積させた。次いで、上記多結晶シリコン膜８
とタングステン珪化膜９とからなる二層膜を選択的に残
置し、所望回路構成に従った電極配線を形成してから全
面に化学気相反応による酸化膜を堆積し、表面安定化膜
10とした。さらに、化学気相反応による Si膜６の堆積
と熱処理及び平坦化研磨を施してからシリコン窒化膜７
を堆積した。ここで、上記 Si 膜６の堆積膜厚さは５μ
mに設定した。A) First, after the oxide film 21 is selectively formed, the silicon nitride film used for the selective oxidation is removed, and then a silicon thermal oxide film having a thickness of 7 nm is formed, and then the first gate oxide film 22 is formed. And Next, the gate oxide film 22 in the bipolar transistor region is selectively removed to partially expose the surface of the Si substrate 1 and the polycrystalline silicon film 8 of 150 nm thick and arsenic of high concentration and the 200 nm thick Tungsten silicide film 9
Was deposited on the entire surface. Then, the polycrystalline silicon film 8
And a tungsten silicide film 9 are selectively left, and an electrode wiring according to a desired circuit configuration is formed, and then an oxide film by chemical vapor reaction is deposited on the entire surface to form a surface stabilizing film.
It was 10. Further, after depositing the Si film 6 by chemical vapor reaction, heat treatment and planarization polishing, the silicon nitride film 7 is formed.
Was deposited. Here, the deposited film thickness of the Si film 6 is 5 μm.
set to m.

【００１８】b) 次いで、実施例３の場合と同様にして
別途準備しておいたシリコン膜４で被覆した窒化アルミ
ニウム支持基板３と上記で得られた基板との貼り合わせ
を行い、さらに、接着強化熱処理、薄化を行った。な
お、機械的・化学的研磨法としては、前記実施例３の場
合と同様に選択研磨法を用い、熱酸化膜21の面が露出し
た段階で研磨を停止させ、選択的に Si 基板の島１を残
置させた。B) Next, the aluminum nitride supporting substrate 3 coated with the silicon film 4 prepared separately in the same manner as in Example 3 and the substrate obtained above are bonded and further bonded. Strengthening heat treatment and thinning were performed. As the mechanical / chemical polishing method, the selective polishing method is used as in the case of the third embodiment, and when the surface of the thermal oxide film 21 is exposed, the polishing is stopped to selectively remove the islands of the Si substrate. 1 was left.

【００１９】本実施例構成の半導体基板においては、酸
化膜21で相互に絶縁分離された極薄(0.15μm)の単結晶
Si 基板１を予め所望個所に配置して構成された半導体
基板と該半導体基板の下部に高融点金属珪化膜による埋
め込み配線を構成することができた。なお、本実施例に
おいては、埋め込み配線として高融点金属珪化膜９と多
結晶シリコン膜８とからなる二層膜を用いた例について
示したが、埋め込み配線と半導体基板とが直接接続され
ない限り、高融点金属またはその珪化膜であっても良
い。In the semiconductor substrate having the structure of this embodiment, the ultra-thin (0.15 μm) single crystal isolated from each other by the oxide film 21 is used.
It was possible to construct a semiconductor substrate which was constructed by arranging the Si substrate 1 in a desired position in advance and a buried wiring made of a refractory metal silicide film under the semiconductor substrate. In this embodiment, an example in which a two-layer film composed of the refractory metal silicide film 9 and the polycrystalline silicon film 8 is used as the embedded wiring is shown, but unless the embedded wiring and the semiconductor substrate are directly connected, It may be a refractory metal or a silicified film thereof.

【００２０】なお、本実施例の半導体基板についても、
単結晶 Si 基板の島１に構成した抵抗素子による発熱試
験を行ったが、10℃以下の昇温しか示さず、従来の SOI
構造よりも格段に優れた放熱特性を示した。The semiconductor substrate of this embodiment also has
A heat generation test was conducted using a resistance element configured on island 1 of a single crystal Si substrate, but it showed only a temperature rise of 10 ° C or less, and the conventional SOI
The heat dissipation characteristics were far superior to the structure.

【００２１】[0021]

【実施例５】実施例３によって得られた半導体基板(図
４ c))のSi 基板１の領域に公知のMOS トランジスタ製
造工程を用いて MOS トランジスタを形成した。なお、
本実施例の場合、Si 基板１の厚さは80nmとなるように
設定した。Fifth Embodiment A MOS transistor is formed in the region of the Si substrate 1 of the semiconductor substrate (FIG. 4c) obtained in the third embodiment by using a known MOS transistor manufacturing process. In addition,
In the case of this example, the thickness of the Si substrate 1 was set to be 80 nm.

【００２２】本実施例のトランジスタにおいては、Si
基板の厚さが空乏層の厚さ以下となるために、ドレイン
強電界のゲート電界に及ぼす影響いわゆる二次元効果が
実効的に緩和され、短チャンネル効果の改善及び大電流
化が実現できた。さらに、発熱も、従来の SOI 構造ト
ランジスタの場合に比べて格段に低減された。In the transistor of this embodiment, Si
Since the thickness of the substrate is less than the thickness of the depletion layer, the effect of the drain strong electric field on the gate electric field, so-called two-dimensional effect, is effectively alleviated, and the improvement of the short channel effect and the increase in current can be realized. In addition, heat generation was also significantly reduced compared to the conventional SOI structure transistor.

【００２３】[0023]

【実施例６】図６は本発明半導体装置の一実施例の構成
を示した断面図である。本実施例の場合、前記実施例４
で得られた半導体基板を用い、図５において埋め込み配
線の多結晶シリコン膜に添加した砒素を貼り合わせ工程
後の熱処理工程によって Si基板１底面の接続領域から
拡散させ、N 型高濃度領域19を形成した。次に、領域19
を形成した Si 基板１領域に公知のバイポーラトランジ
スタ製造方法によってベース拡散層20、N 型高濃度エミ
ッタ拡散層23、多結晶シリコン膜16とタングステン珪化
膜17の重ね膜で構成されるベース取り出し電極、配線層
間絶縁膜18、エミッタ電極23等を形成した。ここで、Si
基板１領域と直接接続された埋込配線８及び９はコレ
クタ引出し電極として働く。さらに、埋込配線と直接接
続されていない Si 基板１領域について公知の MOS ト
ランジスタ製造方法によってソース拡散層14、ドレイン
拡散層15、ゲート絶縁膜11、多結晶シリコン膜12とタン
グステン珪化膜17の重ね膜で構成されるゲート電極、ソ
ース電極25等を形成して、バイポーラトランジスタと M
OS トランジスタとが混在する半導体装置を作成した。[Embodiment 6] FIG. 6 is a sectional view showing the structure of an embodiment of the semiconductor device of the present invention. In the case of this embodiment, the fourth embodiment
Using the semiconductor substrate obtained in step 5, the arsenic added to the polycrystalline silicon film of the buried wiring in FIG. 5 is diffused from the connection region on the bottom surface of the Si substrate 1 by the heat treatment process after the bonding process to form the N-type high concentration region 19. Formed. Then area 19
In the region of the Si substrate 1 in which the substrate is formed, the base diffusion layer 20, the N-type high-concentration emitter diffusion layer 23, the base extraction electrode composed of the stacked film of the polycrystalline silicon film 16 and the tungsten silicide film 17, are formed by a known bipolar transistor manufacturing method, The wiring interlayer insulating film 18, the emitter electrode 23, etc. were formed. Where Si
The buried wirings 8 and 9 directly connected to the substrate 1 region function as collector extraction electrodes. Further, the source diffusion layer 14, the drain diffusion layer 15, the gate insulating film 11, the polycrystalline silicon film 12 and the tungsten silicide film 17 are stacked on each other in the Si substrate 1 region which is not directly connected to the buried wiring by a known MOS transistor manufacturing method. Form the gate electrode, source electrode 25, etc. composed of a film, and
We have created a semiconductor device in which OS transistors are mixed.

【００２４】上記により製造した半導体装置において
は、コレクタ引出電極を半導体層の底面に形成できるた
め、トランジスタ占有面積を従来構造に比べ約 2／3以
下に低減させることができた。また、MOS トランジスタ
においても、埋込電極を第二のゲート電極として使用で
きるため、Si 基板１全体を電流経路として制御するこ
とができ、従来構造に比べて駆動可能電流を５倍以上と
大電流化することができた。さらに、本実施例半導体装
置は、従来構成の SOI トランジスタと比較して放熱特
性に優れており、発熱を格段に低減することができた。In the semiconductor device manufactured as described above, since the collector extraction electrode can be formed on the bottom surface of the semiconductor layer, the area occupied by the transistor can be reduced to about 2/3 or less as compared with the conventional structure. Also, in the MOS transistor, since the embedded electrode can be used as the second gate electrode, the entire Si substrate 1 can be controlled as a current path, and the drivable current is 5 times or more that of the conventional structure. I was able to Furthermore, the semiconductor device of this example is superior in heat dissipation characteristics to the SOI transistor having the conventional configuration, and the heat generation can be significantly reduced.

【００２５】[0025]

【実施例７】図７に本発明半導体装置の他の実施例を示
す。この場合、まず、a) 単結晶半導体基板に公知の手
法により半導体装置を作成した通常の Si 基板１を、別
途準備した研磨支持治具30にワックス31で接着し、裏面
から研削と研磨により薄化した。ここで、研磨は実施例
５に記載した選択研磨法を用い、素子間分離絶縁膜21の
底面が露出した段階で研磨を終了し、Si 基板１の活性
領域のみを選択的に残置させた。b) 続いて、上記 Si
基板１を、プラズマ雰囲気中の低温化学気相反応により
研磨面に表面安定化絶縁膜を薄く堆積した後表面を平坦
に研磨した500μm厚さの炭化珪素基板３に接着剤32を用
いて接着し、次いで、100℃に加熱してワックスを研磨
支持治具から剥離させ、さらに、ワックス溶剤による洗
浄を行ってワックスを完全に除去して半導体装置を完成
した。Seventh Embodiment FIG. 7 shows another embodiment of the semiconductor device of the present invention. In this case, first, a) a normal Si substrate 1 in which a semiconductor device is formed on a single crystal semiconductor substrate by a known method is bonded to a separately prepared polishing support jig 30 with wax 31, and thinned by grinding and polishing from the back surface. Turned into Here, the selective polishing method described in Example 5 was used for polishing, and the polishing was terminated when the bottom surface of the element isolation insulating film 21 was exposed, and only the active region of the Si substrate 1 was left selectively. b) Then, the above Si
The substrate 1 is adhered using an adhesive 32 to a 500 μm thick silicon carbide substrate 3 having a surface-stabilized insulating film thinly deposited on the polished surface by a low temperature chemical vapor reaction in a plasma atmosphere and then the surface is polished flat. Then, the wax was peeled off from the polishing support jig by heating at 100 ° C., and further, the wax was washed to completely remove the wax to complete the semiconductor device.

【００２６】本実施例における半導体装置は、上記実施
例６の場合と異なり、高熱伝導率基板３との貼り合わせ
の前に、Si 基板１にすべての高温熱処理を含む半導体
装置作成工程を施しているので、拡散層の不純物分布制
御等について従来の製造条件をなんら変更する必要がな
く、放熱特性に優れた SOI 構造の半導体装置の作成を
簡便にかつ安価に実現することができた。In the semiconductor device of this embodiment, unlike the case of the above-described sixth embodiment, the Si substrate 1 is subjected to a semiconductor device manufacturing process including all high-temperature heat treatments before being bonded to the high thermal conductivity substrate 3. Therefore, it is not necessary to change the conventional manufacturing conditions for controlling the impurity distribution of the diffusion layer and the like, and it has been possible to easily and inexpensively manufacture a semiconductor device having an SOI structure having excellent heat dissipation characteristics.

【００２７】[0027]

【実施例８】図８に本発明の半導体装置を用いた計算機
の構成図を示す。すなわち、本発明半導体装置を、命令
や演算を処理するプロセッサ500を複数個並列に接続し
た高速大型計算機に適用した場合の例である。本発明を
実施した高速半導体装置は放熱性に優れかつ高集積化が
可能であるため、命令や演算を処理するプロセッサ50
0、記憶制御装置501、主記憶装置502などを、一辺が約1
0〜30mmのチップ上に構成することができた。これらプ
ロセッサ500と記憶制御装置501と、化合物半導体集積回
路からなるデータ通信インタフェース503とを同一水冷
基板506に実装した。また、データ通信インタフェース5
03とデータ通信制御装置504とを同一水冷基板507に実装
した。これら水冷基板506並びに507と、主記憶装置502
を実装した水冷基板とを大きさが一辺約50cm程度あるい
はそれ以下の基板に実装して、大型計算機の中央処理ユ
ニット508を形成した。この中央処理ユニット508内デー
タ通信や、複数の中央処理ユニット間のデータ通信、あ
るいはデータ通信インタフェース503と入出力プロセッ
サ505を実装した基板509との間のデータ通信は、図中の
両端矢印線で示した光ファイバ501を介して行われる。Eighth Embodiment FIG. 8 is a block diagram of a computer using the semiconductor device of the present invention. That is, this is an example in which the semiconductor device of the present invention is applied to a high-speed large-scale computer in which a plurality of processors 500 for processing instructions and operations are connected in parallel. Since the high-speed semiconductor device embodying the present invention has excellent heat dissipation and can be highly integrated, a processor 50 for processing instructions and operations
0, storage control device 501, main storage device 502, etc.
It could be configured on a chip of 0-30 mm. The processor 500, the storage controller 501, and the data communication interface 503 composed of a compound semiconductor integrated circuit are mounted on the same water-cooled substrate 506. In addition, the data communication interface 5
03 and the data communication control device 504 are mounted on the same water-cooled board 507. These water-cooled substrates 506 and 507, and the main storage device 502
The water-cooled board on which is mounted is mounted on a board having a side of about 50 cm or less, and a central processing unit 508 of a large-scale computer is formed. The data communication in the central processing unit 508, the data communication between a plurality of central processing units, or the data communication between the data communication interface 503 and the board 509 on which the input / output processor 505 is mounted is indicated by double-ended arrow lines in the figure. This is done via the illustrated optical fiber 501.

【００２８】この計算機では、命令や演算を処理するプ
ロセッサ500や記憶制御装置501や主記憶装置502などの
半導体装置が並列に高速で動作し、また、データの通信
を光を媒体として行うこととしたため、１秒間当りの命
令処理回数を大幅に増加することができた。In this computer, semiconductor devices such as a processor 500 for processing instructions and operations, a storage control device 501, a main storage device 502, and the like operate in parallel at high speed, and data communication is performed using light as a medium. As a result, the number of instruction processings per second can be significantly increased.

【００２９】[0029]

【発明の効果】以上述べてきたように、半導体基板及び
半導体装置とその製造方法を本発明構成の内容とするこ
とによって、従来技術の有していた課題を解決して、放
熱特性に優れ、動作時の発熱に起因する配線抵抗の増大
や信頼性の低下を防ぎ、半導体装置の大電流動作化、高
速化、高集積化を可能にする構成の半導体基板及び半導
体装置とその製造方法を提供することができた。また、
本発明に基づく半導体装置においては、寄生容量の増加
なしに高信頼度の SOI 構造を提供することができ、α
線照射による誤動作、ラッチアップ現象と呼ばれる隣接
素子間干渉等を完全に防止できる効果がある。As described above, by incorporating the semiconductor substrate and the semiconductor device and the manufacturing method thereof into the contents of the constitution of the present invention, the problems which the prior art has had are solved and the heat dissipation characteristics are excellent. Provided are a semiconductor substrate and a semiconductor device having a configuration capable of preventing an increase in wiring resistance and a decrease in reliability due to heat generation during operation and enabling high current operation, high speed, and high integration of the semiconductor device, and a manufacturing method thereof. We were able to. Also,
In the semiconductor device according to the present invention, a highly reliable SOI structure can be provided without increasing parasitic capacitance.
This has the effect of completely preventing malfunctions due to radiation of rays and interference between adjacent elements called a latch-up phenomenon.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明半導体基板の一実施例の構成を示す断面
図。FIG. 1 is a sectional view showing a configuration of an embodiment of a semiconductor substrate of the present invention.

【図２】従来の半導体基板の構成を示す断面図。FIG. 2 is a sectional view showing the structure of a conventional semiconductor substrate.

【図３】本発明の実施例１の半導体基板の製造工程を示
す断面図。FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor substrate according to the first embodiment of the present invention.

【図４】本発明の実施例３の半導体基板の製造工程を示
す断面図。FIG. 4 is a sectional view showing a manufacturing process of a semiconductor substrate according to a third embodiment of the present invention.

【図５】本発明の実施例４の半導体基板の製造工程を示
す断面図。FIG. 5 is a sectional view showing a manufacturing process of a semiconductor substrate according to a fourth embodiment of the present invention.

【図６】本発明の実施例６の半導体装置の製造工程を示
す断面図。FIG. 6 is a sectional view showing a manufacturing process of a semiconductor device according to a sixth embodiment of the present invention.

【図７】本発明の実施例７の半導体装置の製造工程を示
す断面図。FIG. 7 is a sectional view showing a manufacturing process of a semiconductor device according to a seventh embodiment of the present invention.

【図８】本発明の半導体装置を用いた実施例８の計算機
構成を示す構成図。FIG. 8 is a configuration diagram showing a computer configuration of an eighth embodiment using the semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

１…単結晶 Si 基板、２… SOI 構造を構成する第１の
絶縁膜、３…半導体基板よりも熱伝導率の大きな支持基
板、４…支持基板を保護する第１の薄膜、５…Si 支持
基板、６…Si 膜、７…シリコン窒化膜、８…配線を構
成する埋込多結晶 Si 膜、９…配線を構成する埋込金属
珪化膜、10…配線保護絶縁膜、11…ゲート絶縁膜、12…
配線を構成する多結晶 Si 膜、13…配線を構成する金属
珪化膜、14…ソース拡散層、15…ドレイン拡散層、16…
配線を構成する多結晶 Si 膜、17…配線を構成する金属
珪化膜、18…配線保護絶縁膜、19…コレクタ拡散層、20
…ベース拡散層、21…熱酸化膜、22…ゲート酸化膜、23
…エミッタ拡散層、24…エミッタ電極、25…ソース電
極、26…引出電極、30…研磨支持治具、31…ワックス、
32…接着剤、500…命令や演算を処理するプロセッサ、5
01…記憶制御装置、502…主記憶装置、503…データ通信
インタフェース、504…データ通信制御装置、505…入出
力プロセッサ、506、507…セラミック基板、508…中央
処理ユニット、509…入出力プロセッサ実装基板、510…
データ通信用光ファイバ。DESCRIPTION OF SYMBOLS 1 ... Single crystal Si substrate, 2 ... 1st insulating film which comprises SOI structure, 3 ... Support substrate with a larger thermal conductivity than a semiconductor substrate, 4 ... 1st thin film which protects a support substrate, 5 ... Si support Substrate, 6 ... Si film, 7 ... Silicon nitride film, 8 ... Buried polycrystalline Si film forming wiring, 9 ... Buried metal silicide film forming wiring, 10 ... Wiring protective insulating film, 11 ... Gate insulating film , 12 ...
Polycrystalline Si film forming wiring, 13 ... Metal silicide film forming wiring, 14 ... Source diffusion layer, 15 ... Drain diffusion layer, 16 ...
Polycrystalline Si film forming wiring, 17 ... Metal silicide film forming wiring, 18 ... Wiring protective insulating film, 19 ... Collector diffusion layer, 20
… Base diffusion layer, 21… Thermal oxide film, 22… Gate oxide film, 23
... emitter diffusion layer, 24 ... emitter electrode, 25 ... source electrode, 26 ... extraction electrode, 30 ... polishing support jig, 31 ... wax,
32 ... Adhesive, 500 ... Processor that processes instructions and operations, 5
01 ... Storage control device, 502 ... Main storage device, 503 ... Data communication interface, 504 ... Data communication control device, 505 ... Input / output processor, 506, 507 ... Ceramic substrate, 508 ... Central processing unit, 509 ... Input / output processor implementation Substrate, 510 ...
Optical fiber for data communication.

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】第１の基板と、該基板の少なくとも主表面
を被覆するように設けた第１の薄膜と、該薄膜上に設け
た第１の絶縁膜と、該絶縁膜上に設けた単結晶半導体層
とから構成される半導体基板において、上記第１の基板
の熱伝導率を上記単結晶半導体層の熱伝導率よりも大と
したことを特徴とする半導体基板。1. A first substrate, a first thin film provided so as to cover at least the main surface of the substrate, a first insulating film provided on the thin film, and provided on the insulating film. A semiconductor substrate comprising a single crystal semiconductor layer, wherein the first substrate has a thermal conductivity higher than that of the single crystal semiconductor layer. 【請求項２】上記第１の基板が窒化アルミニウム、炭化
珪素、酸化ベリリウムの何れかから構成されていること
を特徴とする請求項１記載の半導体基板。2. The semiconductor substrate according to claim 1, wherein the first substrate is made of any one of aluminum nitride, silicon carbide and beryllium oxide. 【請求項３】上記単結晶半導体層が第２の絶縁膜により
互いに分離されてなる単結晶半導体層であることを特徴
とする請求項１及び２記載の半導体基板。3. The semiconductor substrate according to claim 1, wherein the single crystal semiconductor layer is a single crystal semiconductor layer separated from each other by a second insulating film. 【請求項４】上記単結晶半導体層と上記第１の絶縁膜と
の間、または、上記第１の絶縁膜中に、少なくとも半導
体膜、高融点金属膜あるいは高融点金属珪化膜の何れか
で構成される配線層を具備していることを特徴とする請
求項３記載の半導体基板。4. A semiconductor film, a refractory metal film or a refractory metal silicide film at least between the single crystal semiconductor layer and the first insulation film or in the first insulation film. The semiconductor substrate according to claim 3, further comprising a wiring layer configured. 【請求項５】請求項３または４に記載の半導体基板の単
結晶半導体層上に構成されていることを特徴とする半導
体装置。5. A semiconductor device, which is formed on the single crystal semiconductor layer of the semiconductor substrate according to claim 3 or 4. 【請求項６】半導体装置を形成した半導体基板を裏面か
ら研磨して薄層化する工程と、上記半導体基板よりも熱
伝導率が大である支持基板と上記半導体基板とを少なく
とも接着層を介して貼りあわせる工程とからなることを
特徴とする半導体装置の製造方法。6. A step of polishing a semiconductor substrate on which a semiconductor device is formed by polishing from the back surface to form a thin layer, and a supporting substrate having a thermal conductivity higher than that of the semiconductor substrate and the semiconductor substrate at least with an adhesive layer interposed therebetween. A method of manufacturing a semiconductor device, comprising the steps of: