JPH0521458A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0521458A JPH0521458A JP17082391A JP17082391A JPH0521458A JP H0521458 A JPH0521458 A JP H0521458A JP 17082391 A JP17082391 A JP 17082391A JP 17082391 A JP17082391 A JP 17082391A JP H0521458 A JPH0521458 A JP H0521458A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- conductivity type
- polycrystalline silicon
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置およびその製
造方法に関し、特にＬＯＣＯＳ酸化膜とサイドウォール
酸化膜とを有するＬＤＤ構造のＭＯＳトランジスタおよ
びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an LDD structure MOS transistor having a LOCOS oxide film and a sidewall oxide film and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】図３に示す断面図を用いて、従来のＬＯ
ＣＯＳ酸化膜とサイドウォール酸化膜とを有するＬＤＤ
構造のＰチャネルＭＯＳトランジスタの構造，および製
造方法も説明する。まず、Ｎ型シリコン基板１表面にＬ
ＯＣＯＳ酸化膜２，ゲート絶縁膜３，ゲート電極４ｂを
形成した後、Ｐ- 拡散層５を形成する。次に、ゲート電
極４ｂの側面にサイドウォール酸化膜を形成した後、Ｐ
+ 拡散層９を形成する。続いて、全面に層間絶縁膜１０
を堆積し、コンタクト穴１１を開口した後、配線電極１
２を形成する。2. Description of the Related Art A conventional LO is shown in FIG.
LDD having COS oxide film and sidewall oxide film
A structure of a P-channel MOS transistor having a structure and a manufacturing method will also be described. First, L on the surface of the N-type silicon substrate 1
After the OCOS oxide film 2, the gate insulating film 3 and the gate electrode 4b are formed, the P − diffusion layer 5 is formed. Next, after forming a sidewall oxide film on the side surface of the gate electrode 4b, P
+ Diffusion layer 9 is formed. Then, the interlayer insulating film 10 is formed on the entire surface.
After depositing and opening the contact hole 11, the wiring electrode 1
Form 2.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来のＬＯＣ
ＯＳ酸化膜とサイドウォール酸化膜とを有するＬＤＤ構
造のＭＯＳトランジスタにおいて、さらに微細なＭＯＳ
トランジスタを実現しようとする場合、特にドレイン側
の拡散層の接合が深いと短チャネル効果が起りやすくな
り、チャネル長の減少とのもにゲートしきい値電圧，ド
レイン耐圧が低下する。これにより、サブスレッショル
ド電流やパンチスルー電流が増加し、このＭＯＳトラン
ジスタの電気特性を劣化させることになる。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In a MOS transistor having an LDD structure having an OS oxide film and a sidewall oxide film, a finer MOS
When a transistor is to be realized, a short channel effect is likely to occur particularly when the junction of the diffusion layer on the drain side is deep, and the gate threshold voltage and the drain breakdown voltage are reduced in addition to the decrease in the channel length. As a result, the subthreshold current and punchthrough current increase, and the electrical characteristics of this MOS transistor are degraded.
【０００４】特にＰチャネルＭＯＳトランジスタにおい
ては、拡散不純物としてボロンを使用するため、Ｎチャ
ネルＭＯＳトランジスタに拡散不純物として使用する砒
素で実現できる接合深さ（０．２−０．３μｍ）に比べ
てボロンは格段に拡散係数が大きく、さらにイオン注入
では低エネルギー注入が難かしく、接合深さは０．３５
−０．４５μｍになるという問題点があった。Particularly in a P-channel MOS transistor, since boron is used as a diffusion impurity, boron is used as a diffusion impurity in the N-channel MOS transistor, compared with a junction depth (0.2-0.3 μm) which can be realized by arsenic. Has a remarkably large diffusion coefficient, and low energy implantation is difficult with ion implantation, and the junction depth is 0.35.
There is a problem that it becomes −0.45 μm.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
一導電型の半導体基板に形成されたＬＯＣＯＳ酸化膜と
サイドウォール酸化膜とを有するＬＤＤ構造のＭＯＳト
ランジスタにおいて、ポリサイド構造のゲート電極と、
ＬＯＣＯＳ酸化膜とサイドウォール酸化膜とに囲まれた
半導体基板上に設けられた逆導電型の高濃度不純物が添
加された多結晶シリコン膜と、半導体基板表面に多結晶
シリコン膜と自己整合的に形成された逆導電型高濃度拡
散層と、を有している。The semiconductor device of the present invention comprises:
In a MOS transistor of LDD structure having a LOCOS oxide film and a sidewall oxide film formed on a semiconductor substrate of one conductivity type, a gate electrode of polycide structure,
A polycrystalline silicon film, which is provided on a semiconductor substrate surrounded by a LOCOS oxide film and a sidewall oxide film and is doped with a high concentration impurity of the opposite conductivity type, and a polycrystalline silicon film on the surface of the semiconductor substrate in a self-aligned manner with the polycrystalline silicon film. And the formed reverse-conductivity-type high-concentration diffusion layer.
【０００６】また本発明の半導体装置の製造方法では、
一導電型の半導体基板に形成されたＬＤＤ構造のＭＯＳ
トランジスタの製造方法において、半導体基板上にＬＯ
ＣＯＳ酸化膜，ゲート絶縁膜，ポリサイド構造のゲート
電極を形成し、逆導電型低濃度拡散層を形成し、ゲート
電極の側面にサイドウォール酸化膜を形成する工程と、
全面に多結晶シリコン膜を堆積し、全面にフォトレジス
ト膜を形成し、エッチバック法によりＬＯＣＯＳ酸化膜
とサイドウォール酸化膜とにより囲まれた逆導電型低濃
度拡散層上にのみこの多結晶シリコン膜を残留させる工
程と、高濃度の逆導電型不純物のイオン注入を行ない、
熱処理を行ない、ＬＯＣＯＳ酸化膜とサイドウォール酸
化膜とにより囲まれた半導体基板表面に逆導電型高濃度
拡散層を形成する工程と、を有している。According to the method of manufacturing a semiconductor device of the present invention,
LDD structure MOS formed on one conductivity type semiconductor substrate
In a method of manufacturing a transistor, LO on a semiconductor substrate
A step of forming a COS oxide film, a gate insulating film, a gate electrode having a polycide structure, forming a low-concentration diffusion layer of opposite conductivity type, and forming a sidewall oxide film on a side surface of the gate electrode;
A polycrystalline silicon film is deposited on the entire surface, a photoresist film is formed on the entire surface, and this polycrystalline silicon is formed only on the reverse conductivity type low concentration diffusion layer surrounded by the LOCOS oxide film and the sidewall oxide film by the etch back method. The step of leaving the film and the ion implantation of high-concentration reverse conductivity type impurities are performed,
Heat treatment is performed to form an opposite conductivity type high concentration diffusion layer on the surface of the semiconductor substrate surrounded by the LOCOS oxide film and the sidewall oxide film.
【０００７】[0007]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【０００８】図１に示す工程順の断面図を用いて、本発
明の第１の実施例を製造工程に沿って説明する。A first embodiment of the present invention will be described along the manufacturing process with reference to sectional views in the order of processes shown in FIG.
【０００９】まず、Ｎ型シリコン基板１表面に選択的に
ＬＯＣＯＳ酸化膜２を形成し、ゲート絶縁膜３を形成し
た後、ポリサイド構造のゲート電極４ａを形成する。ボ
ロンのイオン注入により、ゲート電極４ａに自己整合的
なＰ- 拡散層５を形成する。ＣＶＤ法により全面にシリ
コン酸化膜を堆積し、それをエッチバックしてゲート電
極４ａの側面にサイドウォール酸化膜６を形成する〔図
１（ａ）〕。First, a LOCOS oxide film 2 is selectively formed on the surface of an N-type silicon substrate 1, a gate insulating film 3 is formed, and then a gate electrode 4a having a polycide structure is formed. By ion implantation of boron, a P − diffusion layer 5 self-aligned with the gate electrode 4a is formed. A silicon oxide film is deposited on the entire surface by the CVD method and is etched back to form a sidewall oxide film 6 on the side surface of the gate electrode 4a [FIG. 1 (a)].
【００１０】次に、ＣＶＤ法により全面にノンドープの
多結晶シリコン膜７を堆積し、全面にフォトレジスト膜
８を塗布，形成する〔図１（ｂ）〕。続いて、エッチバ
ックを行なう。途中段階で、Ｐ- 拡散層５上にのみフォ
トレジスト膜７ａが残る〔図１（ｃ）〕。フォトレジス
ト膜７ａをマスクとした多結晶シリコン膜７のエッチン
グ，フォトレジスト膜７ａの除去を行なう。あるいは、
ＬＯＣＯＳ酸化膜２上，およびゲート電極４ａ上の多結
晶シリコン膜７が除去されるまでエッチバックを続行
し、フォトレジスト膜７ａの除去を行なってもよい。Next, a non-doped polycrystalline silicon film 7 is deposited on the entire surface by the CVD method, and a photoresist film 8 is applied and formed on the entire surface [FIG. 1 (b)]. Then, etch back is performed. At the intermediate stage, the photoresist film 7a remains only on the P − diffusion layer 5 [FIG. 1 (c)]. The polycrystalline silicon film 7 is etched using the photoresist film 7a as a mask, and the photoresist film 7a is removed. Alternatively,
Etchback may be continued until the polycrystalline silicon film 7 on the LOCOS oxide film 2 and the gate electrode 4a is removed, and the photoresist film 7a may be removed.
【００１１】本実施例では、ゲート電極４ａがポリサイ
ド構造であることから、多結晶シリコン膜７のエッチン
グ，もしくはエッチバックに際して、ゲート電極４ａが
エッチングされることはない。In this embodiment, since the gate electrode 4a has a polycide structure, the gate electrode 4a is not etched when the polycrystalline silicon film 7 is etched or etched back.
【００１２】次に、高濃度のボロンのイオン注入を行な
い、Ｐ- 拡散層５上にのみ残留している多結晶シリコン
膜７をＰ+ 型の多結晶シリコン膜７ａに変換する。９０
０℃，２−３分の熱処理を行ない、ＮチャネルＭＯＳト
ランジスタと同等な０．２−０．３μｍの浅い接合深さ
のＰ+ 拡散層９を形成する〔図１（ｄ）〕。次に、ＣＶ
Ｄ法により全面に層間絶縁膜１０を堆積し、コンタクト
穴１１を開口し、配線電極１２を形成する〔図１
（ｅ）〕。Next, high concentration boron ion implantation is performed to convert the polycrystalline silicon film 7 remaining only on the P − diffusion layer 5 into a P + type polycrystalline silicon film 7a. 90
A heat treatment is performed at 0 ° C. for 2-3 minutes to form a P + diffusion layer 9 having a shallow junction depth of 0.2-0.3 μm, which is equivalent to that of an N-channel MOS transistor [FIG. 1 (d)]. Next, CV
An interlayer insulating film 10 is deposited on the entire surface by the D method, contact holes 11 are opened, and wiring electrodes 12 are formed [FIG.
(E)].
【００１３】図２は本発明の第２の実施例を説明するた
めの主要工程の断面図である。本実施例は、図１（ｄ）
に示した工程までは第１の実施例と同じである。FIG. 2 is a sectional view of the main steps for explaining the second embodiment of the present invention. This embodiment is shown in FIG.
Up to the step shown in (4), it is the same as in the first embodiment.
【００１４】Ｐ+ 拡散層９を形成を形成した後、まず、
全面に例えばタングステン膜，チタン膜，あるいはモリ
ブデン膜等の高融点金属膜１３を堆積する〔図２
（ａ）〕。After forming the P + diffusion layer 9, first,
A refractory metal film 13 such as a tungsten film, a titanium film, or a molybdenum film is deposited on the entire surface [FIG.
(A)].
【００１５】次に、不活性雰囲気中でランプアニール等
の熱処理を行ない、多結晶シリコン膜７ａと高融点金属
膜１３とのシリサイド化反応を行ない、高融点金属シリ
サイド膜１４を形成する。続いて、未反応の高融点金属
膜１３をエッチング除去する〔図２（ｂ）〕。Next, heat treatment such as lamp annealing is performed in an inert atmosphere to cause a silicidation reaction between the polycrystalline silicon film 7a and the refractory metal film 13 to form a refractory metal silicide film 14. Subsequently, the unreacted refractory metal film 13 is removed by etching [FIG. 2 (b)].
【００１６】次に、第１の実施例と同様に、ＣＶＤ法に
より全面に層間絶縁膜を堆積し、コンタクト穴を開口
し、配線電極を形成する。Next, as in the first embodiment, an interlayer insulating film is deposited on the entire surface by the CVD method, contact holes are opened, and wiring electrodes are formed.
【００１７】なお、図２（ｂ）では多結晶シリコン膜７
ａの全てが高融点金属膜１３と反応している場合を図示
してあるが、多結晶シリコン膜７ａの全てが反応しない
で多結晶シリコン膜７ａと高融点金属シリサイド膜１４
との２層構造膜となる場合もある。またこのシリサイド
化反応により、ポリサイド構造のゲート電極ａ上にも新
たに高融点金属シリサイド膜が形成されるが、Ｐ+ 拡散
層９上に形成される高融点金属シリサイド膜１４より膜
厚が薄いため図示は省略する。In FIG. 2B, the polycrystalline silicon film 7 is used.
Although a case where all of a reacts with the refractory metal film 13 is illustrated, all of the polycrystalline silicon film 7a does not react and the polycrystalline silicon film 7a and the refractory metal silicide film 14 are not reacted.
In some cases, it may be a two-layer structure film. Further, due to this silicidation reaction, a refractory metal silicide film is newly formed on the gate electrode a having a polycide structure, but the film thickness is smaller than that of the refractory metal silicide film 14 formed on the P + diffusion layer 9. Therefore, illustration is omitted.
【００１８】本実施例は第１の実施例に比べて、接合の
深さの浅いＰ+ 拡散層９により必然的に増大する拡散抵
抗を、高融点金属シリサイド膜１４の形成により下げる
ことができる。Compared to the first embodiment, this embodiment can reduce the diffusion resistance which is necessarily increased by the P + diffusion layer 9 having a shallow junction depth by forming the refractory metal silicide film 14. .
【００１９】[0019]
【発明の効果】以上説明したように本発明は、一導電型
の半導体基板に形成されたＬＤＤ構造のＭＯＳトランジ
スタにおいて、ポリサイド構造のゲート電極を設け、Ｌ
ＯＣＯＳ酸化膜とサイドウォール酸化膜とに囲まれた半
導体基板上に逆導電型の高濃度不純物が添加された多結
晶シリコン膜を設け、半導体基板表面にこの多結晶シリ
コン膜からの不純物拡散によりこの多結晶シリコン膜と
自己整合的に逆導電型高濃度拡散層を形成することによ
り、接合の深さの浅い逆導電型高濃度拡散層を設けるこ
と可能となり、ゲートしきい値電圧およびドレイン耐圧
が低下，サブスレッショルド電流やパンチスルー電流に
よりトランジスタの電気特性を劣化を抑制することがで
きる。As described above, according to the present invention, in a MOS transistor of LDD structure formed on a semiconductor substrate of one conductivity type, a gate electrode of polycide structure is provided and L
A polycrystalline silicon film doped with a high-concentration impurity of the opposite conductivity type is provided on a semiconductor substrate surrounded by an OCOS oxide film and a sidewall oxide film, and the impurity is diffused from the polycrystalline silicon film to the surface of the semiconductor substrate. By forming the reverse-conductivity-type high-concentration diffusion layer in a self-aligned manner with the polycrystalline silicon film, it becomes possible to provide the reverse-conductivity-type high-concentration diffusion layer having a shallow junction depth, and the gate threshold voltage and drain withstand voltage can be reduced. It is possible to suppress the deterioration of the electrical characteristics of the transistor due to the decrease, the subthreshold current and the punchthrough current.
【００２０】この効果は、特にＰチャネルＭＯＳトラン
ジスタにおいて顕著である。This effect is particularly remarkable in the P-channel MOS transistor.
【図１】本発明の第１の実施例を説明するための工程順
の断面図である。1A to 1D are cross-sectional views in order of processes for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明するための主要工
程の断面図である。FIG. 2 is a cross-sectional view of a main process for explaining a second embodiment of the present invention.
【図３】従来のＬＤＤ構造のＰチャネルＭＯＳトランジ
スタおよびその製造方法を説明するための工程順の断面
図である。3A to 3D are cross-sectional views in order of processes for explaining a conventional P-channel MOS transistor having an LDD structure and a method for manufacturing the same.
１ Ｎ型シリコン基板 ２ ＬＯＣＯＳ酸化膜 ３ ゲート絶縁膜 ４ａ，４ｂ ゲート電極 ５ Ｐ- 拡散層 ６ サイドウォール酸化膜 ７，７ａ 多結晶シリコン膜 ８，８ａ フォトレジスト膜 ９ Ｐ+ 拡散層 １０ 層間絶縁膜 １１ コンタクト穴 １２ 配線電極 １３ 高融点金属膜 １４ 高融点金属シリサイド膜1 N-type silicon substrate 2 LOCOS oxide film 3 gate insulating films 4a and 4b gate electrode 5 P - diffusion layer 6 sidewall oxide films 7 and 7a polycrystalline silicon film 8 and 8a photoresist film 9 P + diffusion layer 10 interlayer insulating film 11 Contact Hole 12 Wiring Electrode 13 Refractory Metal Film 14 Refractory Metal Silicide Film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/28 ３０１ Ｔ 7738−4Ｍ 21/90 Ｃ 7353−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication location H01L 21/28 301 T 7738-4M 21/90 C 7353-4M
Claims (4)
ＣＯＳ酸化膜とサイドウォール酸化膜とを有するＬＤＤ
構造のＭＯＳトランジスタにおいて、 ポリサイド構造のゲート電極と、 前記サイドウォール酸化膜と前記ＬＯＣＯＳ酸化膜とに
囲まれた前記半導体基板上に設けられた逆導電型の高濃
度不純物が添加された多結晶シリコン膜と、 前記半導体基板表面に前記多結晶シリコン膜と自己整合
的に形成された逆導電型高濃度拡散層と、 を有することを特徴とする半導体装置。1. An LO formed on a semiconductor substrate of one conductivity type
LDD having COS oxide film and sidewall oxide film
In a MOS transistor having a structure, a reverse conductivity type high-concentration impurity-doped polycrystalline silicon provided on the semiconductor substrate surrounded by a gate electrode having a polycide structure, the sidewall oxide film, and the LOCOS oxide film. A semiconductor device comprising: a film; and a reverse-conductivity-type high-concentration diffusion layer formed on the surface of the semiconductor substrate in a self-aligned manner with the polycrystalline silicon film.
に高融点金属シリサイド膜を有することを特徴とする請
求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a refractory metal silicide film is provided on at least the surface of the polycrystalline silicon film.
Ｄ構造のＭＯＳトランジスタの製造方法において、 前記半導体基板上にＬＯＣＯＳ酸化膜，ゲート絶縁膜，
ポリサイド構造のゲート電極を形成し、逆導電型低濃度
拡散層を形成し、前記ゲート電極の側面にサイドウォー
ル酸化膜を形成する工程と、 全面に多結晶シリコン膜を堆積し、全面にフォトレジス
ト膜を形成し、エッチバック法により前記ＬＯＣＯＳ酸
化膜と前記サイドウォール酸化膜とにより囲まれた前記
逆導電型低濃度拡散層上にのみ前記多結晶シリコン膜を
残留させる工程と、 高濃度の逆導電型不純物のイオン注入を行ない、熱処理
を行ない、前記ＬＯＣＯＳ酸化膜と前記サイドウォール
酸化膜とにより囲まれた前記半導体基板表面に逆導電型
高濃度拡散層を形成する工程と、 を有することを特徴とする半導体装置の製造方法。3. An LD formed on a semiconductor substrate of one conductivity type
A method for manufacturing a D-structure MOS transistor, comprising: a LOCOS oxide film, a gate insulating film,
Forming a polycide structure gate electrode, forming a reverse conductivity type low concentration diffusion layer, and forming a sidewall oxide film on the side surface of the gate electrode, and depositing a polycrystalline silicon film on the entire surface and photoresist on the entire surface. Forming a film and leaving the polycrystalline silicon film only on the reverse conductivity type low concentration diffusion layer surrounded by the LOCOS oxide film and the sidewall oxide film by an etch back method; Ion-implanting conductivity type impurities, performing heat treatment, and forming a reverse conductivity type high concentration diffusion layer on the surface of the semiconductor substrate surrounded by the LOCOS oxide film and the sidewall oxide film. A method for manufacturing a characteristic semiconductor device.
後、全面に高融点金属膜を堆積し、熱処理によるシリサ
イド化反応を行ない、未反応の前記高融点金属膜を除去
し、前記多結晶シリコンの少なくとも表面を高融点金属
シリサイド膜に変換することを特徴とする請求項３記載
の半導体装置の製造方法。4. A high melting point metal film is deposited on the entire surface after forming the reverse conductivity type high concentration diffusion layer, a silicidation reaction is performed by heat treatment, and the unreacted high melting point metal film is removed. 4. The method of manufacturing a semiconductor device according to claim 3, wherein at least the surface of the crystalline silicon is converted into a refractory metal silicide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17082391A JPH0521458A (en) | 1991-07-11 | 1991-07-11 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17082391A JPH0521458A (en) | 1991-07-11 | 1991-07-11 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0521458A true JPH0521458A (en) | 1993-01-29 |
Family
ID=15911995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17082391A Pending JPH0521458A (en) | 1991-07-11 | 1991-07-11 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0521458A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6747293B2 (en) | 2001-04-09 | 2004-06-08 | Kabushiki Kaisha Toshiba | Light emitting device |
| US7176623B2 (en) | 2001-04-09 | 2007-02-13 | Kabushiki Kaisha Toshiba | Light emitting device |
| US7183718B2 (en) | 2003-01-10 | 2007-02-27 | Sharp Kabushiki Kaisha | Light-emitting device |
| US7939846B2 (en) | 2008-11-17 | 2011-05-10 | Everlight Electronics Co., Ltd. | Circuit board for LED |
| JP4917012B2 (en) * | 2004-02-25 | 2012-04-18 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Method of forming complementary metal oxide semiconductor (CMOS) and CMOS manufactured according to the method |
| US8835931B2 (en) | 2010-04-16 | 2014-09-16 | Osram Opto Semiconductors Gmbh | Optoelectronic component and method for producing an optoelectronic component |
-
1991
- 1991-07-11 JP JP17082391A patent/JPH0521458A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6747293B2 (en) | 2001-04-09 | 2004-06-08 | Kabushiki Kaisha Toshiba | Light emitting device |
| US7176623B2 (en) | 2001-04-09 | 2007-02-13 | Kabushiki Kaisha Toshiba | Light emitting device |
| US7569989B2 (en) | 2001-04-09 | 2009-08-04 | Kabushiki Kaisha Toshiba | Light emitting device |
| US7183718B2 (en) | 2003-01-10 | 2007-02-27 | Sharp Kabushiki Kaisha | Light-emitting device |
| JP4917012B2 (en) * | 2004-02-25 | 2012-04-18 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Method of forming complementary metal oxide semiconductor (CMOS) and CMOS manufactured according to the method |
| US7939846B2 (en) | 2008-11-17 | 2011-05-10 | Everlight Electronics Co., Ltd. | Circuit board for LED |
| US8835931B2 (en) | 2010-04-16 | 2014-09-16 | Osram Opto Semiconductors Gmbh | Optoelectronic component and method for producing an optoelectronic component |
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