JPH05211437A - Logic circuit - Google Patents
Logic circuitInfo
- Publication number
- JPH05211437A JPH05211437A JP4007023A JP702392A JPH05211437A JP H05211437 A JPH05211437 A JP H05211437A JP 4007023 A JP4007023 A JP 4007023A JP 702392 A JP702392 A JP 702392A JP H05211437 A JPH05211437 A JP H05211437A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- transistor
- circuit
- input
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は論理回路に関し、特に、
集積回路としての動作に二値信号とその反転信号とを必
要とする大規模半導体集積回路に適した、基本的論理回
路に関する。FIELD OF THE INVENTION This invention relates to logic circuits, and more particularly to
The present invention relates to a basic logic circuit suitable for a large-scale semiconductor integrated circuit that requires a binary signal and its inverted signal to operate as an integrated circuit.
【０００２】[0002]
【従来の技術】現在実用化されている半導体集積回路の
多くは、例えば、メモリ用集積回路におけるアドレスデ
コーダ回路のデコード信号やマイクロプロセッサ用集積
回路における制御回路のインストラクションデコード信
号あるいはディジタルシグナルプロセッサ用集積回路に
おける乗算器のブース回路出力信号のように、ある二値
信号が必ずその反転信号を伴なって用いられる構成とな
っており、この半導体集積回路を動作させるには、これ
らの信号の論理演算を行なう必要がある。2. Description of the Related Art Most semiconductor integrated circuits currently in practical use are, for example, decode signals of address decoder circuits in memory integrated circuits, instruction decode signals of control circuits in integrated circuits for microprocessors, or integrated signals for digital signal processors. Like a booth circuit output signal of a multiplier in a circuit, a certain binary signal is always used together with its inverted signal. To operate this semiconductor integrated circuit, logical operation of these signals is required. Need to do.
【０００３】従来半導体集積回路に用いられている基本
的論理回路（以後、単に論理回路と記す）の一例の回路
図を図４に示す。この図に示す回路は、排他的論理和
（ＥＸーＯＲ）およびその否定（ＥＸーＮＯＲ）を出力
する。図４を参照すると、この回路は、ＰＭＯＳトラン
ジスタＰ1 とＮＭＯＳトランジスタＮ1 のソース電極同
志およびドレイン電極同志を接続してなるトランスファ
ゲートと、ＰＭＯＳトランジスタＰ2 とＮＭＯＳトラン
ジスタＮ2 とを直列に接続してなるパストランジスタ回
路とを有している。トランスファゲートは、入力側電極
がパストランジスタ回路を構成する２つのＭＯＳトラン
ジスタのゲート電極に接続されており、その接続点に入
力端子１への入力信号Ａが伝達される。また、トランス
ファゲートのＰＭＯＳトランジスタＰ1 のゲート電極と
パストランジスタ回路のＰＭＯＳトランジスタＰ2 の一
方の電極とが接続され、その接続点に入力端子２への入
力信号Ｂが伝達される。トランスファゲートのＮＭＯＳ
トランジスタＮ1 のゲート電極は、パストランジスタ回
路のＮＭＯＳトランジスタＮ2 の一方の電極に接続さ
れ、その接続点に入力端子３に入力される入力信号Ｂの
反転信号が伝達される。トランスファゲートの出力側電
極は、パストランジスタ回路の２つのＭＯＳトランジス
タの直列の続点に接続されており、その接続点への信号
が、インバータ４によって反転，増幅され、出力信号Ｅ
ＸーＮＯＲとして出力端子５から出力される。インバー
タ４の入力端に伝達された信号はまた、２段のインバー
タ６，７によって反転，正転され増幅されて、出力信号
ＥＸーＯＲとして出力端子８から出力される。インバー
タ４，５および６は、信号を反転，正転させて論理の整
合をとるとともに、出力端子５および８に接続される次
段の論理回路（図示せず）を十分高速で動作させるため
のバッファとしても動作するものであって、集積回路と
しての高速動作には欠かせないものである。尚、入力信
号Ａおよび入力信号Ｂは、前述のような、集積回路とし
ての動作にその信号とその信号自身の反転信号とが必要
とされる信号である。FIG. 4 shows a circuit diagram of an example of a basic logic circuit (hereinafter simply referred to as a logic circuit) conventionally used in a semiconductor integrated circuit. The circuit shown in this figure outputs an exclusive OR (EX-OR) and its negation (EX-NOR). Referring to FIG. 4, in this circuit, a transfer gate formed by connecting the source electrode and the drain electrode of the PMOS transistor P 1 and the NMOS transistor N 1 is connected in series with the PMOS transistor P 2 and the NMOS transistor N 2. And a pass transistor circuit formed by. An input side electrode of the transfer gate is connected to the gate electrodes of two MOS transistors forming a pass transistor circuit, and the input signal A to the input terminal 1 is transmitted to the connection point. The gate electrode of the transfer gate PMOS transistor P 1 is connected to one electrode of the PMOS transistor P 2 of the pass transistor circuit, and the input signal B to the input terminal 2 is transmitted to the connection point. Transfer gate NMOS
The gate electrode of the transistor N 1 is connected to one electrode of the NMOS transistor N 2 of the pass transistor circuit, and the inverted signal of the input signal B input to the input terminal 3 is transmitted to the connection point. The output side electrode of the transfer gate is connected to the serial connection point of two MOS transistors of the pass transistor circuit, and the signal to the connection point is inverted and amplified by the inverter 4, and the output signal E
It is output from the output terminal 5 as X-NOR. The signal transmitted to the input terminal of the inverter 4 is also inverted, forwardly rotated and amplified by the two-stage inverters 6 and 7, and output from the output terminal 8 as the output signal EX-OR. The inverters 4, 5 and 6 invert and normalize the signals to match the logic and operate the logic circuit (not shown) at the next stage connected to the output terminals 5 and 8 at a sufficiently high speed. It also operates as a buffer and is essential for high-speed operation as an integrated circuit. It should be noted that the input signal A and the input signal B are signals that require the signal and an inverted signal of the signal itself for the operation as the integrated circuit as described above.
【０００４】この論理回路は、トランスファゲートのそ
れぞれのＭＯＳトランジスタの導通状態が入力信号Ｂま
たはその反転信号によってそれぞれ制御され、パストラ
ンジスタ回路の２つのＭＯＳトランジスタの導通状態が
入力信号Ａにより制御されることによって、入力信号Ａ
と入力信号Ｂとの排他的論理和演算を行なう。いま図４
において、入力信号Ａが“１”で入力信号Ｂが“０”で
あると、トランスファゲートの２つのＭＯＳトランジス
タＰ1 およびＮ1 並びにパストランジスタ回路のＮＭＯ
ＳトランジスタＮ2 がオン状態になり、パストランジス
タ回路のＰＭＯＳトランジスタＰ2 がオフ状態になる。
従って、入力端子１に入力された“１”信号がトランス
ファゲートおよびインバータ６，７を通して出力端子８
に出力される。又、入力端子３に入力された“１”信号
が、ＮＭＯＳトランジスタＮ2 を通して出力端子８に出
力される。入力信号Ａが“１”で入力信号Ｂが“１”の
場合には、出力端子８に“０”信号が出力され出力端子
５に“１”信号が出力される。入力信号Ａが“１”で入
力信号Ｂが“０”の場合には、出力端子８に“１”信号
が出力され出力端子５に“０”信号が出力される。入力
信号Ａが“０”で入力信号Ｂが“０”の場合には、出力
端子８に“０”信号が出力され出力端子５に“１”信号
が出力される。In this logic circuit, the conduction state of each MOS transistor of the transfer gate is controlled by the input signal B or its inverted signal, and the conduction state of the two MOS transistors of the pass transistor circuit is controlled by the input signal A. The input signal A
And an input signal B are subjected to an exclusive OR operation. Now Figure 4
, The input signal A is "1" and the input signal B is "0", the two MOS transistors P 1 and N 1 of the transfer gate and the NMO of the pass transistor circuit.
The S transistor N 2 is turned on, and the PMOS transistor P 2 of the pass transistor circuit is turned off.
Therefore, the "1" signal input to the input terminal 1 passes through the transfer gate and the inverters 6 and 7 and is output to the output terminal 8
Is output to. Further, the “1” signal input to the input terminal 3 is output to the output terminal 8 through the NMOS transistor N 2 . When the input signal A is “1” and the input signal B is “1”, the “0” signal is output to the output terminal 8 and the “1” signal is output to the output terminal 5. When the input signal A is “1” and the input signal B is “0”, the “1” signal is output to the output terminal 8 and the “0” signal is output to the output terminal 5. When the input signal A is “0” and the input signal B is “0”, the “0” signal is output to the output terminal 8 and the “1” signal is output to the output terminal 5.
【０００５】ここで、信号伝達のスピードを決るクリテ
ィカルパスについて考察すると、各入力端子からＭＯＳ
トランジスタを通り、インバータ６および７を経て、Ｅ
ＸーＯＲ出力端子８に至るパスである。Now, considering a critical path that determines the speed of signal transmission, the MOS is connected from each input terminal.
After passing through the transistor, through inverters 6 and 7, E
This is the path to the X-OR output terminal 8.
【０００６】[0006]
【発明が解決しようとする課題】上述した従来の論理回
路は、論理信号とその反転信号とを一つの回路で得てし
かも次段の論理回路を十分高速で動作させるためのバッ
ファを必要とする。このため、入力端子から出力端子ま
でのクリティカルパスのゲート段数が多くなり、これを
構成するトランジスタ数も多くなるので、これを用いた
集積回路では、動作の高速化、低消費電力化が難しい。The above-mentioned conventional logic circuit requires a buffer for obtaining the logic signal and its inverted signal in one circuit and for operating the logic circuit in the next stage at a sufficiently high speed. .. For this reason, the number of gate stages of the critical path from the input terminal to the output terminal increases, and the number of transistors forming the gate path also increases. Therefore, it is difficult for an integrated circuit using the same to achieve high-speed operation and low power consumption.
【０００７】本発明は上記の点に鑑みてなされたもので
あって、回路構成が簡単で、しかも論理出力までのゲー
ト段数が少なく負荷駆動能力の大きい駆動回路を利用し
やすい、超高速大規模集積回路に適した論理回路を提供
することにある。The present invention has been made in view of the above points, and has an extremely high speed and large scale in which the circuit configuration is simple and the number of gate stages up to the logic output is small and the load driving capability is large. It is to provide a logic circuit suitable for an integrated circuit.
【０００８】[0008]
【課題を解決するための手段】本発明の論理回路は、一
対の信号入力端子間に二つのトランジスタが直列に接続
されてなるパストランジスタ回路を二組設け、一方のパ
ストランジスタ回路を構成するトランジスタと、他方の
パストランジスタ回路を構成するトランジスタとを一つ
ずつ組合せて二組のトランジスタ対となし、一方のパス
トランジスタ回路の信号入力端子と、これに対応する他
方のパストランジスタ回路の信号入力端子のそれぞれ
に、互いに反転関係にある信号をそれぞれ入力し、上記
の二組のトランジスタ対のそれぞれの導通状態を、互い
に反転関係にある信号でそれぞれ制御することを特徴と
している。According to another aspect of the present invention, there is provided a logic circuit, wherein two sets of pass transistor circuits each having two transistors connected in series are provided between a pair of signal input terminals. And one of the transistors forming the other pass transistor circuit are combined one by one to form two pairs of transistors, and the signal input terminal of one pass transistor circuit and the corresponding signal input terminal of the other pass transistor circuit To each of which the signals having the inversion relationship with each other are input, and the conduction state of each of the two transistor pairs is controlled with the signals having the inversion relationship to each other.
【０００９】[0009]
【作用】本発明では、一対の信号入力端子間に互いに直
列に接続した２つのＭＯＳトランジスタからなるパスト
ランジスタ回路に、入力信号Ａとその反転信号からなる
信号組を入力し、２つのＭＯＳトランジスタの導通状態
を他の信号組（入力信号Ｂおよびその反転信号の組）で
制御して、入力信号Ａと入力信号Ｂの排他的論理和を得
る。同様にして、もう一つのパストランジスタ回路を用
い、この回路のトランジスタを上記と同じ入力信号Ｂお
よびその反転信号で制御して、否排他的論理和を同時に
得る。すなわち、従来の論理回路では用いられていなか
った、入力信号Ａの反転信号を用いることにより、論理
回路の構成を単純化すると共に、立ち上り，立ち下りの
よく揃った論理信号とその否定論理信号とを同時に得
る。According to the present invention, a pair of signal transistors consisting of two MOS transistors connected in series between a pair of signal input terminals are input with a signal set consisting of the input signal A and its inversion signal to input the signal set of the two MOS transistors. The conduction state is controlled by another signal set (the set of the input signal B and its inverted signal) to obtain the exclusive OR of the input signal A and the input signal B. Similarly, another pass-transistor circuit is used, and the transistors of this circuit are controlled by the same input signal B and its inverted signal as described above to simultaneously obtain a non-exclusive OR. That is, by using the inverted signal of the input signal A, which is not used in the conventional logic circuit, the logic circuit configuration is simplified, and the rise and fall well-aligned logic signals and their negative logic signals are used. Get at the same time.
【００１０】又、上記のパストランジスタ回路の両端に
入力する信号を、入力信号Ａと入力信号Ｂの信号組また
は入力信号Ａの反転信号と入力信号Ｂの反転信号の信号
組とすることにより、論理積回路または論理和回路とし
て動作させることができる。Further, the signals input to both ends of the pass transistor circuit are set as a signal set of the input signal A and the input signal B or a signal set of the inverted signal of the input signal A and the inverted signal of the input signal B. It can be operated as an AND circuit or an OR circuit.
【００１１】本発明の論理回路は、論理信号とその否定
論理信号とを同時に出力するので、２つのＢｉＣＭＯＳ
増幅器をフリップフロップ接続した型の、高速で高負荷
駆動能力を有する駆動回路を利用するのに適している。
従って、このような駆動回路と組み合せることによっ
て、通過ゲート段数を増加させることなしに次段の論理
回路を高速で駆動することができ、集積回路の高速動作
が可能になる。Since the logic circuit of the present invention outputs a logic signal and its negation logic signal at the same time, two BiCMOS circuits are provided.
It is suitable for using a driving circuit of flip-flop type in which an amplifier is connected and which has a high speed and a high load driving capability.
Therefore, by combining with such a drive circuit, the logic circuit of the next stage can be driven at high speed without increasing the number of pass gate stages, and the integrated circuit can operate at high speed.
【００１２】本発明の論理回路を集積回路に用いる場合
には、パストランジスタ回路で生成され上記の駆動回路
部で増幅された論理信号を、低電圧振幅のまま次段の論
理回路に伝える。次段の論理回路では、パストランジス
タ回路を構成するＮＭＯＳトランジスタのゲートへの入
力信号（入力信号Ｂおよびその反転信号）の入力端子に
プルアップ用のＰＭＯＳトランジスタを設け、ゲート入
力信号の高レベルを高位電源電圧まで引き上げることに
よりＮＭＯＳトランジスタのチャンネル抵抗を下げて、
動作の高速化を画る。パストランジスタ回路は本質的に
高速であり、更に出力信号の電圧振幅が小さいので、集
積回路の高速化および低消費電力化を達成できる。When the logic circuit of the present invention is used in an integrated circuit, the logic signal generated by the pass transistor circuit and amplified by the drive circuit section is transmitted to the logic circuit of the next stage while keeping the low voltage amplitude. In the logic circuit of the next stage, a pull-up PMOS transistor is provided at the input terminal of the input signal (input signal B and its inverted signal) to the gate of the NMOS transistor that constitutes the pass transistor circuit, and the high level of the gate input signal is set. The channel resistance of the NMOS transistor is lowered by raising it to a higher power supply voltage,
Draw high-speed operation. Since the pass transistor circuit is essentially high speed and the voltage amplitude of the output signal is small, it is possible to achieve high speed and low power consumption of the integrated circuit.
【００１３】[0013]
【実施例】次に、本発明の最適な実施例について説明す
る。図１（ａ）は、本発明の第１の実施例の回路図であ
る。図に示した回路は、出力端子５に入力信号Ａと入力
信号Ｂとの否排他的論理和信号を出力し、出力端子８に
排他的論理和信号を出力する。図１（ａ）を参照する
と、本実施例は、４つのＮＭＯＳトランジスタＮ3 〜Ｎ
5 を含む論理回路部と、ＮＰＮバイポーラトランジスタ
とＮＭＯＳトランジスタとからなる２組のＢｉＣＭＯＳ
増幅回路を組み合せた駆動回路部と、２つのＰＭＯＳト
ランジスタＰ5 ，Ｐ6 からなるプルアップ回路部とから
なっている。Next, an optimum embodiment of the present invention will be described. FIG. 1A is a circuit diagram of the first embodiment of the present invention. The circuit shown in the figure outputs an exclusive OR signal of the input signal A and the input signal B to the output terminal 5, and outputs an exclusive OR signal to the output terminal 8. Referring to FIG. 1A, this embodiment includes four NMOS transistors N 3 to N 3.
Two sets of BiCMOS consisting of a logic circuit section including 5 and an NPN bipolar transistor and an NMOS transistor
It is composed of a drive circuit section in which an amplifier circuit is combined and a pull-up circuit section composed of two PMOS transistors P 5 and P 6 .
【００１４】論理回路部は、２つのＮＭＯＳトランジス
タＮ3 とＮ4 とが入力端子９と入力端子１との間に直列
に接続されており、接続点が出力端子８に接続されてい
る。又、２つのＮＭＯＳトランジスタＮ5 およびＮ
6 が、入力端子１と入力端子９との間に直列に接続され
ており、接続点が出力端子５に接続されている。入力端
子１には入力信号Ａが入力され、入力端子９には入力信
号Ａの反転信号が入力されている。ＮＭＯＳトランジス
タＮ3 およびＮ5 のゲートには入力信号Ｂが入力され、
ＮＭＯＳトランジスタＮ4 およびＮ6 のゲートには入力
信号Ｂの反転信号が入力されている。In the logic circuit section, two NMOS transistors N 3 and N 4 are connected in series between the input terminal 9 and the input terminal 1, and the connection point is connected to the output terminal 8. Also, two NMOS transistors N 5 and N
6 is connected in series between the input terminal 1 and the input terminal 9, and the connection point is connected to the output terminal 5. The input signal A is input to the input terminal 1, and the inverted signal of the input signal A is input to the input terminal 9. The input signal B is input to the gates of the NMOS transistors N 3 and N 5 ,
The inverted signal of the input signal B is input to the gates of the NMOS transistors N 4 and N 6 .
【００１５】いま図１（ａ）において、入力信号Ｂが
“０”であると、ＮＭＯＳトランジスタＮ3 ，Ｎ5 がオ
フ状態で、ＮＭＯＳトランジスタＮ4 ，Ｎ6 がオン状態
であるので、出力端子５に入力信号Ａの反転信号が出力
され出力端子８に入力信号Ａが出力される。一方、入力
信号Ｂが“１”の場合は、ＮＭＯＳトランジスタＮ3 ，
Ｎ5 がオン状態でＮＭＯＳトランジスタＮ4 ，Ｎ6 がオ
フ状態であるので、出力端子５に入力信号Ａが出力され
出力端子８には入力信号Ａの反転信号が出力される。以
上の論理状態は、図１（ｂ）に示す真理値表で表され、
本実施例では、簡単な回路構成で排他的論理和と否排他
的論理和とが同時に得られることが分る。しかも、出力
信号ＥＸーＯＲおよびＥＸーＮＯＲは、高レベルがＮＭ
ＯＳトランジスタのしきい値電圧分だけ低くく、論理振
幅が小さく抑えられているので、高速化、低消費電力化
に有利である。更に、本実施例の論理回路部では、入力
信号ＡはＮＭＯＳトランジスタＮ4 ，Ｎ5 のソース電極
容量に接続されているだけであり、従来の論理回路とは
異なって、他のＭＯＳトランジスタ（図４中のＰＭＯＳ
トランジスタＰ2 およびＮＭＯＳトランジスタＮ2 ）の
ゲート電極には接続されていない。従って、本実施例に
おける論理回路部は、入力信号Ａに対する負荷容量が軽
減されており、その分高速化に有利である。[0015] In now to Figure 1 (a), when there the input signal B is "0", the NMOS transistors N 3, N 5 is turned off, the NMOS transistor N 4, N 6 is in the ON state, the output terminal An inverted signal of the input signal A is output to 5 and the input signal A is output to the output terminal 8. On the other hand, when the input signal B is “1”, the NMOS transistor N 3 ,
Since N 5 is on and the NMOS transistors N 4 and N 6 are off, the input signal A is output to the output terminal 5 and the inverted signal of the input signal A is output to the output terminal 8. The above logic states are represented by the truth table shown in FIG.
In this embodiment, it can be seen that the exclusive OR and the non-exclusive OR can be obtained at the same time with a simple circuit configuration. Moreover, the high level of the output signals EX-OR and EX-NOR is NM.
Since it is as low as the threshold voltage of the OS transistor and the logic amplitude is suppressed to be small, it is advantageous for speeding up and low power consumption. Further, in the logic circuit portion of this embodiment, the input signal A is only connected to the source electrode capacitances of the NMOS transistors N 4 and N 5 , and unlike the conventional logic circuit, other MOS transistors (see FIG. PMOS in 4
It is not connected to the gate electrodes of the transistor P 2 and the NMOS transistor N 2 ). Therefore, in the logic circuit section of the present embodiment, the load capacity for the input signal A is reduced, which is advantageous for speeding up.
【００１６】次に、駆動回路部では、２つのＢｉＣＭＯ
Ｓ増幅回路が互いに自己の出力を相手の入力組の一つと
して入力するように接続されており、一方の増幅回路の
入力端に前述の論理回路部からの排他的論理和信号が入
力され、他方の増幅回路の入力端に否排他的論理和信号
が入力されている。この駆動回路部を構成するＢｉＣＭ
ＯＳ増幅回路では、高位電源ライン１０とグランドライ
ン１１との間に直列に接続されたＮＰＮバイポーラトラ
ンジスタＱ1 とＮＭＯＳトランジスタＮ7 との接続点を
出力端とし、ＮＰＮバイポーラトランジスタＱ1 のベー
ス電極は、高位電源ライン１１とグランドライン１２と
の間に直列に接続されたＰＭＯＳトランジスタＰ3 とＮ
ＭＯＳトランジスタＮ8 の直列回路の接続点に接続され
ている。そして、ＰＭＯＳトランジスタＰ3 ，ＮＭＯＳ
トランジスタＮ8 およびＮＭＯＳトランジスタＮ7 のゲ
ート電極がこの増幅回路の入力端に接続されている。も
う一方のＢｉＣＭＯＳ増幅回路も同じ構成である。Next, in the drive circuit section, two BiCMOs are used.
The S amplifier circuits are connected to each other so that their outputs are input as one of the other input sets, and the exclusive OR signal from the logic circuit section is input to the input terminal of one of the amplifier circuits. The exclusive-OR signal is input to the input terminal of the other amplifier circuit. BiCM configuring this drive circuit unit
In the OS amplifier circuit, the connection point between the NPN bipolar transistor Q 1 and the NMOS transistor N 7 connected in series between the high-potential power line 10 and the ground line 11 is used as an output terminal, and the base electrode of the NPN bipolar transistor Q 1 is , PMOS transistors P 3 and N connected in series between the high level power line 11 and the ground line 12.
It is connected to the connection point of the series circuit of the MOS transistor N 8 . Then, the PMOS transistor P 3 and the NMOS
The gate electrodes of the transistor N 8 and the NMOS transistor N 7 are connected to the input terminal of this amplifier circuit. The other BiCMOS amplifier circuit has the same configuration.
【００１７】この駆動回路部では、出力段にＮＰＮバイ
ポーラトランジスタを使用して駆動能力を増強してい
る。更に、一方のＢｉＣＭＯＳ増幅回路の出力信号を他
方の増幅回路の入力端にフィードバックし、他方の出力
信号も同様に一方の増幅回路の入力端に入力して、２つ
の入力信号を相補的に増幅している。バイポーラトラン
ジスタの駆動には、ゲート長が短かく入力容量の小さい
ＭＯＳトランジスタを使用することによって、前段の回
路（本実施例では前述の論理回路部）が駆動すべき負荷
容量を軽減している。又、出力信号の高レベルは電源電
圧よりＮＰＮバイポーラトランジスタのビルトイン電圧
分だけ低くなり、例えば、高位電源電圧が３．３Ｖの時
は、出力信号の高レベルが２．７Ｖ程度になって信号振
幅が抑えられるので、高速化、低消費電力化に効果があ
る。以上の工夫により入力信号が高速に増幅される。こ
の駆動回路部は、入力信号として立ち上り，立ち下りの
よく揃った、互いに反転関係にある一対の信号を入力す
ると、安定に動作して上記の特徴を発揮するので、本実
施例の論理回路部と組み合せて使用するのに適した駆動
回路である。In this drive circuit section, an NPN bipolar transistor is used in the output stage to enhance the drive capability. Further, the output signal of one BiCMOS amplifier circuit is fed back to the input terminal of the other amplifier circuit, and the other output signal is similarly input to the input terminal of the one amplifier circuit to complementarily amplify the two input signals. is doing. A MOS transistor having a short gate length and a small input capacitance is used for driving the bipolar transistor, so that the load capacitance to be driven by the circuit at the preceding stage (in the present embodiment, the logic circuit section) is reduced. Further, the high level of the output signal becomes lower than the power supply voltage by the built-in voltage of the NPN bipolar transistor. For example, when the high power supply voltage is 3.3V, the high level of the output signal becomes about 2.7V and the signal amplitude becomes high. This is effective in speeding up and reducing power consumption. The input signal is amplified at high speed by the above device. This drive circuit section operates stably and exhibits the above characteristics when a pair of signals having a good rise and a fall, which are well aligned with each other and having an inversion relationship, are input as input signals. This drive circuit is suitable for use in combination with.
【００１８】次に、本実施例の論理回路部の入力端子２
および３には、プルアップ用のＰＭＯＳトランジスタＰ
5 およびＰ6 が設けられており、入力信号Ｂおよびその
反転信号のレベルを高めている。ＰＭＯＳトランジスタ
Ｐ5 は、ソース電極が高位電源端子１０に接続されドレ
イン電極が入力端子３に接続され、ゲートには入力信号
Ｂが入力されている。ＰＭＯＳトランジスタＰ6 も同様
に、ソース電極が高位電源端子１０に接続されドレイン
電極が入力端子２に接続され、ゲートには入力信号Ｂの
反転信号が入力されている。入力信号Ｂおよびその反転
信号の高レベルが低いと、この信号に制御されるＮＭＯ
ＳトランジスタＮ3 〜Ｎ6 のチャンネル抵抗が高くなる
ので、信号の伝播速度が遅くなる。そこで、上記のプル
アップ用ＰＭＯＳトランジスタＰ5 ，Ｐ6 で入力信号Ｂ
およびその反転信号の高レベルを高位電源電圧レベルま
で引き上げて高速性を保つ。Next, the input terminal 2 of the logic circuit section of this embodiment
And 3 are pull-up PMOS transistors P
5 and P 6 are provided to raise the level of the input signal B and its inverted signal. In the PMOS transistor P 5 , the source electrode is connected to the high potential power supply terminal 10, the drain electrode is connected to the input terminal 3, and the input signal B is input to the gate. Similarly, in the PMOS transistor P 6 , the source electrode is connected to the high potential power supply terminal 10, the drain electrode is connected to the input terminal 2, and the inverted signal of the input signal B is input to the gate. When the high level of the input signal B and its inverted signal is low, the NMO controlled by this signal is low.
Since the channel resistance of the S transistor N 3 to N 6 becomes high, the propagation speed of the signal is delayed. Therefore, the input signal B is applied to the pull-up PMOS transistors P 5 and P 6 described above.
And the high level of the inverted signal thereof is raised to the high power supply voltage level to maintain high speed.
【００１９】一般に、ＭＯＳトランジスタを高速で駆動
するには、ゲート入力信号は、高位電源電位とグランド
電位との間をフルスイングする全振幅信号であることが
望ましいが、本実施例の論理回路部および駆動回路部か
らの出力信号は振幅が小さく抑えられている。これに対
して、上記のように、論理回路部のＮＭＯＳトランジス
タのゲート入力信号レベルをプルアップすれば、集積回
路内で本発明の論理回路を縦続に接続してその高速性，
低消費電力性の特徴を十分に発揮することができる。こ
の場合、図４に示す従来の論理回路では、入力信号Ａが
ＰＭＯＳトランジスタＰ2 およびＮＭＯＳトランジスタ
Ｎ2 のゲート電極にも入力されているので、入力信号Ｂ
およびその反転信号の入力端子２，３のみならず、入力
信号Ａの入力端子１にもプルアップトランジスタを設け
入力信号Ａのレベルを高めなくてはならず、トランジス
タ数が増えてしまう。これに対して本実施例では、入力
信号Ａおよびその反転信号は論理回路部のＮＭＯＳトラ
ンジスタＮ3 〜Ｎ6 のいずれのゲート電極にも接続され
ていないので、これらの入力信号ラインにはプルアップ
用のＰＭＯＳトランジスタを設ける必要がない。Generally, in order to drive the MOS transistor at high speed, it is desirable that the gate input signal is a full amplitude signal that fully swings between the high potential power supply potential and the ground potential. However, the logic circuit section of the present embodiment. Also, the amplitude of the output signal from the drive circuit unit is suppressed to be small. On the other hand, as described above, if the gate input signal level of the NMOS transistor of the logic circuit section is pulled up, the logic circuits of the present invention are connected in series in the integrated circuit to achieve high speed,
The characteristics of low power consumption can be sufficiently exhibited. In this case, in the conventional logic circuit shown in FIG. 4, since the input signal A is also input to the gate electrodes of the PMOS transistor P 2 and the NMOS transistor N 2 , the input signal B is input.
A pull-up transistor must be provided not only on the input terminals 2 and 3 for the inverted signal and the input terminal 1 for the input signal A to increase the level of the input signal A, but the number of transistors increases. In this embodiment the contrary, the input signal A and the inverted signal is not connected to any of the gate electrode of the NMOS transistor N 3 to N 6 of the logic circuit portion, the pull-up on these input signal lines It is not necessary to provide a PMOS transistor for.
【００２０】上記の第１の実施例においては、入力端子
１０，９に入力する信号の組み合せを入力信号Ａおよび
その反転信号の組として、排他的論理和演算および否排
他的論理和演算を行なう回路について説明したが、図２
（ａ）に示す第２の実施例のように、入力信号Ａと入力
信号Ｂとからなる信号組および、入力信号Ａの反転信号
と入力信号Ｂの反転信号とからなる信号組を入力して、
論理積演算および否論理積演算を行わせることもでき
る。In the first embodiment, the exclusive OR operation and the non-exclusive OR operation are performed by using the combination of the signals input to the input terminals 10 and 9 as the combination of the input signal A and its inverted signal. I explained the circuit,
As in the second embodiment shown in (a), a signal set consisting of the input signal A and the input signal B and a signal set consisting of the inverted signal of the input signal A and the inverted signal of the input signal B are input. ,
It is also possible to perform a logical product operation and a non-logical product operation.
【００２１】図２（ａ）は、本発明の第２の実施例の回
路図である。この図に示す論理回路部は、出力端子５に
入力信号Ａと入力信号Ｂとの論理積を出力し、出力端子
８に否論理積を出力する。図２（ａ）を参照すると、本
実施例の論理回路部は、２つのＮＭＯＳトランジスタＮ
3 とＮ4 とが入力端子９と入力端子３との間に直列に接
続されており、接続点が出力端子８に接続されている。
又、２つのＮＭＯＳトランジスタＮ5 およびＮ6 が、入
力端子１と入力端子２との間に直列に接続されており、
接続点が出力端子５に接続されている。入力端子１には
入力信号Ａが入力され、入力端子９に入力信号Ａの反転
信号が入力されている。ＮＭＯＳトランジスタＮ3 およ
びＮ5 のゲートには、入力信号Ｂが入力され、ＮＭＯＳ
トランジスタＮ4 およびＮ6 のゲートには、入力信号Ｂ
の反転信号が入力されている。ここで図２（ａ）におい
て、入力信号Ｂが“０”であれば、ＮＭＯＳトランジス
タＮ3 ，Ｎ5 がオフ状態でありＮＭＯＳトランジスタＮ
4 ，Ｎ6 がオン状態にあるので、出力端子５に入力信号
Ｂが出力され出力端子８に入力信号Ｂの反転信号が出力
される。一方、入力信号Ｂが“１”の場合は、ＮＭＯＳ
トランジスタＮ3 ，Ｎ5 がオン状態でありＮＭＯＳトラ
ンジスタＮ4 ，Ｎ6 がオフ状態であるので、出力端子５
に入力信号Ａが出力され出力端子８に入力信号Ａの反転
信号が出力される。以上の論理状態は図２（ｂ）に示す
真理値表で表され、この論理回路部で論理積演算と否論
理積演算とが同時に行われることが分る。FIG. 2A is a circuit diagram of the second embodiment of the present invention. The logic circuit section shown in this figure outputs the logical product of the input signal A and the input signal B to the output terminal 5, and outputs the negative logical product to the output terminal 8. Referring to FIG. 2A, the logic circuit unit of this embodiment has two NMOS transistors N
3 and N 4 are connected in series between the input terminal 9 and the input terminal 3, and the connection point is connected to the output terminal 8.
Also, two NMOS transistors N 5 and N 6 are connected in series between the input terminal 1 and the input terminal 2,
The connection point is connected to the output terminal 5. The input signal A is input to the input terminal 1, and the inverted signal of the input signal A is input to the input terminal 9. The input signal B is input to the gates of the NMOS transistors N 3 and N 5 ,
The input signal B is applied to the gates of the transistors N 4 and N 6.
The inverted signal of is input. Here in FIG. 2 (a), if the input signal B "0", the NMOS transistor N 3, N 5 is off NMOS transistors N
Since 4 and N 6 are in the ON state, the input signal B is output to the output terminal 5 and the inverted signal of the input signal B is output to the output terminal 8. On the other hand, when the input signal B is "1", the NMOS
Since the transistors N 3 and N 5 are on and the NMOS transistors N 4 and N 6 are off, the output terminal 5
The input signal A is output to and the inverted signal of the input signal A is output to the output terminal 8. The above logical state is represented by the truth table shown in FIG. 2B, and it can be seen that the logical product operation and the logical AND operation are simultaneously performed in this logic circuit unit.
【００２２】次に、本実施例では、入力信号Ｂおよびそ
の反転信号が入力される入力端子２および３に、プルア
ップ用ＰＭＯＳトランジスタトランジスタに加えて、プ
ルダウン用のＮＭＯＳトランジスタを設けてプルダウン
の高速化を画っている。プルダウン用ＮＭＯＳトランジ
スタＮ11は、ソース電極がグランドライン１１に接続さ
れドレイン電極が入力端子３に接続され、ゲートには入
力信号Ｂが入力されている。ＮＭＯＳトランジスタＮ12
も同様に、ソース電極がグランドライン１１に接続され
ドレイン電極が入力端子２に接続され、ゲートには入力
信号Ｂの反転信号が入力されている。本実施例でも、従
来の論理回路と異なって、入力信号Ａおよびその反転信
号の入力端にはプルアップ，プルダウン用のＭＯＳトラ
ンジスタを設ける必要がないので、従来の論理回路に比
べてトランジスタが少なくて動作の高速化を計ることが
できる。又、論理回路部に、図１（ｂ）に示す駆動回路
部を接続することによって、第１の実施例と同様に、こ
の駆動回路部の高速駆動性を十分に利用することができ
る。Next, in this embodiment, a pull-down NMOS transistor is provided at the input terminals 2 and 3 to which the input signal B and its inverted signal are inputted, in addition to the pull-up PMOS transistor transistor, a high pull-down speed is provided. It is drawing. In the pull-down NMOS transistor N 11 , the source electrode is connected to the ground line 11, the drain electrode is connected to the input terminal 3, and the input signal B is input to the gate. NMOS transistor N 12
Similarly, the source electrode is connected to the ground line 11, the drain electrode is connected to the input terminal 2, and the inverted signal of the input signal B is input to the gate. Also in this embodiment, unlike the conventional logic circuit, it is not necessary to provide MOS transistors for pulling up and pulling down at the input terminal of the input signal A and its inverted signal, and therefore the number of transistors is smaller than that of the conventional logic circuit. Therefore, the operation speed can be increased. Further, by connecting the drive circuit section shown in FIG. 1B to the logic circuit section, the high-speed drivability of this drive circuit section can be fully utilized as in the first embodiment.
【００２３】更に、図２（ａ）に示す回路において、論
理回路部の４つのＮＭＯＳトランジスタのゲートに入力
される入力信号Ｂおよびその反転信号の極性を、図３
（ａ）に示す第３の実施例のように、第２の実施例とは
反対にすることによって、この論理回路部を論理和回路
および否論理和回路として動作させることができる。Further, in the circuit shown in FIG. 2A, the polarities of the input signal B and its inverted signal input to the gates of the four NMOS transistors of the logic circuit section are shown in FIG.
As in the third embodiment shown in (a), by reversing the second embodiment, this logic circuit section can be operated as a logical sum circuit and a negative logical sum circuit.
【００２４】図３（ａ）は、本発明の第３の実施例の回
路図である。この図に示す論理回路部は、出力端子５に
入力信号Ａと入力信号Ｂとの論理和を出力し、出力端子
８に否論理和を出力する。図３（ａ）を参照すると、本
実施例における論理回路部と図２（ａ）に示す第２の実
施例における論理回路部とが異なるのは、４つのＮＭＯ
ＳトランジスタＮ3 〜Ｎ6 のゲート入力である。本実施
例では、ＮＭＯＳトランジスタＮ3 およびＮ5 のゲート
に入力信号Ｂの反転信号が入力され、ＮＭＯＳトランジ
スタＮ4 およびＮ6 のゲートに、入力信号Ｂが入力され
ている。いま図３（ａ）において、入力信号Ｂが“０”
であれば、ＮＭＯＳトランジスタＮ4 ，Ｎ6 がオフ状態
でありＮＭＯＳトランジスタＮ3 ，Ｎ5 がオン状態にあ
るので、出力端子５に入力信号Ａが出力され出力端子８
に入力信号Ａの反転信号が出力される。一方、入力信号
Ｂが“１”の場合は、ＮＭＯＳトランジスタＮ4 ，Ｎ6
がオン状態でありＮＭＯＳトランジスタＮ3 ，Ｎ5 がオ
フ状態であるので、出力端子５に入力信号Ｂが出力され
出力端子８に入力信号Ｂの反転信号が出力される。以上
の論理状態は図３（ｂ）に示す真理値表で表され、この
論理回路部で論理和演算と否論理和演算とが同時に行わ
れることが分る。FIG. 3A is a circuit diagram of the third embodiment of the present invention. The logic circuit section shown in this figure outputs the logical sum of the input signal A and the input signal B to the output terminal 5, and outputs the negative logical sum to the output terminal 8. With reference to FIG. 3A, the difference between the logic circuit unit according to the present embodiment and the logic circuit unit according to the second embodiment illustrated in FIG.
It is a gate input of the S transistors N 3 to N 6 . In this embodiment, the inverted signal of the input signal B is input to the gates of the NMOS transistors N 3 and N 5 , and the input signal B is input to the gates of the NMOS transistors N 4 and N 6 . Now, in FIG. 3A, the input signal B is "0".
Then, since the NMOS transistors N 4 and N 6 are in the off state and the NMOS transistors N 3 and N 5 are in the on state, the input signal A is output to the output terminal 5 and the output terminal 8
An inverted signal of the input signal A is output to. On the other hand, when the input signal B "1" is, NMOS transistors N 4, N 6
Is on and the NMOS transistors N 3 and N 5 are off, the input signal B is output to the output terminal 5 and the inverted signal of the input signal B is output to the output terminal 8. The above logic state is represented by the truth table shown in FIG. 3B, and it can be seen that the logical sum operation and the disjunction operation are simultaneously performed in this logic circuit section.
【００２５】本実施例においても、図１（ａ）に示す駆
動回路部と組み合せてその高速負荷駆動性を利用するこ
とができる。又、論理回路部の入力端子２，３にだけ、
プルアップ用ＰＭＯＳトランジスタおよびプルダウン用
ＮＭＯＳトランジスタを設ければ、従来の論理回路にお
けるよりも少ないトランジスタでより高速に動作させる
ことができる。Also in this embodiment, the high speed load drivability can be utilized in combination with the drive circuit section shown in FIG. Also, only at the input terminals 2 and 3 of the logic circuit section,
By providing the pull-up PMOS transistor and the pull-down NMOS transistor, it is possible to operate at a higher speed with a smaller number of transistors than in the conventional logic circuit.
【００２６】[0026]
【発明の効果】以上説明してきたとおり、本発明の論理
回路においては、２組のパストランジスタ回路を設け、
一方のパストランジスタ回路への入力信号の極性とこれ
に対応する他方のパストランジスタ回路への入力信号の
極性とを互いに反転の関係にすることにより、立ち上
り，立ち下りのよく揃った論理出力と否論理出力が同時
に得られる。これにより、本発明によれば、ＢｉＣＭＯ
Ｓ増幅回路をフリップフロップ接続して互いに極性が逆
の２入力信号を相補的に増幅する型の、高速性，高負荷
駆動能力に優れた駆動回路を利用することができる。し
かも本発明の論理回路は、入力信号の負担が軽減されて
いるので、入力信号のプルアップ，プルダウン回路の構
成がその分簡単になる。本発明の論理回路は、大規模集
積回路上で縦続接続して用いれば、集積回路としての動
作速度の高速化、低消費電力化および高密度化に大きな
効果を示す。As described above, in the logic circuit of the present invention, two sets of pass transistor circuits are provided,
By setting the polarities of the input signals to one pass transistor circuit and the polarities of the corresponding input signals to the other pass transistor circuit to be inverse to each other, it is possible to determine whether the logical output has a good rise and fall. Logic outputs are obtained at the same time. Thereby, according to the present invention, the BiCMO
It is possible to use a drive circuit of a type that complementarily amplifies two input signals whose polarities are opposite to each other by connecting the S amplifier circuits in a flip-flop manner and which is excellent in high speed and high load drive capability. Moreover, since the load of the input signal is reduced in the logic circuit of the present invention, the configuration of the pull-up / pull-down circuit for the input signal is simplified accordingly. The logic circuit of the present invention, when used in cascade connection on a large-scale integrated circuit, shows great effects in increasing the operating speed of the integrated circuit, reducing the power consumption, and increasing the density.
【図１】分図（ａ）は、本発明の第１の実施例の回路図
である。分図（ｂ）は、分図（ａ）に示す回路の真理値
表を表す図である。FIG. 1A is a circuit diagram of a first embodiment of the present invention. Diagram (b) is a diagram showing a truth table of the circuit shown in diagram (a).
【図２】分図（ａ）は、本発明の第２の実施例の回路図
である。分図（ｂ）は、分図（ａ）に示す回路の真理値
表を表す図である。FIG. 2A is a circuit diagram of a second embodiment of the present invention. Diagram (b) is a diagram showing a truth table of the circuit shown in diagram (a).
【図３】分図（ａ）は、本発明の第３の実施例の回路図
である。分図（ｂ）は、分図（ａ）に示す回路の真理値
表を表す図である。FIG. 3A is a circuit diagram of a third embodiment of the present invention. Diagram (b) is a diagram showing a truth table of the circuit shown in diagram (a).
【図４】従来の論理回路の一例の実施例の回路図であ
る。FIG. 4 is a circuit diagram of an example of an example of a conventional logic circuit.
１，２，３，９ 入力端子 ４，６，７ インバータ ５，８ 出力端子 １０ 高位電源ライン １１ グランドライン 1,2,3,9 Input terminal 4,6,7 Inverter 5,8 Output terminal 10 High power line 11 Ground line
Claims (10)
スタが直列に接続されてなるパストランジスタ回路を二
組設け、 一方のパストランジスタ回路を構成するトランジスタ
と、他方のパストランジスタ回路を構成するトランジス
タとを一つずつ組合せて二組のトランジスタ対となし、 一方のパストランジスタ回路の信号入力端子と、これに
対応する他方のパストランジスタ回路の信号入力端子の
それぞれに、互いに反転関係にある信号をそれぞれ入力
し、 前記二組のトランジスタ対のそれぞれの導通状態を、互
いに反転関係にある信号でそれぞれ制御することを特徴
とする論理回路。1. A pair of pass transistor circuits in which two transistors are connected in series between a pair of signal input terminals are provided, and a transistor forming one pass transistor circuit and a transistor forming the other pass transistor circuit. To form two pairs of transistors, and apply a signal having an inverse relationship to each of the signal input terminal of one pass transistor circuit and the corresponding signal input terminal of the other pass transistor circuit. A logic circuit, characterized in that the respective conductive states of the two transistor pairs are respectively controlled by signals which are in an inverse relationship with each other.
１のＮチャンネル型ＭＯＳ電界効果トランジスタと、ソ
ース電極に前記第１の信号の反転信号が加えられる第２
のＮチャンネル型ＭＯＳ電界効果トランジスタとを直列
に接続してなる第１のパストランジスタ回路と、 ソース電極に前記第１の信号の反転信号が加えられる第
３のＮチャンネル型ＭＯＳ電界効果トランジスタと、ソ
ース電極に前記第１の信号が加えられる第４のＮチャン
ネル型ＭＯＳ電界効果トランジスタとを直列に接続して
なる第２のパストランジスタ回路とを含み、 前記第１のＮチャンネル型ＭＯＳ電界効果トランジスタ
のゲート電極および前記第３のＮチャンネル型ＭＯＳ電
界効果トランジスタのゲート電極に第２の信号が入力さ
れ、 前記第２のＮチャンネル型ＭＯＳ電界効果トランジスタ
のゲート電極および前記第４のＮチャンネル型ＭＯＳ電
界効果トランジスタのゲート電極に前記第２の信号の反
転信号が入力される論理回路。2. A first signal applied to the source electrode
1 N-channel MOS field effect transistor,
A second inverted signal of the first signal applied to the source electrode
N-channel type MOS field effect transistor in series
A first pass transistor circuit connected to the first pass transistor circuit and a source electrode to which an inverted signal of the first signal is applied.
3 N-channel MOS field effect transistor,
A fourth N channel to which the first signal is applied to the source electrode.
Connect the nell-type MOS field effect transistor in series
A second N-channel MOS field effect transistor including:
Gate electrode and the third N-channel MOS electrode
The second signal is input to the gate electrode of the field effect transistor.
And the second N-channel MOS field effect transistor
Gate electrode and the fourth N-channel MOS electrode
The gate electrode of the field effect transistor receives the second signal
A logic circuit to which a transfer signal is input.
１のＮチャンネル型ＭＯＳ電界効果トランジスタと、ソ
ース電極に第２の信号が加えられる第２のＮチャンネル
型ＭＯＳ電界効果トランジスタとを直列に接続してなる
第１のパストランジスタ回路と、 ソース電極に前記第１の信号の反転信号が加えられる第
３のＮチャンネル型ＭＯＳ電界効果トランジスタと、ソ
ース電極に前記第２の信号の反転信号が加えられる第４
のＮチャンネル型ＭＯＳ電界効果トランジスタとを直列
に接続してなる第２のパストランジスタ回路とを含み、 前記第１のＮチャンネル型ＭＯＳ電界効果トランジスタ
のゲート電極および前記第３のＮチャンネル型ＭＯＳ電
界効果トランジスタのゲート電極に前記第２の信号が入
力され、 前記第２のＮチャンネル型ＭＯＳ電界効果トランジスタ
のゲート電極および前記第４のＮチャンネル型ＭＯＳ電
界効果トランジスタのゲート電極に前記第２の信号の反
転信号が入力される論理回路。3. A first N-channel type MOS field effect transistor to which a first signal is applied to a source electrode and a second N-channel type MOS field effect transistor to which a second signal is applied to a source electrode are connected in series. A first pass transistor circuit connected to the source electrode, a third N-channel MOS field effect transistor to the source electrode of which the inverted signal of the first signal is applied, and an inverted signal of the second signal of the source electrode. Fourth added
A second pass transistor circuit in which the N-channel MOS field effect transistor is connected in series, and the gate electrode of the first N-channel MOS field effect transistor and the third N-channel MOS electric field are provided. The second signal is input to the gate electrode of the effect transistor, and the second signal is input to the gate electrode of the second N-channel MOS field effect transistor and the gate electrode of the fourth N-channel MOS field effect transistor. A logic circuit to which the inverted signal of is input.
１のＮチャンネル型ＭＯＳ電界効果トランジスタと、ソ
ース電極に第２の信号が加えられる第２のＮチャンネル
型ＭＯＳ電界効果トランジスタとを直列に接続してなる
第１のパストランジスタ回路と、 ソース電極に前記第１の信号の反転信号が加えられる第
３のＮチャンネル型ＭＯＳ電界効果トランジスタと、ソ
ース電極に前記第２の信号の反転信号が加えられる第４
のＮチャンネル型ＭＯＳ電界効果トランジスタとを直列
に接続してなる第２のパストランジスタ回路とを含み、 前記第１のＮチャンネル型ＭＯＳ電界効果トランジスタ
のゲート電極および前記第３のＮチャンネル型ＭＯＳ電
界効果トランジスタのゲート電極に前記第２の信号が入
力され、 前記第２のＮチャンネル型ＭＯＳ電界効果トランジスタ
のゲート電極および前記第４のＮチャンネル型ＭＯＳ電
界効果トランジスタのゲート電極に前記第２の信号の反
転信号が入力される論理回路。4. A first N-channel type MOS field effect transistor to which a first signal is applied to a source electrode and a second N-channel type MOS field effect transistor to which a second signal is applied to a source electrode are connected in series. A first pass transistor circuit connected to the source electrode, a third N-channel MOS field effect transistor to the source electrode of which the inverted signal of the first signal is applied, and an inverted signal of the second signal of the source electrode. Fourth added
A second pass transistor circuit in which the N-channel MOS field effect transistor is connected in series, and the gate electrode of the first N-channel MOS field effect transistor and the third N-channel MOS electric field are provided. The second signal is input to the gate electrode of the effect transistor, and the second signal is input to the gate electrode of the second N-channel MOS field effect transistor and the gate electrode of the fourth N-channel MOS field effect transistor. A logic circuit to which the inverted signal of is input.
自己の出力を相手の入力組の一つとして入力してなる駆
動回路を有し、前記第１のパストランジスタ回路の出力
および前記第２のパストランジスタ回路の出力を増幅し
て出力することを特徴とする請求項１記載の論理回路。5. A drive circuit comprising two BiCMOS amplifier circuits, each of which outputs its own output as one of the other input sets, the output of the first pass transistor circuit and the second path. 2. The logic circuit according to claim 1, wherein the output of the transistor circuit is amplified and output.
Ｓ電界効果トランジスタとが直列に接続され、この出力
用バイポーラトランジスタのベース電位をＣＭＯＳイン
バータで駆動する型の２つの増幅回路を、互いに自己の
出力を相手の入力組の一つとして入力してなる駆動回路
を有し、 前記第１のパストランジスタ回路の出力が、前記駆動回
路の一方の増幅回路に入力され、前記第２のパストラン
ジスタ回路の出力が、前記駆動回路の他方の増幅回路に
入力されることを特徴とする請求項２，請求項３または
請求項４記載の論理回路。6. An output bipolar transistor and an MO
An S field effect transistor is connected in series, and two amplifier circuits of a type in which the base potential of the output bipolar transistor is driven by a CMOS inverter are input to each other as their own outputs as one of the other input sets. A drive circuit, the output of the first pass transistor circuit is input to one amplification circuit of the drive circuit, and the output of the second pass transistor circuit is input to the other amplification circuit of the drive circuit. 5. The logic circuit according to claim 2, claim 3, or claim 4.
するトランジスタおよび前記第２のパストランジスタ回
路を構成するトランジスタの導通状態を制御する互いに
反転関係にある一組の信号の入力端子に、プルアップト
ランジスタが設けられていることを特徴とする請求項１
または請求項５記載の論理回路。7. A pull-up is provided to an input terminal of a pair of signals which are in an inverse relationship to each other and which controls the conduction states of a transistor forming the first pass transistor circuit and a transistor forming the second pass transistor circuit. A transistor is provided, The transistor of Claim 1 characterized by the above-mentioned.
Alternatively, the logic circuit according to claim 5.
の信号の反転信号入力端子のそれぞれにプルアップ用の
Ｐチャンネル型ＭＯＳ電界効果トランジスタが設けら
れ、それぞれのＰチャンネル型ＭＯＳ電界効果トランジ
スタは、自己がプルアップすべき信号とは反転関係にあ
る信号により導通状態が制御されることを特徴とする請
求項２，請求項３，請求項４または請求項６記載の論理
回路。8. The second signal input terminal and the second signal input terminal
A P-channel MOS field-effect transistor for pull-up is provided at each of the inverted signal input terminals of the signal of FIG. 7. The logic circuit according to claim 2, claim 3, claim 4, or claim 6, wherein the conduction state is controlled by the.
するトランジスタおよび前記第２のパストランジスタ回
路を構成するトランジスタの導通状態を制御する互いに
反転関係にある一組の信号の入力端子に、プルアップト
ランジスタおよびプルダウントランジスタが設けられて
いることを特徴とする請求項１または請求項５記載の論
理回路。9. A pull-up is provided to an input terminal of a pair of signals which are in an inverse relationship to each other and which controls conduction states of a transistor forming the first pass transistor circuit and a transistor forming the second pass transistor circuit. The logic circuit according to claim 1 or 5, further comprising a transistor and a pull-down transistor.
２の信号の反転信号入力端子のそれぞれに、プルアップ
用のＰチャンネル型ＭＯＳ電界効果トランジスタおよび
プルダウン用のＮチャンネル型ＭＯＳ電界効果トランジ
スタが設けられ、それぞれのＰチャンネル型ＭＯＳ電界
効果トランジスタおよびＮチャンネル型ＭＯＳ電界効果
トランジスタは、自己がプルアップまたはプルダウンす
べき信号とは反転関係にある信号により導通状態が制御
されることを特徴とする請求項２，請求項３，請求項４
または請求項６記載の論理回路。10. A P-channel MOS field-effect transistor for pull-up and an N-channel MOS field-effect transistor for pull-down are provided at each of the second signal input terminal and the inverted signal input terminal of the second signal. Each of the P-channel MOS field effect transistor and the N-channel MOS field effect transistor provided is characterized in that its conduction state is controlled by a signal having an inverse relationship with a signal to be pulled up or pulled down by itself. Claim 2, Claim 3, Claim 4
Alternatively, the logic circuit according to claim 6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4007023A JP2760195B2 (en) | 1992-01-20 | 1992-01-20 | Logic circuit |
| EP19930100798 EP0552734A3 (en) | 1992-01-20 | 1993-01-20 | High speed logic circuit having a reduced number of critical path gate stages |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4007023A JP2760195B2 (en) | 1992-01-20 | 1992-01-20 | Logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05211437A true JPH05211437A (en) | 1993-08-20 |
| JP2760195B2 JP2760195B2 (en) | 1998-05-28 |
Family
ID=11654447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4007023A Expired - Fee Related JP2760195B2 (en) | 1992-01-20 | 1992-01-20 | Logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2760195B2 (en) |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120028315A (en) * | 2009-04-30 | 2012-03-22 | 텔라 이노베이션스, 인코포레이티드 | Circuitry and layouts for xor and xnor logic |
| US8756551B2 (en) | 2007-08-02 | 2014-06-17 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
| US8759985B2 (en) | 2008-03-27 | 2014-06-24 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
| US8816402B2 (en) | 2008-03-13 | 2014-08-26 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor |
| US8823062B2 (en) | 2006-03-09 | 2014-09-02 | Tela Innovations, Inc. | Integrated circuit with offset line end spacings in linear gate electrode level |
| US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
| US8951916B2 (en) | 2007-12-13 | 2015-02-10 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
| US8966424B2 (en) | 2007-03-07 | 2015-02-24 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
| US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
| US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
| US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
| US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
| US9202779B2 (en) | 2008-01-31 | 2015-12-01 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
| US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
| US9240413B2 (en) | 2006-03-09 | 2016-01-19 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
| US9269702B2 (en) | 2009-10-13 | 2016-02-23 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the same |
| US9336344B2 (en) | 2006-03-09 | 2016-05-10 | Tela Innovations, Inc. | Coarse grid design methods and structures |
| US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
| US9633987B2 (en) | 2007-03-05 | 2017-04-25 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
| US9754878B2 (en) | 2006-03-09 | 2017-09-05 | Tela Innovations, Inc. | Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires |
-
1992
- 1992-01-20 JP JP4007023A patent/JP2760195B2/en not_active Expired - Fee Related
Cited By (78)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9754878B2 (en) | 2006-03-09 | 2017-09-05 | Tela Innovations, Inc. | Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires |
| US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
| US9425273B2 (en) | 2006-03-09 | 2016-08-23 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same |
| US9589091B2 (en) | 2006-03-09 | 2017-03-07 | Tela Innovations, Inc. | Scalable meta-data objects |
| US9336344B2 (en) | 2006-03-09 | 2016-05-10 | Tela Innovations, Inc. | Coarse grid design methods and structures |
| US9425272B2 (en) | 2006-03-09 | 2016-08-23 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same |
| US8823062B2 (en) | 2006-03-09 | 2014-09-02 | Tela Innovations, Inc. | Integrated circuit with offset line end spacings in linear gate electrode level |
| US10230377B2 (en) | 2006-03-09 | 2019-03-12 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
| US10217763B2 (en) | 2006-03-09 | 2019-02-26 | Tela Innovations, Inc. | Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid |
| US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
| US10186523B2 (en) | 2006-03-09 | 2019-01-22 | Tela Innovations, Inc. | Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid |
| US10141334B2 (en) | 2006-03-09 | 2018-11-27 | Tela Innovations, Inc. | Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures |
| US10141335B2 (en) | 2006-03-09 | 2018-11-27 | Tela Innovations, Inc. | Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures |
| US9425145B2 (en) | 2006-03-09 | 2016-08-23 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
| US9917056B2 (en) | 2006-03-09 | 2018-03-13 | Tela Innovations, Inc. | Coarse grid design methods and structures |
| US9240413B2 (en) | 2006-03-09 | 2016-01-19 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
| US8921896B2 (en) | 2006-03-09 | 2014-12-30 | Tela Innovations, Inc. | Integrated circuit including linear gate electrode structures having different extension distances beyond contact |
| US8921897B2 (en) | 2006-03-09 | 2014-12-30 | Tela Innovations, Inc. | Integrated circuit with gate electrode conductive structures having offset ends |
| US8946781B2 (en) | 2006-03-09 | 2015-02-03 | Tela Innovations, Inc. | Integrated circuit including gate electrode conductive structures with different extension distances beyond contact |
| US8952425B2 (en) | 2006-03-09 | 2015-02-10 | Tela Innovations, Inc. | Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length |
| US9443947B2 (en) | 2006-03-09 | 2016-09-13 | Tela Innovations, Inc. | Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same |
| US9673825B2 (en) | 2006-03-09 | 2017-06-06 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
| US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
| US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
| US9905576B2 (en) | 2006-03-09 | 2018-02-27 | Tela Innovations, Inc. | Semiconductor chip including region having rectangular-shaped gate structures and first metal structures |
| US9859277B2 (en) | 2006-03-09 | 2018-01-02 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
| US9711495B2 (en) | 2006-03-09 | 2017-07-18 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
| US9741719B2 (en) | 2006-03-09 | 2017-08-22 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
| US9633987B2 (en) | 2007-03-05 | 2017-04-25 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
| US10074640B2 (en) | 2007-03-05 | 2018-09-11 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
| US9595515B2 (en) | 2007-03-07 | 2017-03-14 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit defined within dynamic array section |
| US9424387B2 (en) | 2007-03-07 | 2016-08-23 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
| US8966424B2 (en) | 2007-03-07 | 2015-02-24 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
| US9910950B2 (en) | 2007-03-07 | 2018-03-06 | Tela Innovations, Inc. | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
| US8756551B2 (en) | 2007-08-02 | 2014-06-17 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
| US8759882B2 (en) | 2007-08-02 | 2014-06-24 | Tela Innovations, Inc. | Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos |
| US10734383B2 (en) | 2007-10-26 | 2020-08-04 | Tela Innovations, Inc. | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits |
| US8951916B2 (en) | 2007-12-13 | 2015-02-10 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
| US9281371B2 (en) | 2007-12-13 | 2016-03-08 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
| US10461081B2 (en) | 2007-12-13 | 2019-10-29 | Tel Innovations, Inc. | Super-self-aligned contacts and method for making the same |
| US9818747B2 (en) | 2007-12-13 | 2017-11-14 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
| US9530734B2 (en) | 2008-01-31 | 2016-12-27 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
| US9202779B2 (en) | 2008-01-31 | 2015-12-01 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
| US9208279B2 (en) | 2008-03-13 | 2015-12-08 | Tela Innovations, Inc. | Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods |
| US9117050B2 (en) | 2008-03-13 | 2015-08-25 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications |
| US10727252B2 (en) | 2008-03-13 | 2020-07-28 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same |
| US10658385B2 (en) | 2008-03-13 | 2020-05-19 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on four gate electrode tracks |
| US9536899B2 (en) | 2008-03-13 | 2017-01-03 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same |
| US10651200B2 (en) | 2008-03-13 | 2020-05-12 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on three gate electrode tracks |
| US8816402B2 (en) | 2008-03-13 | 2014-08-26 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor |
| US8836045B2 (en) | 2008-03-13 | 2014-09-16 | Tela Innovations, Inc. | Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track |
| US8835989B2 (en) | 2008-03-13 | 2014-09-16 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications |
| US9245081B2 (en) | 2008-03-13 | 2016-01-26 | Tela Innovations, Inc. | Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods |
| US9213792B2 (en) | 2008-03-13 | 2015-12-15 | Tela Innovations, Inc. | Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods |
| US8847331B2 (en) | 2008-03-13 | 2014-09-30 | Tela Innovations, Inc. | Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures |
| US8847329B2 (en) | 2008-03-13 | 2014-09-30 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts |
| US8853794B2 (en) | 2008-03-13 | 2014-10-07 | Tela Innovations, Inc. | Integrated circuit within semiconductor chip including cross-coupled transistor configuration |
| US8853793B2 (en) | 2008-03-13 | 2014-10-07 | Tela Innovations, Inc. | Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends |
| US10020321B2 (en) | 2008-03-13 | 2018-07-10 | Tela Innovations, Inc. | Cross-coupled transistor circuit defined on two gate electrode tracks |
| US8866197B2 (en) | 2008-03-13 | 2014-10-21 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature |
| US8872283B2 (en) | 2008-03-13 | 2014-10-28 | Tela Innovations, Inc. | Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature |
| US9871056B2 (en) | 2008-03-13 | 2018-01-16 | Tela Innovations, Inc. | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same |
| US9081931B2 (en) | 2008-03-13 | 2015-07-14 | Tela Innovations, Inc. | Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer |
| US9779200B2 (en) | 2008-03-27 | 2017-10-03 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
| US8759985B2 (en) | 2008-03-27 | 2014-06-24 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
| US9390215B2 (en) | 2008-03-27 | 2016-07-12 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
| US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
| KR20160136459A (en) * | 2009-04-30 | 2016-11-29 | 텔라 이노베이션스, 인코포레이티드 | Circuitry and layouts for xor and xnor logic |
| KR20120028315A (en) * | 2009-04-30 | 2012-03-22 | 텔라 이노베이션스, 인코포레이티드 | Circuitry and layouts for xor and xnor logic |
| JP2012525774A (en) * | 2009-04-30 | 2012-10-22 | テラ イノヴェイションズ インコーポレイテッド | XOR and XNOR logic circuit and layout |
| JP2017069981A (en) * | 2009-04-30 | 2017-04-06 | テラ イノヴェイションズ インコーポレイテッド | Circuitry and layout for xor and xnor logic |
| KR20160075788A (en) * | 2009-04-30 | 2016-06-29 | 텔라 이노베이션스, 인코포레이티드 | Circuitry and layouts for xor and xnor logic |
| US10446536B2 (en) | 2009-05-06 | 2019-10-15 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
| US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
| US9530795B2 (en) | 2009-10-13 | 2016-12-27 | Tela Innovations, Inc. | Methods for cell boundary encroachment and semiconductor devices implementing the same |
| US9269702B2 (en) | 2009-10-13 | 2016-02-23 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the same |
| US9704845B2 (en) | 2010-11-12 | 2017-07-11 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
| US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2760195B2 (en) | 1998-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2760195B2 (en) | Logic circuit | |
| EP0196113A2 (en) | Tri-state buffer circuit | |
| JPH0353782B2 (en) | ||
| JP2861910B2 (en) | Output circuit | |
| US7196550B1 (en) | Complementary CMOS driver circuit with de-skew control | |
| JP2551586B2 (en) | Interface circuit | |
| JP2830244B2 (en) | Tri-state buffer circuit | |
| JPH05122049A (en) | Output buffer circuit | |
| KR930015344A (en) | Bipolar-complementary metal oxide semiconductor (BICMOS) output buffer circuit with complementary metal oxide semiconductor (CMOS) data path and bipolar current amplification | |
| JPH06326592A (en) | Electronic circuit with driver circuit | |
| EP0552734A2 (en) | High speed logic circuit having a reduced number of critical path gate stages | |
| JPH11122092A (en) | Signal level conversion circuit | |
| JPH11177408A (en) | Cmos driver circuit | |
| JP2903885B2 (en) | CMOS output buffer circuit | |
| JP3055165B2 (en) | Output buffer circuit | |
| JPS61126818A (en) | Output buffer driver circuit | |
| JP2903835B2 (en) | Logic circuit | |
| JPS62231521A (en) | Semiconductor integrated circuit | |
| JP2808913B2 (en) | Connection circuit between semiconductor integrated circuits | |
| JPH01286616A (en) | Bicmos logic circuit | |
| JPH03283815A (en) | Output buffer circuit | |
| JPS5990426A (en) | Tri-state buffer circuit | |
| JPH05199099A (en) | Output buffer circuit | |
| JPH01286617A (en) | Bicmos logic circuit | |
| JPS6097726A (en) | Cmos output buffer circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980217 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080320 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090320 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090320 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100320 Year of fee payment: 12 |
|
| LAPS | Cancellation because of no payment of annual fees |