JPH05206801A - Delay circuit - Google Patents
Delay circuitInfo
- Publication number
- JPH05206801A JPH05206801A JP4012137A JP1213792A JPH05206801A JP H05206801 A JPH05206801 A JP H05206801A JP 4012137 A JP4012137 A JP 4012137A JP 1213792 A JP1213792 A JP 1213792A JP H05206801 A JPH05206801 A JP H05206801A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- circuit
- capacitor
- thin film
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は遅延回路に関する。FIELD OF THE INVENTION The present invention relates to a delay circuit.
【０００２】[0002]
【従来の技術】従来、ＣＲの時定数を利用した遅延回路
では、遅延用の抵抗とトランジスタ回路とを同一のシリ
コン基板に集積化する場合、遅延用の抵抗には拡散抵抗
を用いていた。図５は、遅延用の抵抗に拡散抵抗を用い
た場合のシリコン集積回路の断面図である。６１はシリ
コン基板、６２は低濃度拡散層、６３はフィールド絶縁
層、６４はコンタクト用の高濃度拡散層、６５は層間絶
縁層、６６は引出し用電極である。すなわち、低濃度拡
散層６２を拡散抵抗として用いている。2. Description of the Related Art Conventionally, in a delay circuit using a CR time constant, when a delay resistor and a transistor circuit are integrated on the same silicon substrate, a diffused resistor is used as the delay resistor. FIG. 5 is a cross-sectional view of a silicon integrated circuit in which a diffused resistor is used as a delay resistor. Reference numeral 61 is a silicon substrate, 62 is a low concentration diffusion layer, 63 is a field insulating layer, 64 is a high concentration diffusion layer for contact, 65 is an interlayer insulating layer, and 66 is an extraction electrode. That is, the low concentration diffusion layer 62 is used as the diffusion resistance.
【０００３】[0003]
【発明が解決しようとする課題】拡散抵抗では抵抗値自
体のバラツキや抵抗値の温度変化が大きく（総合的な抵
抗値のバラツキは±４０％程度）、高精度の抵抗を形成
することが困難である。したがって、遅延用の抵抗とト
ランジスタ回路とを同一のシリコン基板に集積化する場
合、精度のよい遅延回路を実現することができなかっ
た。With diffused resistors, variations in the resistance value itself and changes in the resistance value with temperature are large (total variation in resistance value is about ± 40%), and it is difficult to form a highly accurate resistor. Is. Therefore, when the delay resistor and the transistor circuit are integrated on the same silicon substrate, an accurate delay circuit cannot be realized.
【０００４】本発明の目的は、高精度の抵抗をトランジ
スタ回路が形成されたシリコン基板に集積化し、精度の
よい遅延回路を得ることである。An object of the present invention is to integrate a high-precision resistor on a silicon substrate on which a transistor circuit is formed to obtain a highly accurate delay circuit.
【０００５】[0005]
【課題を解決するための手段】本発明における遅延回路
は、遅延用の抵抗とトランジスタ回路とを同一のシリコ
ン基板上に形成するとともに、遅延用の抵抗を薄膜抵抗
を用いて形成したものである。In the delay circuit of the present invention, the delay resistor and the transistor circuit are formed on the same silicon substrate, and the delay resistor is formed by using a thin film resistor. ..
【０００６】[0006]
【実施例】図１は、本発明における遅延回路の第１実施
例を示した電気回路図である。１は薄膜抵抗を用いて形
成された抵抗、２はキャパシタ、３〜８はＭＯＳトラン
ジスタ、９および１０はＣＭＯＳインバ―タ、１１はシ
ュミットトリガタイプのＣＭＯＳインバ―タ、１２はＣ
ＭＯＳナンドゲートである。抵抗１とトランジスタ回路
（ＭＯＳトランジスタ３〜８、ＣＭＯＳインバ―タ９お
よび１０、シュミットトリガタイプのＣＭＯＳインバ―
タ１１並びにＣＭＯＳナンドゲート１２）とは、同一の
シリコン基板上、すなわち同一の集積回路内に形成され
ている。キャパシタ２は、上記トランジスタ回路が形成
された集積回路内に形成してもよいし、集積回路外に外
付けしてもよい。1 is an electric circuit diagram showing a first embodiment of a delay circuit according to the present invention. 1 is a resistor formed by using a thin film resistor, 2 is a capacitor, 3 to 8 are MOS transistors, 9 and 10 are CMOS inverters, 11 is a Schmitt trigger type CMOS inverter, and 12 is C.
It is a MOS NAND gate. Resistor 1 and transistor circuit (MOS transistors 3 to 8, CMOS inverters 9 and 10, Schmitt trigger type CMOS inverter)
The gate 11 and the CMOS NAND gate 12) are formed on the same silicon substrate, that is, in the same integrated circuit. The capacitor 2 may be formed inside the integrated circuit in which the transistor circuit is formed, or may be externally attached outside the integrated circuit.
【０００７】図２は、図１の遅延回路の動作を示したタ
イミングチャートである。以下、このタイミングチャー
トを用いて動作を説明する。FIG. 2 is a timing chart showing the operation of the delay circuit of FIG. The operation will be described below with reference to this timing chart.
【０００８】まず、入力端子“ＩＮ”が論理値“０”の
ときには、ＭＯＳトランジスタ３および７がオン状態、
ＭＯＳトランジスタ４、６および８がオフ状態となって
いる。したがって、キャパシタ２にはＭＯＳトランジス
タ３を通して電荷が充電されており、また、ＭＯＳトラ
ンジスタ５および６で構成される定電流回路はオフ状態
となっている。First, when the input terminal "IN" has the logical value "0", the MOS transistors 3 and 7 are turned on,
MOS transistors 4, 6 and 8 are off. Therefore, the capacitor 2 is charged with electric charge through the MOS transistor 3, and the constant current circuit constituted by the MOS transistors 5 and 6 is in the off state.
【０００９】入力端子“ＩＮ”が論理値“１”になる
と、ＭＯＳトランジスタ４がオン状態、ＭＯＳトランジ
スタ３および７がオフ状態となる。その結果、抵抗１を
通してＭＯＳトランジスタ５に定電流が流れ、キャパシ
タ２の電荷がＭＯＳトランジスタ６を通して放電され
る。そして、キャパシタ２の電位がシュミットトリガＣ
ＭＯＳインバ―タ１１の反転電位よりも低くなると、シ
ュミットトリガＣＭＯＳインバ―タ１１の出力が反転し
て論理値“１”となる。すなわち、抵抗１とキャパシタ
２とはＭＯＳトランジスタ５および６で構成される定電
流回路を介して間接的に結合されているため、入力信号
は抵抗１とキャパシタ２とで定まる時定数に基いて遅延
されるわけである。以後、ＭＯＳトランジスタ８もオン
状態となり、キャパシタ２の電荷はＭＯＳトランジスタ
８を通して急激に放電される。When the input terminal "IN" becomes the logical value "1", the MOS transistor 4 is turned on and the MOS transistors 3 and 7 are turned off. As a result, a constant current flows through the MOS transistor 5 through the resistor 1 and the charge of the capacitor 2 is discharged through the MOS transistor 6. The potential of the capacitor 2 is the Schmitt trigger C
When it becomes lower than the inversion potential of the MOS inverter 11, the output of the Schmitt trigger CMOS inverter 11 is inverted and becomes the logical value "1". That is, since the resistor 1 and the capacitor 2 are indirectly coupled via the constant current circuit composed of the MOS transistors 5 and 6, the input signal is delayed based on the time constant determined by the resistor 1 and the capacitor 2. It is done. After that, the MOS transistor 8 is also turned on, and the charge of the capacitor 2 is rapidly discharged through the MOS transistor 8.
【００１０】入力端子“ＩＮ”が論理値が再び“０”に
なると、キャパシタ２にはＭＯＳトランジスタ３を通し
て電荷が充電される。そして、キャパシタ２の電位がシ
ュミットトリガＣＭＯＳインバ―タ１１の反転電位より
も高くなると、シュミットトリガＣＭＯＳインバ―タ１
１の出力が反転して論理値“０”となる。When the logic value of the input terminal "IN" becomes "0" again, the capacitor 2 is charged with the electric charge through the MOS transistor 3. When the potential of the capacitor 2 becomes higher than the inversion potential of the Schmitt trigger CMOS inverter 11, the Schmitt trigger CMOS inverter 1
The output of 1 is inverted and becomes a logical value "0".
【００１１】図３は図１の抵抗１（薄膜抵抗）の構成を
示した断面図であり、図４は図１のトランジスタ回路
（ＭＯＳトランジスタ３〜８、ＣＭＯＳインバ―タ９お
よび１０、シュミットトリガタイプのＣＭＯＳインバ―
タ１１並びにＣＭＯＳナンドゲート１２）に用いるＭＯ
Ｓトランジスタの構成を示した断面図である。抵抗１と
トランジスタ回路とは同一のシリコン基板上に形成され
ている。２１はＮ型のシリコン基板、２２はＰ型の低濃
度拡散層、２３はゲ―ト絶縁層、２４はフィ―ルド絶縁
層（形成材料は酸化シリコン）、２５はゲ―ト電極（形
成材料はモリブデン等）、２６はソ―ス／ドレインを形
成する高濃度拡散層である。２７は薄膜抵抗層であり、
ＮｉＣｒ系やＳｉＣｒ系の薄膜抵抗材料を用いて形成さ
れている。２８は層間絶縁層（形成材料は酸化シリコ
ン）である。２９はソ―ス／ドレイン用引出し電極およ
び薄膜抵抗用引出し電極であり、両者はアルミニウムを
用いて同一の工程で形成されている。薄膜抵抗層２７
は、従来の拡散抵抗に比べて高精度の抵抗値のものが形
成できるため（総合的な抵抗値のバラツキは±５％程
度）、精度のよい遅延回路を実現することができる。FIG. 3 is a sectional view showing the structure of the resistor 1 (thin film resistor) of FIG. 1, and FIG. 4 is the transistor circuit of FIG. 1 (MOS transistors 3 to 8, CMOS inverters 9 and 10, Schmitt trigger). Type of CMOS Inver
MO to be used for the memory 11 and the CMOS NAND gate 12)
It is sectional drawing which showed the structure of the S transistor. The resistor 1 and the transistor circuit are formed on the same silicon substrate. Reference numeral 21 is an N-type silicon substrate, 22 is a P-type low-concentration diffusion layer, 23 is a gate insulating layer, 24 is a field insulating layer (silicon oxide is a forming material), and 25 is a gate electrode (a forming material). Is a molybdenum or the like), and 26 is a high concentration diffusion layer forming a source / drain. 27 is a thin film resistance layer,
It is formed by using a NiCr-based or SiCr-based thin film resistance material. Reference numeral 28 is an interlayer insulating layer (forming material is silicon oxide). Reference numeral 29 denotes a source / drain lead-out electrode and a thin-film resistor lead-out electrode, both of which are formed of aluminum in the same step. Thin film resistance layer 27
Since it is possible to form a resistor having a resistance value with a higher precision than that of the conventional diffused resistor (the total variation in the resistance value is about ± 5%), it is possible to realize an accurate delay circuit.
【００１２】図６は、本発明における遅延回路の第２実
施例を示した電気回路図である。４１は薄膜抵抗を用い
て形成された抵抗、４２はキャパシタ、４３はＭＯＳト
ランジスタ、４４および４５はＣＭＯＳインバ―タであ
る。抵抗４１とトランジスタ回路（ＭＯＳトランジスタ
４３、ＣＭＯＳインバ―タ４４および４５）とは、同一
のシリコン基板上、すなわち同一の集積回路内に形成さ
れている。キャパシタ４２は、上記トランジスタ回路が
形成された集積回路内に形成してもよいし、集積回路外
に外付けしてもよい。抵抗４１（薄膜抵抗）の構成およ
びトランジスタ回路に用いるＭＯＳトランジスタの構成
は、上記第１実施例と同様である（図３および図４参
照）。本実施例においても、遅延用の抵抗４１に薄膜抵
抗を用いているので、上記第１実施例と同様の効果を得
ることができる。FIG. 6 is an electric circuit diagram showing a second embodiment of the delay circuit according to the present invention. Reference numeral 41 is a resistor formed by using a thin film resistor, 42 is a capacitor, 43 is a MOS transistor, and 44 and 45 are CMOS inverters. The resistor 41 and the transistor circuit (MOS transistor 43, CMOS inverters 44 and 45) are formed on the same silicon substrate, that is, in the same integrated circuit. The capacitor 42 may be formed inside the integrated circuit in which the transistor circuit is formed, or may be externally attached outside the integrated circuit. The configuration of the resistor 41 (thin film resistor) and the configuration of the MOS transistor used in the transistor circuit are the same as those in the first embodiment (see FIGS. 3 and 4). Also in this embodiment, since the thin film resistor is used as the delay resistor 41, the same effect as that of the first embodiment can be obtained.
【００１３】[0013]
【発明の効果】本発明では、遅延用の抵抗を薄膜抵抗を
用いて形成したため、高精度の抵抗値が得られ、精度の
よい遅延回路を実現することができる。According to the present invention, since the resistance for delay is formed by using the thin film resistance, the resistance value with high accuracy can be obtained and the delay circuit with high accuracy can be realized.
【図１】本発明における遅延回路の第１実施例を示した
電気回路図である。FIG. 1 is an electric circuit diagram showing a first embodiment of a delay circuit according to the present invention.
【図２】図１の遅延回路の動作を示したタイミングチャ
ートである。FIG. 2 is a timing chart showing the operation of the delay circuit of FIG.
【図３】図１の抵抗１の構成を示した断面図である。3 is a cross-sectional view showing a configuration of a resistor 1 of FIG.
【図４】図１のトランジスタ回路を構成するＭＯＳトラ
ンジスタの構成を示した断面図である。FIG. 4 is a cross-sectional view showing a configuration of a MOS transistor that constitutes the transistor circuit of FIG.
【図５】従来例を示したものであり、遅延用の抵抗に拡
散抵抗を用いた場合のシリコン集積回路の断面図であ
る。FIG. 5 shows a conventional example, and is a cross-sectional view of a silicon integrated circuit in which a diffused resistor is used as a delay resistor.
【図６】本発明における遅延回路の第２実施例を示した
電気回路図である。FIG. 6 is an electric circuit diagram showing a second embodiment of the delay circuit according to the present invention.
１……抵抗 ２……キャパシタ ３〜８……ＭＯＳトランジスタ ９、１０……ＣＭＯＳインバ―タ １１……シュミットトリガタイプのＣＭＯＳインバ―タ １２……ＣＭＯＳナンドゲート ２１……シリコン基板 ２７……薄膜抵抗層 ４１……抵抗 ４２……キャパシタ ４３……ＭＯＳトランジスタ ４４、４５……ＣＭＯＳインバ―タ 1 ... Resistor 2 ... Capacitor 3-8 ... MOS transistor 9, 10 ... CMOS inverter 11 ... Schmitt trigger type CMOS inverter 12 ... CMOS NAND gate 21 ... Silicon substrate 27 ... Thin film resistor Layer 41 ... Resistor 42 ... Capacitor 43 ... MOS transistor 44, 45 ... CMOS inverter
Claims (1)
荷を充放電するトランジスタ回路とを有し、上記抵抗と
上記キャパシタとで定まる時定数に基いて遅延信号を生
じる遅延回路において、 上記トランジスタ回路および上記抵抗を同一のシリコン
基板上に形成するとともに、上記抵抗を薄膜抵抗を用い
て形成したことを特徴とする遅延回路。1. A delay circuit having a resistor, a capacitor, and a transistor circuit for charging and discharging the charge of the capacitor, wherein the delay circuit generates a delay signal based on a time constant determined by the resistor and the capacitor. A delay circuit characterized in that the resistors are formed on the same silicon substrate and the resistors are formed by using thin film resistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4012137A JPH05206801A (en) | 1992-01-27 | 1992-01-27 | Delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4012137A JPH05206801A (en) | 1992-01-27 | 1992-01-27 | Delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05206801A true JPH05206801A (en) | 1993-08-13 |
Family
ID=11797130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4012137A Pending JPH05206801A (en) | 1992-01-27 | 1992-01-27 | Delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05206801A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019133977A1 (en) * | 2017-12-29 | 2019-07-04 | Texas Instruments Incorporated | Delay based comparator |
| US11309903B1 (en) | 2020-12-23 | 2022-04-19 | Texas Instruments Incorporated | Sampling network with dynamic voltage detector for delay output |
| US11316525B1 (en) | 2021-01-26 | 2022-04-26 | Texas Instruments Incorporated | Lookup-table-based analog-to-digital converter |
| US11316526B1 (en) | 2020-12-18 | 2022-04-26 | Texas Instruments Incorporated | Piecewise calibration for highly non-linear multi-stage analog-to-digital converter |
| US11387840B1 (en) | 2020-12-21 | 2022-07-12 | Texas Instruments Incorporated | Delay folding system and method |
| US11424758B2 (en) | 2018-12-31 | 2022-08-23 | Texas Instruments Incorporated | Conversion and folding circuit for delay-based analog-to-digital converter system |
| US11438001B2 (en) | 2020-12-24 | 2022-09-06 | Texas Instruments Incorporated | Gain mismatch correction for voltage-to-delay preamplifier array |
| US11595053B2 (en) | 2018-12-12 | 2023-02-28 | Texas Instruments Incorporated | Analog-to-digital converter with interpolation |
| US11881867B2 (en) | 2021-02-01 | 2024-01-23 | Texas Instruments Incorporated | Calibration scheme for filling lookup table in an ADC |
| US11962318B2 (en) | 2021-01-12 | 2024-04-16 | Texas Instruments Incorporated | Calibration scheme for a non-linear ADC |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58136129A (en) * | 1982-02-08 | 1983-08-13 | Nippon Telegr & Teleph Corp <Ntt> | Waveform conversion circuit |
| JPS6235551A (en) * | 1985-08-08 | 1987-02-16 | Nec Corp | Constant-current source circuit of hybrid integrated circuit |
| JPS62142403A (en) * | 1985-12-17 | 1987-06-25 | Seiko Epson Corp | Source follower circuit |
-
1992
- 1992-01-27 JP JP4012137A patent/JPH05206801A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58136129A (en) * | 1982-02-08 | 1983-08-13 | Nippon Telegr & Teleph Corp <Ntt> | Waveform conversion circuit |
| JPS6235551A (en) * | 1985-08-08 | 1987-02-16 | Nec Corp | Constant-current source circuit of hybrid integrated circuit |
| JPS62142403A (en) * | 1985-12-17 | 1987-06-25 | Seiko Epson Corp | Source follower circuit |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019133977A1 (en) * | 2017-12-29 | 2019-07-04 | Texas Instruments Incorporated | Delay based comparator |
| US10958258B2 (en) | 2017-12-29 | 2021-03-23 | Texas Instruments Incorporated | Delay based comparator |
| US11316505B2 (en) | 2017-12-29 | 2022-04-26 | Texas Instruments Incorporated | Delay based comparator |
| US11595053B2 (en) | 2018-12-12 | 2023-02-28 | Texas Instruments Incorporated | Analog-to-digital converter with interpolation |
| US11424758B2 (en) | 2018-12-31 | 2022-08-23 | Texas Instruments Incorporated | Conversion and folding circuit for delay-based analog-to-digital converter system |
| US11316526B1 (en) | 2020-12-18 | 2022-04-26 | Texas Instruments Incorporated | Piecewise calibration for highly non-linear multi-stage analog-to-digital converter |
| US11387840B1 (en) | 2020-12-21 | 2022-07-12 | Texas Instruments Incorporated | Delay folding system and method |
| US11309903B1 (en) | 2020-12-23 | 2022-04-19 | Texas Instruments Incorporated | Sampling network with dynamic voltage detector for delay output |
| US11438001B2 (en) | 2020-12-24 | 2022-09-06 | Texas Instruments Incorporated | Gain mismatch correction for voltage-to-delay preamplifier array |
| US11962318B2 (en) | 2021-01-12 | 2024-04-16 | Texas Instruments Incorporated | Calibration scheme for a non-linear ADC |
| US11316525B1 (en) | 2021-01-26 | 2022-04-26 | Texas Instruments Incorporated | Lookup-table-based analog-to-digital converter |
| US11881867B2 (en) | 2021-02-01 | 2024-01-23 | Texas Instruments Incorporated | Calibration scheme for filling lookup table in an ADC |
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