JPH0520289A - Method for monitoring runaway of cpu circuit - Google Patents

Method for monitoring runaway of cpu circuit

Info

Publication number
JPH0520289A
JPH0520289A JP3169641A JP16964191A JPH0520289A JP H0520289 A JPH0520289 A JP H0520289A JP 3169641 A JP3169641 A JP 3169641A JP 16964191 A JP16964191 A JP 16964191A JP H0520289 A JPH0520289 A JP H0520289A
Authority
JP
Japan
Prior art keywords
cpu
retrigger
cpus
request
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3169641A
Other languages
Japanese (ja)
Inventor
Masayuki Mori
雅之 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP3169641A priority Critical patent/JPH0520289A/en
Publication of JPH0520289A publication Critical patent/JPH0520289A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To provide a CPU circuit runaway monitoring method capable of monitoring the runaway of plural CPUs by means of one watchdog timer circuit. CONSTITUTION:Plural CPUs 1 to (n) are connected in series, the watchdog timer circuit 7 is connected to the final stage CPU, a retrigger request is outputted from the leading CPU 1 to the succeeding CPU 2 at a fixed period, respective CPUs 2 to (n) successively transfer the retrigger request from each preceding CPU to each succeeding CPU, and the circuit 7 inputs the retrigger request from the final CPU n, and if the retrigger request is interrupted due to the runaway of any one of the CPUs, outputs a reset signal to all the CPUs to restore the runaway of the CPU.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、複数のＣＰＵを用いて
制御を行うＣＰＵ回路の暴走監視方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway monitoring method for a CPU circuit which controls using a plurality of CPUs.

【０００２】[0002]

【従来の技術】従来複数ＣＰＵ回路の暴走監視方法は、
図３に示すように、複数のＣＰＵ１，２にそれぞれ独立
にＷＤＴ（ウオッチドッグタイマ）回路７，８を接続
し、各ＣＰＵ１，２からそれぞれ独立にＷＤＴ回路７，
８の一定周期のリトリガ信号を発生させＷＤＴ回路７，
８に出力し、何れかのＣＰＵが暴走し、そのＣＰＵに対
応したＷＤＴ回路にリトリガ信号の入力がなくなると、
そのＷＤＴ回路はリセット信号を対応したＣＰＵに出力
しリセットをかけるか、又は論理和回路９を介して出力
し全ＣＰＵにリセットをかけてＣＰＵの暴走を復帰させ
ている。2. Description of the Related Art A conventional runaway monitoring method for a plurality of CPU circuits is as follows.
As shown in FIG. 3, WDT (watchdog timer) circuits 7 and 8 are independently connected to a plurality of CPUs 1 and 2, respectively, and WDT circuits 7 and 8 are independently provided from the CPUs 1 and 2, respectively.
8 WDT circuit 7,
If any CPU goes out of control and the WDT circuit corresponding to that CPU loses the input of the retrigger signal,
The WDT circuit outputs a reset signal to the corresponding CPU for resetting, or outputs it through the logical sum circuit 9 for resetting all CPUs to restore the runaway of the CPUs.

【０００３】[0003]

【発明が解決しようとする課題】ところで、上記従来の
ＣＰＵ回路の暴走監視方法では、ＣＰＵの数だけＷＤＴ
回路が必要となり、ＣＰＵの数が多くなると回路が複雑
なものとなる。そして複雑な回路であればあるほど信頼
性は低下し、かつ高価になる。By the way, in the above-mentioned conventional runaway monitoring method for the CPU circuit, the WDTs corresponding to the number of CPUs are used.
A circuit becomes necessary, and the circuit becomes complicated as the number of CPUs increases. The more complicated the circuit, the lower the reliability and the higher the cost.

【０００４】本発明は、従来のこのような問題点に鑑み
てなされたもので、その目的とするところは、複数ＣＰ
Ｕの暴走監視を１つのウオッチドッグタイマ回路を用い
てなしうるＣＰＵ回路の暴走監視方法を提供することに
ある。The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a plurality of CPs.
It is another object of the present invention to provide a runaway monitoring method for a CPU circuit, which can monitor runaway of U by using one watchdog timer circuit.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明のＣＰＵ回路の暴走監視方法は、複数のＣＰ
Ｕを直列に接続すると共に、その最後段のＣＰＵにウオ
ッチドッグタイマ回路を接続し、最前段のＣＰＵから一
定周期でその後段のＣＰＵにリトリガ要求を出力し、そ
のリトリガ要求が入力するＣＰＵから最後段の各ＣＰＵ
ではそれぞれその前段からのリトリガ要求の入力により
その後段のＣＰＵへ順次リトリガ要求を出力し、ウオッ
チドッグタイマ回路は最終段のＣＰＵからのリトリガ要
求が途絶えると全ＣＰＵにリセット信号を出力するよう
にしたものである。In order to achieve the above object, a method for monitoring runaway of a CPU circuit according to the present invention comprises a plurality of CPs.
In addition to connecting U in series, the watchdog timer circuit is connected to the CPU at the last stage, the CPU at the front stage outputs a retrigger request to the CPU at the subsequent stage at a constant cycle, and the CPU that receives the retrigger request outputs the retrigger Each CPU of the stage
Then, when the retrigger request is input from the preceding stage, the retrigger request is sequentially output to the CPUs in the subsequent stages, and the watchdog timer circuit outputs the reset signal to all CPUs when the retrigger request from the CPU in the final stage is interrupted. It is a thing.

【０００６】また上記暴走監視方法は、直列に接続した
ＣＰＵの一部を並列に接続し、この並列のＣＰＵからの
それぞれのリトリガ要求を後段のＣＰＵに出力し、その
後段のＣＰＵはその全てのリトリガ要求が入力されたこ
とを条件に後段ＣＰＵへリトリガ要求を出力するように
することもできる。In the runaway monitoring method, a part of the CPUs connected in series is connected in parallel, and each retrigger request from the parallel CPUs is output to the subsequent CPU, and the subsequent CPUs all of them. It is also possible to output the retrigger request to the subsequent CPU on condition that the retrigger request is input.

【０００７】[0007]

【作用】直列に接続されたＣＰＵが正常であれば、最前
段ＣＰＵから一定周期で後段にリトリガ要求が出力さ
れ、その後段から最終段のＣＰＵに順次前段からのリト
リガ要求の入力により後段のＣＰＵへリトリガ要求が出
力される。最終段のＣＰＵからリトリガ要求がウオッチ
ドッグタイマ（ＷＤＴ）回路に入力している間はウオッ
チドッグタイマ回路からは出力が発生しない。If the CPUs connected in series are normal, a retrigger request is output from the foremost-stage CPU to the latter-stage at a constant cycle, and the subsequent-stage CPUs are sequentially input to the latter-stage CPUs to the subsequent-stage CPUs. A trigger request is output. While the retrigger request from the final stage CPU is input to the watchdog timer (WDT) circuit, no output is generated from the watchdog timer circuit.

【０００８】直列に接続されたＣＰＵのうちの何れかが
暴走すると、暴走したＣＰＵからのリトリガ要求が出な
いので、最終段のＣＰＵからウオッチドッグタイマ回路
へのリトリガ信号が途絶する。このためウオッチドッグ
タイマ回路から全ＣＰＵへリセット信号が出力され、暴
走したＣＰＵは暴走から復帰する。When any one of the CPUs connected in series runs out of control, the rerunning signal from the CPU in the final stage to the watchdog timer circuit is interrupted because the rerunning request is not issued from the running out of CPU. Therefore, the watchdog timer circuit outputs a reset signal to all the CPUs, and the runaway CPU recovers from the runaway.

【０００９】ＣＰＵの一部を並列とした場合、その後段
のＣＰＵは並列に接続されたＣＰＵの全てのリトリガ要
求されたことを条件に後段ＣＰＵへリトリガ要求を出力
するので、並列接続されたＣＰＵの一方が暴走した場合
でも最終段ＣＰＵからウオッチドッグタイマへのリトリ
ガ要求はなくなり、ウオッチドッグタイマからリセット
信号が出力される。When a part of the CPUs are arranged in parallel, the CPUs in the subsequent stages output retrigger requests to the latter-stage CPUs on condition that all the retrigger requests of the CPUs connected in parallel have been issued. Even if one of the two runs out of control, the retrigger request from the final stage CPU to the watchdog timer disappears, and the reset signal is output from the watchdog timer.

【００１０】[0010]

【実施例】本発明の実施例を図面を参照して説明する。Embodiments of the present invention will be described with reference to the drawings.

【００１１】図１において、１〜３，ｎは直列に接続さ
れた複数のＣＰＵ、７は最後段のＣＰＵｎに接続された
ＷＤＴ回路である。ＣＰＵ１は一定周期毎にＣＰＵ２へ
リトリガ要求する。ＣＰＵ２〜ＣＰＵｎはそれぞれ前段
のＣＰＵ１〜ＣＰＵｎ−１からのリトリガ要求が入力す
ると後段のＣＰＵ３〜ＣＰＵｎ，ＷＤＴ回路に順次リト
リガ要求を出力し、前段からのリトリガ要求が入力され
ないときは後段へのリトリガ要求出力を行わないように
する。しかして最後段ＣＰＵｎからのリトリガ要求出力
はＷＤＴ回路７のリトリガ信号となる。In FIG. 1, 1 to 3 and n are a plurality of CPUs connected in series, and 7 is a WDT circuit connected to the last-stage CPU n. The CPU 1 makes a retrigger request to the CPU 2 at regular intervals. When the retrigger request from the preceding stage CPU1 to CPUn-1 is input, the CPU2 to CPUn sequentially output the retrigger request to the subsequent stage CPU3 to CPUn and the WDT circuit. When the retrigger request from the preceding stage is not input, the retrigger request to the subsequent stage. Turn off output. Then, the retrigger request output from the last-stage CPUn becomes the retrigger signal of the WDT circuit 7.

【００１２】ＷＤＴ回路７の出力側は各ＣＰＵ１〜ＣＰ
Ｕｎに接続されており、ＣＰＵｎからリトリガ信号が一
定時間以内の間隔で入力されている間は何も出力せず、
一定時間以上リトリガ信号が途絶するとリセット信号を
各ＣＰＵ１〜ＣＰＵｎに出力し、全ＣＰＵにリセットを
かけて暴走したＣＰＵを復帰させるようになっている。The output side of the WDT circuit 7 is each CPU 1 to CP.
It is connected to Un and outputs nothing while the retrigger signal is input from the CPUn at intervals within a fixed time.
When the retrigger signal is interrupted for a certain period of time or more, a reset signal is output to each of the CPU1 to CPUn to reset all CPUs to recover the runaway CPU.

【００１３】このため、各ＣＰＵ１〜ＣＰＵｎが正常に
動作しているときは、ＣＰＵ１から出力されるリトリガ
要求が順次後段のＣＰＵへ受け渡され、ＷＤＴ回路７の
リトリガを行うのでＷＤＴ回路からは何も出力されな
い。Therefore, when each of the CPUs 1 to CPUn is operating normally, the retrigger request output from the CPU 1 is sequentially passed to the subsequent CPU, and the WDT circuit 7 is retriggered. Is not output.

【００１４】しかし、ＣＰＵ１〜ＣＰＵｎのうちの何れ
か１つでもＣＰＵが暴走すると、暴走したＣＰＵより後
段のＣＰＵへはリトリガ要求が出力されなくなり、最終
ＣＰＵｎからＷＤＴ回路７へリトリガ要求が出力されな
くなるのでＷＤＴ回路７から全ＣＰＵに対しリセット信
号が出力され、暴走したＣＰＵは復帰する。However, if any one of the CPU1 to CPUn runs out of control, the retrigger request is not output to the CPU subsequent to the runaway CPU, and the retrigger request is not output from the final CPUn to the WDT circuit 7. Therefore, a reset signal is output from the WDT circuit 7 to all CPUs, and the runaway CPU is restored.

【００１５】次に、一部のＣＰＵを並列に接続した実施
例を図２に示す。この実施例はＣＰＵ１及びＣＰＵ３に
それぞれＣＰＵ２およびＣＰＵ４を並列に接続した例を
示すもので、並列のＣＰＵ１，ＣＰＵ２及びＣＰＵ３，
ＣＰＵ４からリトリガ要求を受ける後段のＣＰＵ３及び
ＣＰＵ５はそれぞれ並列のＣＰＵからの全てのリトリガ
要求を受け取った後後段ＣＰＵ５及びＣＰＵ６へのリト
リガ要求を出力し、並列接続された一方のＣＰＵのみが
暴走してもその後段ＣＰＵからリトリガ要求が出力しな
いようになっている。FIG. 2 shows an embodiment in which some CPUs are connected in parallel. This embodiment shows an example in which a CPU 2 and a CPU 4 are connected in parallel to a CPU 1 and a CPU 3, respectively.
After receiving all the retrigger requests from the parallel CPUs, the post-stage CPUs 3 and 5 receiving the retrigger request from the CPU 4 output the retrigger requests to the post-stage CPUs 5 and 6 respectively, and only one CPU connected in parallel runs out of control. Also, the retrigger request is not output from the subsequent CPU.

【００１６】この場合も何れかのＣＰＵが暴走すると最
後段ＣＰＵｎからＷＤＴ回路７にリトリガ要求が出力さ
れなくなり、ＷＤＴ回路から全ＣＰＵにリセットがかか
るので、暴走したＣＰＵは復帰する。In this case as well, if any CPU goes out of control, the retrigger request is not output from the last-stage CPU n to the WDT circuit 7, and all the CPUs are reset from the WDT circuit.

【００１７】[0017]

【発明の効果】本発明は、上述のとおり構成されている
ので、次に記載する効果を奏する。Since the present invention is configured as described above, it has the following effects.

【００１８】（１）１つのウオッチドッグタイマ回路を
用いて複数のＣＰＵの暴走監視を行うことができる。(1) It is possible to monitor runaway of a plurality of CPUs using one watchdog timer circuit.

【００１９】（２）本発明方法によれば構成が簡単で安
価にして信頼性のあるＣＰＵ回路の暴走監視装置を得る
ことができる。(2) According to the method of the present invention, it is possible to obtain a reliable runaway monitoring device for a CPU circuit which has a simple structure and is inexpensive.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明を実施するＣＰＵ回路の暴走監視装置を
示すブロック回路図。FIG. 1 is a block circuit diagram showing a runaway monitoring device for a CPU circuit embodying the present invention.

【図２】本発明の他の方法を実施するＣＰＵ回路の暴走
監視装置を示すブロック回路図。FIG. 2 is a block circuit diagram showing a runaway monitoring device for a CPU circuit that implements another method of the present invention.

【図３】従来ＣＰＵ回路の暴走監視装置を示すブロック
回路図。FIG. 3 is a block circuit diagram showing a runaway monitoring device for a conventional CPU circuit.

【符号の説明】[Explanation of symbols]

１〜５，ｎ…ＣＰＵ、７，８…ウオッチドッグタイマ
（ＷＤＴ）回路。1 to 5, n ... CPU, 7, 8 ... Watchdog timer (WDT) circuit.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 複数のＣＰＵを直列に接続すると共に、
その最後段のＣＰＵにウオッチドッグタイマ回路を接続
し、最前段のＣＰＵから一定周期でその後段のＣＰＵに
リトリガ要求を出力し、そのリトリガ要求が入力するＣ
ＰＵから最後段の各ＣＰＵではそれぞれその前段からの
リトリガ要求の入力によりその後段のＣＰＵへ順次リト
リガ要求を出力し、ウオッチドッグタイマ回路は最終段
のＣＰＵからのリトリガ要求が途絶えると全ＣＰＵにリ
セット信号を出力することを特徴としたＣＰＵ回路の暴
走監視方法。1. A plurality of CPUs are connected in series, and
A watchdog timer circuit is connected to the CPU in the last stage, the CPU in the front stage outputs a retrigger request to the CPU in the subsequent stage at a constant cycle, and the retrigger request is input.
Each CPU in the last stage from the PU outputs the retrigger request to the CPU in the subsequent stage in response to the input of the retrigger request from the preceding stage, and the watchdog timer circuit is reset to all CPUs when the retrigger request from the CPU in the last stage is cut off. A runaway monitoring method for a CPU circuit, which is characterized by outputting a signal. 【請求項２】 直列に接続したＣＰＵの一部を並列に接
続し、この並列のＣＰＵからのそれぞれのリトリガ要求
を後段のＣＰＵに出力し、その後段のＣＰＵはその全て
のリトリガ要求が入力されたことを条件に後段ＣＰＵへ
リトリガ要求を出力することを特徴とした請求項１に記
のＣＰＵ回路の暴走監視方法。2. A part of CPUs connected in series is connected in parallel, and each retrigger request from the CPUs in parallel is output to a subsequent CPU, and all subsequent retrigger requests are input to the subsequent CPUs. The runaway monitoring method for a CPU circuit according to claim 1, wherein a retrigger request is output to the subsequent-stage CPU on the condition.
JP3169641A 1991-07-10 1991-07-10 Method for monitoring runaway of cpu circuit Pending JPH0520289A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3169641A JPH0520289A (en) 1991-07-10 1991-07-10 Method for monitoring runaway of cpu circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3169641A JPH0520289A (en) 1991-07-10 1991-07-10 Method for monitoring runaway of cpu circuit

Publications (1)

Publication Number Publication Date
JPH0520289A true JPH0520289A (en) 1993-01-29

Family

ID=15890257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3169641A Pending JPH0520289A (en) 1991-07-10 1991-07-10 Method for monitoring runaway of cpu circuit

Country Status (1)

Country Link
JP (1) JPH0520289A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3542443A1 (en) * 1984-05-30 1987-06-11 Taga Electric Co Ltd ACTIVATION DEVICE FOR A RECTANGULAR PLATE RESONATOR

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3542443A1 (en) * 1984-05-30 1987-06-11 Taga Electric Co Ltd ACTIVATION DEVICE FOR A RECTANGULAR PLATE RESONATOR

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