JPH05190085A - Manufacture of plasma display panel - Google Patents
Manufacture of plasma display panelInfo
- Publication number
- JPH05190085A JPH05190085A JP414592A JP414592A JPH05190085A JP H05190085 A JPH05190085 A JP H05190085A JP 414592 A JP414592 A JP 414592A JP 414592 A JP414592 A JP 414592A JP H05190085 A JPH05190085 A JP H05190085A
- Authority
- JP
- Japan
- Prior art keywords
- address
- electrodes
- address electrode
- display
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Gas-Filled Discharge Tubes (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、プラズマディスプレイ
パネルの製造方法に係り、特に電極を厚膜印刷法で形成
する製造方法の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a plasma display panel, and more particularly to improvement of a method of forming electrodes by a thick film printing method.
【０００２】コンピュータが多用されることにより、コ
ンピュータによる計算結果の表示やＣＡＤ、ＣＧなどの
図形表示、ワードプロセッサによる文章作成、情報照会
などにディスプレイも頻繁に使用されるようになった。Due to the frequent use of computers, displays have come to be frequently used for displaying calculation results by computers, displaying graphics such as CAD and CG, creating sentences by word processors, and inquiring information.
【０００３】このディスプレイの使用に伴いディスプレ
イの小型化が進み、より薄く、かつ鮮明で安定した表示
が可能なディスプレイが要求されている。このため、今
日では、薄型ディスプレイパネルが製造可能な液晶ディ
スプレイやプラズマディスプレイが使用されているが、
画像を鮮明で安定に表示可能にすることが今後の課題と
なっている。With the use of this display, miniaturization of the display has progressed, and there is a demand for a display that is thinner, clear, and capable of stable display. For this reason, liquid crystal displays and plasma displays that can be used to manufacture thin display panels are used today.
A future issue is to be able to display images clearly and stably.
【０００４】[0004]
【従来の技術】プラズマディスプレイパネル（ＰＤＰ）
には、例えば特開昭59-79938，同61-39341などに示され
た三電極面放電形ＰＤＰがある。2. Description of the Related Art Plasma display panel (PDP)
Is a three-electrode surface discharge PDP disclosed in, for example, Japanese Patent Laid-Open Nos. 59-79938 and 61-39341.
【０００５】この三電極面放電形ＰＤＰは、表示用放電
を行うための維持電極対を有する基板とアドレス用放電
（消去放電ともいう）を発生させるためのアドレス電極
を有する基板とをガス放電空間を挟んで対向配置して構
成される。This three-electrode surface discharge PDP includes a substrate having a sustain electrode pair for performing a display discharge and a substrate having an address electrode for generating an address discharge (also referred to as an erase discharge) in a gas discharge space. It is configured to be opposed to each other with the pinch in between.
【０００６】図３はその表示面側の基板３に設けたアド
レス電極の配列形態を示し、この図ではカラー表示のた
めに３本のアドレス電極を１セットにして１絵素（ドッ
ト）を構成するとともに、５×７ドットの表示を得るた
めに５セットずつで群をなして１表示行を構成してい
る。FIG. 3 shows an arrangement form of address electrodes provided on the substrate 3 on the display surface side. In this figure, one set of three address electrodes constitutes one picture element (dot) for color display. In addition, in order to obtain a display of 5 × 7 dots, a group of 5 sets is formed to form one display line.
【０００７】各セットのアドレス電極群１１、１２は電
極３本相当のスペースを隔てて配列され、かつ各アドレ
ス電極セットの一端からは、リード端子４が導出され、
そのリード端子４はアドレス電極に電圧をかけるための
ドライバに接続される。The address electrode groups 11 and 12 of each set are arranged with a space corresponding to three electrodes, and the lead terminal 4 is led out from one end of each address electrode set.
The lead terminal 4 is connected to a driver for applying a voltage to the address electrode.
【０００８】前記アドレス電極は、例えば厚膜銀ペース
トを基板３上の所定領域に印刷した後、該厚膜銀ペース
トを所定温度で焼成することにより基板３に融着して形
成されるが、基板３の端部とアドレス電極群１１間、ア
ドレス電極群１１とアドレス電極群１２間のように電極
が存在しない領域が余りに広いと、その厚膜銀ペースト
の焼成時に表示領域を構成するアドレス電極群１１、１
２のそれぞれの両端部分のアドレス電極と中央部分のア
ドレス電極の焼成が均一に行われないため、それら両端
部分のアドレス電極の表面部分に、酸化物層が厚く形成
されるということがあった。The address electrodes are formed by, for example, printing a thick film silver paste on a predetermined area on the substrate 3 and then fusing the thick film silver paste at a predetermined temperature to fuse the substrate 3 with the paste. If the regions where no electrodes are present are too wide, such as between the end portion of the substrate 3 and the address electrode group 11 and between the address electrode group 11 and the address electrode group 12, the address electrodes that form the display area when the thick silver paste is fired are formed. Groups 11, 1
Since the address electrodes at both end portions and the address electrode at the central portion of No. 2 are not uniformly fired, a thick oxide layer may be formed on the surface portions of the address electrodes at both end portions.
【０００９】[0009]
【発明が解決しようとする課題】従って、上記したよう
に、焼成状態の不均一化により表示領域を構成するアド
レス電極群の両端部分と中央部分のアドレス電極での電
気特性の差が大きくなり、ディスプレイパネル全面で安
定にかつ均一に動作出来る電圧範囲が狭くなり、しかも
アドレス電極に電圧をかけても本来アドレスのための消
去放電を発生しなければならないセルに、その消去放電
が確実に行われず余剰点灯、従って誤表示を引き起こす
という問題を生じていた。Therefore, as described above, the difference in the electrical characteristics between the address electrodes at both ends and the center of the address electrode group forming the display region becomes large due to the non-uniform firing state. The voltage range that allows stable and uniform operation on the entire display panel becomes narrower, and even if a voltage is applied to the address electrode, the erase discharge for the address should originally be generated, but the erase discharge is not reliably performed. There has been a problem of excessive lighting, and thus causing an erroneous display.
【００１０】本発明は、このような従来の状況から、ア
ドレス電極群を基板に融着するための焼成時において、
その焼成状態を良好にし、該アドレス電極群の電気特性
の不均一性を解消したプラズマディスプレイパネルの製
造方法を提供することを目的とする。In view of the conventional situation as described above, the present invention provides a method for fusing the address electrode group to the substrate at the time of firing.
An object of the present invention is to provide a method for manufacturing a plasma display panel in which the firing state is improved and the nonuniformity of the electric characteristics of the address electrode group is eliminated.
【００１１】[0011]
【課題を解決するための手段】図１は本発明の原理図で
ある。図中、１は前述したアドレス電極群であり、プラ
ズマディスプレイパネルを構成する一方の基板３上の表
示領域のみに厚膜印刷法で形成されるものである。FIG. 1 shows the principle of the present invention. In the figure, reference numeral 1 denotes the above-mentioned address electrode group, which is formed by a thick film printing method only on the display region on one of the substrates 3 constituting the plasma display panel.
【００１２】２はダミー電極であり、アドレス電極と実
質的に同一形状を持ち、かつアドレス電極群１の外側領
域、つまりプラズマディスプレイパネルの表示領域外に
厚膜印刷法でアドレス電極群１と同時に形成されるもの
である。Reference numeral 2 denotes a dummy electrode, which has substantially the same shape as the address electrode, and is formed outside the address electrode group 1, that is, outside the display area of the plasma display panel at the same time as the address electrode group 1 by a thick film printing method. It is what is formed.
【００１３】[0013]
【作用】本発明では、図１のようにアドレス電極群１の
両側にアドレス電極と実質的に同一形状のダミー電極２
を同時に形成している。In the present invention, the dummy electrodes 2 having substantially the same shape as the address electrodes are formed on both sides of the address electrode group 1 as shown in FIG.
Are formed at the same time.
【００１４】従って、アドレス電極を形成するための厚
膜銀ペーストの焼成時において、焼成状態が不良となる
領域がアドレス電極群１の外側のいわゆる表示領域外の
表示に使用しないダミー電極２の部分となり、表示に使
用するアドレス電極は良好な焼成状態を得られるため、
表示領域のアドレス電極の電気特性を均一化することが
可能となる。Therefore, when the thick film silver paste for forming the address electrodes is fired, the region where the firing state is defective is the portion of the dummy electrode 2 which is outside the so-called display region outside the address electrode group 1 and which is not used for display. Since the address electrode used for display can obtain a good firing state,
It is possible to make the electrical characteristics of the address electrodes in the display area uniform.
【００１５】[0015]
【実施例】以下、図面を用いて実施例を詳細に説明す
る。図２は、本発明の実施例を示す図である。Embodiments will be described in detail below with reference to the drawings. FIG. 2 is a diagram showing an embodiment of the present invention.
【００１６】図２は三電極面放電形ＰＤＰを形成する表
示面側の基板の一部分を示すものであり、基板３にアド
レス電極群１１および１２とダミー電極２１および２２
が厚膜印刷で同時に形成されている。FIG. 2 shows a part of the substrate on the display surface side forming the three-electrode surface discharge PDP. Address electrodes 11 and 12 and dummy electrodes 21 and 22 are provided on the substrate 3.
Are simultaneously formed by thick film printing.
【００１７】本実施例では、図２に示すように、従来例
同様３本のアドレス電極を１セットとし、５セットでア
ドレス電極群１１および１２を構成しており、各アドレ
ス電極群を所定間隔で配置し、各アドレス電極のセット
にはリード端子４が接続し、該リード端子４はドライバ
に配線している。In the present embodiment, as shown in FIG. 2, the address electrode groups 11 and 12 are composed of 5 sets, each of which has 3 address electrodes as one set, as in the conventional example. The lead terminal 4 is connected to each address electrode set, and the lead terminal 4 is wired to the driver.
【００１８】また、基板３の端部とアドレス電極群１
１、アドレス電極群１１と１２の間には、それぞれ３本
ずつのダミー電極群２１と２２が設けられており、その
各ダミー電極は各アドレス電極と同様な形状で、かつア
ドレス電極と同じ間隔で形成されている。Further, the end portion of the substrate 3 and the address electrode group 1
1, three dummy electrode groups 21 and 22 are provided between the address electrode groups 11 and 12, and each dummy electrode has the same shape as each address electrode and has the same spacing as the address electrode. Is formed by.
【００１９】なお、これらダミー電極群２１、２２はリ
ード端子４が設けられておらず、ドライバにも接続され
ていない。更に、アドレス電極群１１、１２とダミー電
極群２１、２２は、それぞれ各電極のセット間の間隔と
同じ間隔で配置している。The dummy electrode groups 21 and 22 are not provided with the lead terminal 4 and are not connected to the driver. Further, the address electrode groups 11 and 12 and the dummy electrode groups 21 and 22 are arranged at the same intervals as the intervals between the respective sets of electrodes.
【００２０】このように本実施例では、アドレス電極群
の両側にダミー電極群を該アドレス電極群とともに厚膜
印刷法で形成するので、焼成工程時において各アドレス
電極群のうちの外側の電極も内側（中央部分）の電極と
同じ状態で焼成が行われる。As described above, in this embodiment, since the dummy electrode groups are formed on both sides of the address electrode group together with the address electrode group by the thick film printing method, the outer electrodes of each address electrode group are also formed during the firing process. The firing is performed in the same state as the inner (central portion) electrode.
【００２１】この実施例の場合、基板端部に近いダミー
電極では焼成不良状態が発生し易いけれども、この電極
は表示には無関係であるため表示品質向上何ら問題な
い。なお、上記実施例では複数のアドレス電極群のあい
だに非表示のスペース領域を設けた部分的表示のパネル
構成を示したが、本発明はこれに限らず例えばパネル全
面が１つの表示領域となる構成のパネルにも適用可能で
あり、その場合基板の端部に近いアドレス電極の外側に
ダミー電極を配置すればよい。In the case of this embodiment, the dummy electrode near the edge of the substrate is likely to be in a defective firing state, but since this electrode is irrelevant to the display, there is no problem in improving the display quality. In the above embodiment, the panel structure of partial display in which the non-display space region is provided between the plurality of address electrode groups has been shown, but the present invention is not limited to this, and the entire panel becomes one display region, for example. It can also be applied to a panel having a structure, in which case the dummy electrode may be arranged outside the address electrode near the edge of the substrate.
【００２２】また、各電極間の間隔を等間隔にするよう
にも上記したが、必ずしも等間隔でなくてもよい。Further, although it has been described that the intervals between the electrodes are equal, the intervals are not necessarily equal.
【００２３】[0023]
【発明の効果】以上説明したように、本発明によれば、
三電極面放電形プラズマディスプレイパネルの厚膜印刷
法によるアドレス電極群を均一に焼成することが出来、
それによって表示領域内のアドレス電極群の電気特性の
均一化が可能となり、更に該ディスプレイパネルの動作
電圧の電圧範囲が広くなるため、ディスプレイパネル全
面での安定した表示およびそのディスプレイパネルの性
能向上に寄与するところが大きい。As described above, according to the present invention,
The address electrode group can be uniformly fired by the thick film printing method of the three-electrode surface discharge type plasma display panel,
As a result, the electric characteristics of the address electrode group in the display area can be made uniform, and the voltage range of the operating voltage of the display panel is widened, so that stable display on the entire display panel and improvement of the performance of the display panel can be achieved. There is a great contribution.
【図１】本発明の原理図である。FIG. 1 is a principle diagram of the present invention.
【図２】本発明の実施例を示す図である。FIG. 2 is a diagram showing an example of the present invention.
【図３】従来例を示す図である。FIG. 3 is a diagram showing a conventional example.
１、１１、１２ アドレス電極群 ２ ダミー電極 ３ 基板 ４ リード端子 ２１、２２ ダミー電極群 1, 11, 12 Address electrode group 2 Dummy electrode 3 Substrate 4 Lead terminal 21, 22 Dummy electrode group
Claims (1)
極対と、これら電極対と交差する方向に配列された複数
のアドレス電極（１）とを有するプラズマディスプレイ
パネルの製造方法において、 前記複数のアドレス電極（１）を厚膜印刷法により形成
する際、群単位のアドレス電極の外側領域に当該アドレ
ス電極と実質的に同一形状のダミー電極（２）を同時に
形成することを特徴とするプラズマディスプレイパネル
の製造方法。1. A method of manufacturing a plasma display panel, comprising: a plurality of sustain electrode pairs, each pair being adjacent to each other; and a plurality of address electrodes (1) arranged in a direction intersecting with the electrode pairs. When the address electrodes (1) of (1) are formed by a thick film printing method, a dummy electrode (2) having substantially the same shape as the address electrodes is simultaneously formed in an area outside the group-wise address electrodes. Display panel manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP414592A JP2751704B2 (en) | 1992-01-13 | 1992-01-13 | Method for manufacturing plasma display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP414592A JP2751704B2 (en) | 1992-01-13 | 1992-01-13 | Method for manufacturing plasma display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05190085A true JPH05190085A (en) | 1993-07-30 |
| JP2751704B2 JP2751704B2 (en) | 1998-05-18 |
Family
ID=11576613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP414592A Expired - Fee Related JP2751704B2 (en) | 1992-01-13 | 1992-01-13 | Method for manufacturing plasma display panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2751704B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100235483B1 (en) * | 1995-09-28 | 1999-12-15 | 김영남 | Functional layer array of flat panel device |
| KR100488449B1 (en) * | 2002-09-12 | 2005-05-11 | 엘지전자 주식회사 | Plasma display panel |
| KR100496283B1 (en) * | 2000-04-28 | 2005-06-17 | 삼성에스디아이 주식회사 | Plasma display panel |
-
1992
- 1992-01-13 JP JP414592A patent/JP2751704B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100235483B1 (en) * | 1995-09-28 | 1999-12-15 | 김영남 | Functional layer array of flat panel device |
| KR100496283B1 (en) * | 2000-04-28 | 2005-06-17 | 삼성에스디아이 주식회사 | Plasma display panel |
| KR100488449B1 (en) * | 2002-09-12 | 2005-05-11 | 엘지전자 주식회사 | Plasma display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2751704B2 (en) | 1998-05-18 |
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