JPH05166984A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05166984A JPH05166984A JP3331687A JP33168791A JPH05166984A JP H05166984 A JPH05166984 A JP H05166984A JP 3331687 A JP3331687 A JP 3331687A JP 33168791 A JP33168791 A JP 33168791A JP H05166984 A JPH05166984 A JP H05166984A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- electrode
- pellet
- resistance
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置、特に樹脂封
止形パワーＭＯＳＦＥＴの電極取り出し構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an electrode lead-out structure for a resin-sealed power MOSFET.
【０００２】[0002]
【従来の技術】樹脂封止形のトランジスタ、例えばパワ
ーＭＯＳＦＥＴ（絶縁ゲート電界効果トランジスタ）
は、図１、図２に示すように金属ヘッダ・（ステム）１
の上に半導体素子（ペレット）２を取り付け、ヘッダに
直結する真中の１本のリード３をドレイン取り出し用と
し、素子の他の２つの電極から金（またはアルミニウ
ム）ワイヤ４を介して接続した２つのリードをソース取
り出し用リード５およびゲート取り出し用リードとし、
ステムの上面または全面で素子とリードのワイヤ接続
（ボンディング）部分を包囲して樹脂成形体７で封止し
た構造を有する。2. Description of the Related Art A resin-sealed transistor, such as a power MOSFET (insulated gate field effect transistor)
Is a metal header (stem) 1 as shown in FIGS.
A semiconductor element (pellet) 2 was attached on the top of the device, one lead 3 in the center directly connected to the header was used for drain extraction, and the other two electrodes of the element were connected via a gold (or aluminum) wire 4 2 The two leads are the source lead 5 and the gate lead,
It has a structure in which the wire connection (bonding) portion of the element and the lead is surrounded by the upper surface or the entire surface of the stem and sealed by the resin molded body 7.
【０００３】近年、パワーＭＯＳＦＥＴ等の特性の向上
（低オン抵抗化）への顧客の要求がますます強くなって
おり、これに伴ってデバイス（半導体素子）の低オン抵
抗化の技術開発が進み、現在では数ｍΩのオン抵抗の素
子も開発されつつある。しかしながら、従来から半導体
素子の電極とステムのリードとの接続（ワイヤボンディ
ング）に使用されている金（またはアルミニウム）ワイ
ヤは、ワイヤ自身の持つワイヤ抵抗が数１０ｍΩと高
く、このワイヤ自身の持つ抵抗のために、さらに進むと
推定される低オン抵抗化のネックとなると考えられる。In recent years, customers' demands for improving the characteristics of power MOSFETs (reduction of on-resistance) have become stronger and stronger, and along with this, technological development for lowering on-resistance of devices (semiconductor elements) has progressed. At present, an element having an on-resistance of several mΩ is being developed. However, the gold (or aluminum) wire conventionally used for connection (wire bonding) between the electrode of the semiconductor element and the lead of the stem has a high wire resistance of several tens of mΩ and the resistance of the wire itself. Therefore, it is considered that it will become a bottleneck for lowering the on-resistance which is estimated to progress further.
【０００４】ワイヤ部分での抵抗の軽減手段として、
（１）ワイヤを太くすること、（２）ワイヤの長さを短
くすること、（３）ワイヤを複数本重ねて使用すること
等が考えられ、一部では採用されているが次の問題があ
る。（１）のワイヤをある太さ以上にすることはボンデ
ィング装置及び技術に制約を生じる。（２）はリードの
ボンディング・ポストの位置がペレットに接近するよう
にリードを形成する必要があり、設計上にかなり無理が
ある。（３）ワイヤを多重に使用することはある程度ま
でしか効果はなく、ボンディングシステムにも問題があ
る。As a means for reducing the resistance at the wire portion,
(1) Making the wire thicker, (2) shortening the wire length, (3) stacking multiple wires, etc. can be considered. is there. Making the wire of (1) more than a certain thickness limits the bonding apparatus and technology. In the case of (2), it is necessary to form the lead so that the position of the bonding post of the lead approaches the pellet, which is quite unreasonable in design. (3) The use of multiple wires is effective only to some extent, and there is a problem in the bonding system.
【０００５】バイポーラ・トランジスタではリードを延
長させ、その先端を曲げて直接に半田電極に接触させる
手段がコネクタ方式として本出願人により開発されてい
る。この場合は軟かく厚い半田電極構造であることによ
り、リードとの接続が比較的容易に実現できたが、ＭＯ
ＳＦＥＴでは電極部分がうすい金属膜であるために上記
の方式をそのまま採用することには困難があった。In the bipolar transistor, a means for extending a lead and bending the tip of the lead to directly contact the solder electrode has been developed by the applicant as a connector system. In this case, because of the soft and thick solder electrode structure, connection with the lead could be realized relatively easily.
Since the electrode portion of the SFET is a thin metal film, it is difficult to directly adopt the above method.
【０００６】[0006]
【発明が解決しようとする課題】解決しようとする問題
点は、パワーＭＯＳＦＥＴにおいて低オン抵抗化を実現
できる電極構造をうることである。A problem to be solved is to obtain an electrode structure capable of realizing low on-resistance in a power MOSFET.
【０００７】[0007]
【課題を解決するための手段】本発明は半導体素子電極
とリードとの接続を従来のワイヤ方式から、少なくとも
１本のリードを電極位置に延長して少なくとも一部の先
端を電極に直接に接続することを特徴とする。これによ
り、ワイヤの抵抗分を主とする電極部分の抵抗分を低減
し、半導体素子のもつ低オン抵抗特性を引き出すことが
できる。According to the present invention, at least one lead is extended to the electrode position and at least a part of the tip is directly connected to the electrode, unlike the conventional wire system for connecting the semiconductor element electrode and the lead. It is characterized by doing. As a result, the resistance of the electrode portion, which is mainly the resistance of the wire, can be reduced, and the low on-resistance characteristic of the semiconductor element can be brought out.
【０００８】本発明は前記半導体装置をＭＯＳＦＥＴと
し、素子の電極表面には、半田との付着性のよい金属膜
を形成し、少なくともソース電極に対してリード端を半
田を介して接続するものであり、ソースを通じて低オン
抵抗特性を有効に引き出すことができる。According to the present invention, the semiconductor device is a MOSFET, a metal film having good adhesion to solder is formed on the electrode surface of the element, and at least the lead end is connected to the source electrode via solder. The low on-resistance characteristic can be effectively brought out through the source.
【０００９】[0009]
【実施例】図３は本発明の半導体装置の一実施例の平面
図、図４は同正面図である。１は金属ヘッダ、２は半導
体素子（ペレット）、３はドレイン取り出し用リードで
ヘッダにかしめ等により一体的に連結してある。８はソ
ース取り出し用リードでボンディング・ポストとなる部
分をペレット側に延長し、先端をペレットの表面電極
（ソース）に接触するまでに曲げてある。なお、ペレッ
トの表面電極は、従来のＡｌ（アルミニウム）膜電極の
かわりにＴｉ（チタン）−Ｎｉ（ニッケル）−Ａｇ
（銀）等からなる積層金属薄膜１０を形成する。これら
金属は相互に付属性がよい材質であり、とくに表面のＡ
ｇは半田（Ｐｂ−Ｓｎ）との接着性が良い。FIG. 3 is a plan view of an embodiment of the semiconductor device of the present invention, and FIG. 4 is a front view of the same. Reference numeral 1 is a metal header, 2 is a semiconductor element (pellet), and 3 is a drain extraction lead, which is integrally connected to the header by caulking or the like. Reference numeral 8 denotes a source extraction lead, which extends a portion serving as a bonding post to the pellet side and is bent until the tip comes into contact with the surface electrode (source) of the pellet. The surface electrode of the pellet is Ti (titanium) -Ni (nickel) -Ag instead of the conventional Al (aluminum) film electrode.
A laminated metal thin film 10 made of (silver) or the like is formed. These metals are materials that have good attachment to each other, especially on the surface A
g has good adhesiveness with solder (Pb-Sn).
【００１０】ペレットの表面電極とリードとの接続に先
立って、裏面に半田等の接着剤（ペースト状）を塗布し
たペレットを金属ヘッダ１上に搭載し、ソース取り出し
リード８の延長部先端と電極１０との位置合わせを行な
う。この接触部分（リード、電極表面）に電気的導通を
うるため接着剤として例えば半田ペースト１１を塗布
し、その後リフロー炉を通すことにより、ヘッダへのペ
レット付けおよびソース・リードとのボンディングが完
了する。この実施例では他の一方の表面電極とゲート取
り出しリード６との間はワイヤボンディングによって電
気的に接続を行う。Prior to the connection between the surface electrode of the pellet and the lead, the pellet having the back surface coated with an adhesive (paste) such as solder is mounted on the metal header 1 and the tip of the extension of the source lead 8 and the electrode. Align with 10. In order to obtain electrical continuity to this contact portion (lead, electrode surface), for example, solder paste 11 is applied as an adhesive and then passed through a reflow oven to complete pelleting to the header and bonding to the source lead. . In this embodiment, the other surface electrode and the gate lead 6 are electrically connected by wire bonding.
【００１１】図５は本発明の半導体装置の他の一実施例
の平面図である。この例ではゲート取り出しリード９と
同じくソース取り出しリード８と同じくボンディング・
ポストとなる部分を延長し、先端を曲げてペレットの表
面電極に接触させ、半田等を用いて直接に接続するもの
である。この場合はワイヤボンディング工程が不要であ
り、工程が簡易化する。図６はリード先端とペレット表
面の積層電極１０とを半田等の接着剤１１により、直接
に接着した状態を示す一部拡大正面図である。FIG. 5 is a plan view of another embodiment of the semiconductor device of the present invention. In this example, like the gate extraction lead 9, the source extraction lead 8 and the bonding
The post is extended, the tip is bent and brought into contact with the surface electrode of the pellet, and is directly connected using solder or the like. In this case, the wire bonding process is unnecessary and the process is simplified. FIG. 6 is a partially enlarged front view showing a state in which the tip of the lead and the laminated electrode 10 on the surface of the pellet are directly bonded by an adhesive 11 such as solder.
【００１２】[0012]
【発明の効果】本発明は、以上説明したように構成され
ているので、以下に記載されるような効果がある。従来
の金ワイヤ、アルミニウム・ワイヤ径により制限される
ワイヤ抵抗分が、リードのボンディング・ポストの延長
部分に代替されることにより、ワイヤ抵抗値が軽減さ
れ、低オン抵抗のデバイスが実現できる。特に少なくと
もソース取り出しリード側を直接にペレット表面電極に
接続することにより、オン抵抗のかかる主要部分が有効
に低抵抗化される。また、ソース用、ゲート用の両リー
ドを直接に接続する形式ではペレットボンディング作業
とリードボンディング作業とを同時に行なうから、プロ
セスを簡易化しコストの節減化に寄与する。Since the present invention is constructed as described above, it has the following effects. By replacing the conventional wire resistance, which is limited by the diameter of gold wire and aluminum wire, with the extension part of the bonding post of the lead, the wire resistance value is reduced, and a low on-resistance device can be realized. In particular, by directly connecting at least the source take-out lead side to the pellet surface electrode, the resistance of the main part where the ON resistance is applied can be effectively lowered. Further, in the type in which both the source and gate leads are directly connected, the pellet bonding work and the lead bonding work are performed at the same time, which simplifies the process and contributes to cost reduction.
【図面の簡単な説明】[Brief description of drawings]
【図１】従来の樹脂モールド半導体装置の平面図であ
る。FIG. 1 is a plan view of a conventional resin-molded semiconductor device.
【図２】従来の樹脂モールド半導体装置の正面図であ
る。FIG. 2 is a front view of a conventional resin-molded semiconductor device.
【図３】本発明の一実施例を示す半導体装置の平面図で
ある。FIG. 3 is a plan view of a semiconductor device showing an embodiment of the present invention.
【図４】本発明の一実施例を示す半導体装置の正面図で
ある。FIG. 4 is a front view of a semiconductor device showing an embodiment of the present invention.
【図５】本発明の他の一実施例を示す半導体装置の平面
図である。FIG. 5 is a plan view of a semiconductor device showing another embodiment of the present invention.
【図６】本発明の一実施例を示す半導体装置の一部拡大
正面図である。FIG. 6 is a partially enlarged front view of a semiconductor device showing an embodiment of the present invention.
１ 金属ヘッダ（ステム） ２ 半導体素子（ペレット） ３ ドレイン取り出し用リード ４ ボンディングワイヤ（金、アルミニウム） ５ ソース取り出し用リード ６ ゲート取り出し用リード ７ 樹脂成形体（パッケージ部材） ８ ボンディング・ポスト部を延長したソース取り出し
用リード ９ ボンディング・ポスト部を延長したゲート取り出し
用リード １０ 積層金属電極 １１ 半田1 metal header (stem) 2 semiconductor element (pellet) 3 lead for drain extraction 4 bonding wire (gold, aluminum) 5 lead for source extraction 6 lead for gate extraction 7 resin molding (package member) 8 extension of bonding post Leads for source extraction 9 Leads for gate extraction with extended bonding post 10 Laminated metal electrode 11 Solder
───────────────────────────────────────────────────── フロントページの続き (72)発明者 萩原 義美 群馬県高崎市西横手町111番地 株式会社 日立製作所高崎工場内 (72)発明者 石坂 勝男 群馬県高崎市西横手町111番地 株式会社 日立製作所高崎工場内 (72)発明者 天野 智章 埼玉県入間郡毛呂山町大字旭台15番地 日 立東部セミコンダクタ株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshimi Hagiwara, 111 Nishiyokote-cho, Takasaki-shi, Gunma Hitachi, Ltd. Takasaki factory (72) Inventor Katsuo Ishizaka 111 Nishiyote-cho, Takasaki, Gunma Hitachi, Ltd. Takasaki Plant (72) Inventor Tomoaki Amano 15 Asahidai, Moroyama Town, Iruma District, Saitama Prefecture
Claims (4)
属ヘッダと、ヘッダおよび素子の電極に電気的に接続さ
せた複数のリードと、これらを包囲して封止するパッケ
ージ部材とからなる半導体装置であって、少なくとも１
本のリードを素子の電極位置まで延長し、リード先端を
電極に対し直接に接続することを特徴とする半導体装
置。1. A semiconductor comprising a semiconductor element, a metal header to which a substrate of the element is attached, a plurality of leads electrically connected to electrodes of the header and the element, and a package member which surrounds and seals these leads. A device having at least one
A semiconductor device in which a lead of a book is extended to an electrode position of an element and a tip of the lead is directly connected to the electrode.
電極には半田との付着性のよい金属膜を形成し、リード
先端と半田を介して接続する。2. The semiconductor device according to claim 1, wherein a metal film having good adhesion to solder is formed on the electrode of the element, and the tip of the lead is connected via the solder.
あって、素子のドレイン電極はヘッダ基板に接続し、ゲ
ート電極はワイヤを介してリードに接続するとともに、
ソース電極は延長されたリード先端と直接に接続する。3. The semiconductor device according to claim 2, which is a MOSFET, wherein the drain electrode of the device is connected to the header substrate, and the gate electrode is connected to the lead via a wire.
The source electrode is directly connected to the extended lead tip.
であって、ドレイン電極はヘッダに接続するとともに、
ゲート電極とソース電極とはリードに直接に接続する。4. The semiconductor device according to claim 2 is a MOSFET.
And the drain electrode is connected to the header,
The gate electrode and the source electrode are directly connected to the lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3331687A JPH05166984A (en) | 1991-12-16 | 1991-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3331687A JPH05166984A (en) | 1991-12-16 | 1991-12-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05166984A true JPH05166984A (en) | 1993-07-02 |
Family
ID=18246461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3331687A Pending JPH05166984A (en) | 1991-12-16 | 1991-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05166984A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0731505A3 (en) * | 1995-03-06 | 1998-04-15 | Motorola, Inc. | Semiconductor leadframe structure and method of manufacturing the same |
| US5889658A (en) * | 1997-11-25 | 1999-03-30 | Motorola, Inc. | Package assembly for an electronic component |
| JP2007251218A (en) * | 2007-07-06 | 2007-09-27 | Renesas Technology Corp | Manufacturing method of power mosfet and power mosfet |
| JP2008177588A (en) * | 2008-02-12 | 2008-07-31 | Renesas Technology Corp | Semiconductor device |
| JP2011135115A (en) * | 2011-04-08 | 2011-07-07 | Renesas Electronics Corp | Semiconductor device |
| US8304890B2 (en) | 2003-06-30 | 2012-11-06 | Renesas Electronics Corporation | Semiconductor device |
| JP2014225643A (en) * | 2013-04-16 | 2014-12-04 | ローム株式会社 | Semiconductor device |
| JP2015019115A (en) * | 2014-10-28 | 2015-01-29 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP2016040839A (en) * | 2015-10-27 | 2016-03-24 | ルネサスエレクトロニクス株式会社 | Method of manufacturing semiconductor device |
| JP2019134160A (en) * | 2017-12-18 | 2019-08-08 | イクシス，エルエルシー | Thin power semiconductor device package with thin surface mount die and no internal bond wire |
-
1991
- 1991-12-16 JP JP3331687A patent/JPH05166984A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0731505A3 (en) * | 1995-03-06 | 1998-04-15 | Motorola, Inc. | Semiconductor leadframe structure and method of manufacturing the same |
| US5889658A (en) * | 1997-11-25 | 1999-03-30 | Motorola, Inc. | Package assembly for an electronic component |
| US9165901B2 (en) | 2003-06-30 | 2015-10-20 | Renesas Electronics Corporation | Semiconductor device |
| US8304890B2 (en) | 2003-06-30 | 2012-11-06 | Renesas Electronics Corporation | Semiconductor device |
| US8796838B2 (en) | 2003-06-30 | 2014-08-05 | Renesas Electronics Corporation | Semiconductor device |
| US9824996B2 (en) | 2003-06-30 | 2017-11-21 | Renesas Electronics Corporation | Semiconductor device having low on resistance |
| JP2007251218A (en) * | 2007-07-06 | 2007-09-27 | Renesas Technology Corp | Manufacturing method of power mosfet and power mosfet |
| JP2008177588A (en) * | 2008-02-12 | 2008-07-31 | Renesas Technology Corp | Semiconductor device |
| JP2011135115A (en) * | 2011-04-08 | 2011-07-07 | Renesas Electronics Corp | Semiconductor device |
| US9859182B2 (en) | 2013-04-16 | 2018-01-02 | Rohm Co., Ltd. | Semiconductor device |
| JP2014225643A (en) * | 2013-04-16 | 2014-12-04 | ローム株式会社 | Semiconductor device |
| US10312171B2 (en) | 2013-04-16 | 2019-06-04 | Rohm Co., Ltd. | Semiconductor device |
| JP2015019115A (en) * | 2014-10-28 | 2015-01-29 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP2016040839A (en) * | 2015-10-27 | 2016-03-24 | ルネサスエレクトロニクス株式会社 | Method of manufacturing semiconductor device |
| JP2019134160A (en) * | 2017-12-18 | 2019-08-08 | イクシス，エルエルシー | Thin power semiconductor device package with thin surface mount die and no internal bond wire |
| US11296017B2 (en) | 2017-12-18 | 2022-04-05 | Littelfuse, Inc. | Thin profile power semiconductor device package having face-to-face mounted dice and no internal bond wires |
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