JPH05129742A - Hybrid integrated circuit device and manufacture thereof - Google Patents
Hybrid integrated circuit device and manufacture thereofInfo
- Publication number
- JPH05129742A JPH05129742A JP3313586A JP31358691A JPH05129742A JP H05129742 A JPH05129742 A JP H05129742A JP 3313586 A JP3313586 A JP 3313586A JP 31358691 A JP31358691 A JP 31358691A JP H05129742 A JPH05129742 A JP H05129742A
- Authority
- JP
- Japan
- Prior art keywords
- metal substrate
- insulating
- insulating metal
- circuit pattern
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は混成集積回路装置および
その製造方法に関し、詳細には、気密封止のためのケー
ス材が不要な混成集積回路装置構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device and a method of manufacturing the same, and more particularly to a hybrid integrated circuit device structure which does not require a case material for hermetic sealing.
【０００２】[0002]
【従来の技術】図１１を参照すると、従来の混成集積回
路装置は絶縁金属基板(70)、この絶縁金属基板(70)上
に、絶縁層(76)を介して形成した各種パッド(78)、導電
路、所定のパッド(78)上に固着したパワー素子(80)、集
積回路素子(82)等の半導体素子、チップコンデンサ、あ
るいはチップ抵抗(86)、並びに外部リード(88)および搭
載素子を気密封止するケース材(90)等から構成される。2. Description of the Related Art Referring to FIG. 11, a conventional hybrid integrated circuit device includes an insulating metal substrate (70) and various pads (78) formed on the insulating metal substrate (70) via an insulating layer (76). , Conductive path, power element (80) fixed on a predetermined pad (78), semiconductor element such as integrated circuit element (82), chip capacitor or chip resistor (86), and external lead (88) and mounted element And a case member (90) for hermetically sealing.
【０００３】絶縁金属基板(70)には放熱特性および加工
性を考慮して略２ｍｍ厚のアルミニウム(72)が使用さ
れ、絶縁性の向上のためにその表面が陽極酸化処理（そ
の酸化膜を符号74で示す）される。この絶縁金属基板(7
0)は混成集積回路装置が略完成した時点で、数単位乃至
十数単位の混成集積回路装置基板から単位混成集積回路
装置のサイズに分割プレスされる。Aluminum (72) having a thickness of about 2 mm is used for the insulating metal substrate (70) in consideration of heat radiation characteristics and workability, and its surface is anodized (the oxide film is Indicated by reference numeral 74). This insulated metal substrate (7
In (0), when the hybrid integrated circuit device is substantially completed, several units to a dozen units of the hybrid integrated circuit device substrate are divided and pressed to the size of the unit hybrid integrated circuit device.
【０００４】各種パッド(78)および導電路は、ポリイミ
ド樹脂等の接着性を有する熱硬化性絶縁樹脂と略３５μ
ｍ厚の銅箔とのクラッド材を温度１５０℃〜１７０℃、
１平方センチメートル当り５０〜１００Ｋｇの圧力で絶
縁金属基板(70)にホットプレスした後、その銅箔をホト
エッチングする等して所定パターンに形成される。な
お、回路素子がワイアボンディングされるパッド(78)に
はニッケルメッキが施される。また、前記熱硬化性絶縁
樹脂はこのホットプレス工程で完全硬化して略３５μｍ
厚の絶縁層(76)となる。The various pads (78) and conductive paths are made of a thermosetting insulating resin such as polyimide resin having an adhesive property of approximately 35 μm.
m-thick copper foil with a clad material at a temperature of 150 ° C to 170 ° C,
The insulating metal substrate 70 is hot-pressed at a pressure of 50 to 100 kg per square centimeter, and then the copper foil is photo-etched to form a predetermined pattern. The pad (78) to which the circuit element is wire bonded is plated with nickel. In addition, the thermosetting insulating resin is completely cured in this hot pressing process to be about 35 μm.
It becomes a thick insulating layer (76).
【０００５】パワー回路素子(80)あるいは集積回路素子
(82)等の半導体素子およびその他の回路素子にはチップ
部品が使用される。パワー回路素子(80)はヒートシンク
(84)を介して所定のパッド(78)に半田固着され、集積回
路素子(82)は銀ペースト等により所定のパッド(78)に半
田固着される。また、チップコンデンサ、あるいはチッ
プ抵抗(86)、外部リード(88)等の異型部品は半田固着さ
れる。これら回路素子は所定のパッド(78)上にスクリー
ン印刷したソルダーペーストに一時的に付着させた後、
リフローして完全固着される。Power circuit element (80) or integrated circuit element
Chip components are used for semiconductor elements such as (82) and other circuit elements. Power circuit element (80) is a heat sink
The integrated circuit element (82) is soldered and fixed to the predetermined pad (78) through the (84), and the integrated circuit element (82) is soldered and fixed to the predetermined pad (78) with silver paste or the like. Further, the odd-shaped components such as the chip capacitor or the chip resistor (86) and the external lead (88) are fixed by soldering. After temporarily attaching these circuit elements to the solder paste screen-printed on the predetermined pad (78),
It reflows and is completely fixed.
【０００６】樹脂製のケース材(90)は、例えばエポキシ
含浸ポリエステル不繊布を接着シート（図示しない）と
して、加熱圧着して（１２５℃、８時間）絶縁金属基板
(70)の終辺部で固着され、搭載回路素子を気密封止す
る。外部リード(88)が固着されるこのケース材(90)の凹
部にはエポキシ樹脂が充填され、さらにこれを硬化（１
２５℃、２〜８時間）して、外部リード(88)の固着部の
機械的強度が向上される。The resin case material (90) is, for example, an epoxy-impregnated polyester non-woven cloth as an adhesive sheet (not shown), which is heat-pressed (125 ° C., 8 hours) to an insulating metal substrate.
It is fixed at the end of (70) and hermetically seals the mounted circuit element. The recess of the case material (90) to which the external lead (88) is fixed is filled with epoxy resin and is further cured (1
At 25 ° C. for 2 to 8 hours), the mechanical strength of the fixed portion of the outer lead (88) is improved.
【０００７】[0007]
【発明が解決しようとする課題】従来の混成集積回路装
置は、絶縁金属基板(70)上に搭載するチップ形状の半導
体素子を気密封止するためのケース材(90)が必要であ
り、さらには、このケース材(90)を絶縁金属基板(70)に
固着するために上記したように、高温度、長時間の熱処
理が必要である問題を有している。A conventional hybrid integrated circuit device requires a case material (90) for hermetically sealing a chip-shaped semiconductor element mounted on an insulating metal substrate (70). However, as described above, there is a problem that heat treatment at high temperature for a long time is required to fix the case material (90) to the insulating metal substrate (70).
【０００８】また、ケース材(90)の存在のため、表面実
装方式の混成集積回路装置には複雑な折曲形状の外部リ
ードを必要とする問題も有している。さらに、ケース材
(90)と搭載素子との間にマージンが必要であるため、混
成集積回路装置厚が大きくなる問題も有している。Further, due to the presence of the case material 90, there is a problem that the surface mount type hybrid integrated circuit device requires an external lead having a complicated bent shape. In addition, case material
Since a margin is required between (90) and the mounted element, there is also a problem that the thickness of the hybrid integrated circuit device becomes large.
【０００９】そこで、本発明の目的はケース材(90)が不
要な、従って、ケース材(90)の固着のための熱処理が不
要な混成集積回路装置構造およびその製造方法を提供す
ることにある。Therefore, an object of the present invention is to provide a hybrid integrated circuit device structure which does not require the case material (90), and therefore does not require heat treatment for fixing the case material (90), and a manufacturing method thereof. ..
【００１０】[0010]
【課題を解決するための手段】本発明は、絶縁金属基板
の回路パターン形成面の所定領域を、プレス加工して凹
部を形成し、この凹部に絶縁樹脂を充填して搭載回路素
子を埋設したことを主要な特徴とする。According to the present invention, a predetermined area of a circuit pattern forming surface of an insulating metal substrate is pressed to form a recess, and the recess is filled with an insulating resin to embed a mounted circuit element. That is the main feature.
【００１１】[0011]
【作用】絶縁金属基板に形成した凹部に回路素子を搭載
し、この凹部に絶縁樹脂を充填するため、回路素子を気
密封止するためのケース材が不要となり、従って、ケー
ス材を絶縁金属基板の周辺部に接着するための長時間の
熱処理工程が不要となる。Since the circuit element is mounted in the recess formed in the insulating metal substrate and the recess is filled with the insulating resin, a case material for hermetically sealing the circuit element is not required. There is no need for a long heat treatment step for bonding to the peripheral portion of the.
【００１２】また、プレス加工により絶縁金属基板に凹
部を形成するため、絶縁金属基板の基体、その酸化膜、
絶縁層、銅箔回路パターンからなる積層構造が破壊され
ない。さらにまた、外部リードの引き出し方向が制限さ
れないため表面実装方式に対応することが容易となる。Further, since the concave portion is formed in the insulating metal substrate by pressing, the substrate of the insulating metal substrate, its oxide film,
The laminated structure consisting of insulating layer and copper foil circuit pattern is not destroyed. Furthermore, since the pull-out direction of the external lead is not limited, it becomes easy to support the surface mounting method.
【００１３】[0013]
【実施例】図１乃至図７を参照して本発明の第１の実施
例を説明する。なお、図１および図２は一部を切断して
内部構造を示す完成混成集積回路装置の斜視図であり、
図３乃至図７は実施例の各製造段階の断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. 1 and 2 are perspective views of a completed hybrid integrated circuit device showing an internal structure by cutting a part thereof,
3 to 7 are cross-sectional views of each manufacturing stage of the embodiment.
【００１４】図１および図２を参照すると、本発明の混
成集積回路装置は絶縁金属基板(20)の回路パターン形成
面を窪ませて凹部を形成し、この凹部内に集積回路素子
(42)等を搭載した後、凹部に絶縁樹脂(58)を充填して搭
載回路素子を気密封止する構造を備える。従って、本発
明の混成集積回路装置の厚さは外部リード(54)の高さを
考慮しなければ、絶縁金属基板(20)の厚さの高々２倍に
過ぎず、極めて薄型の構造を備える。Referring to FIGS. 1 and 2, in the hybrid integrated circuit device of the present invention, the surface of the insulating metal substrate (20) on which the circuit pattern is formed is recessed to form a recess, and an integrated circuit element is formed in the recess.
After the (42) and the like are mounted, the insulating resin (58) is filled into the recess to hermetically seal the mounted circuit element. Therefore, the thickness of the hybrid integrated circuit device of the present invention is at most twice the thickness of the insulating metal substrate 20 without considering the height of the external leads 54, and has a very thin structure. ..
【００１５】図３を参照すると、絶縁金属基板(20)に
は、放熱特性および加工性を考慮して、表面を陽極酸化
処理した（その酸化膜を符号24で示す）略２ｍｍ厚のア
ルミニウム(22)が使用される。この製造段階の絶縁金属
基板(20)は数乃至十数単位の混成集積回路装置の平面サ
イズを有しており、単位混成集積回路装置への分割を考
慮してスリット（図示しない）が形成されている。この
絶縁金属基板(20)の一主面に、ポリイミド樹脂等の接着
性を有する熱硬化性絶縁樹脂(28)と略３５μｍ厚の銅箔
(30)とからなるクラッド材(26)が温度１５０℃〜１７０
℃、１平方センチメートル当り５０〜１００Ｋｇの圧力
でホットプレスされる。このホットプレス工程により、
熱硬化性絶縁樹脂(30)は完全硬化して略３５μｍ厚の絶
縁層(28)となる。Referring to FIG. 3, the insulating metal substrate (20) is anodized on its surface (the oxide film is indicated by reference numeral 24) of approximately 2 mm in thickness in consideration of heat dissipation characteristics and workability. 22) is used. The insulating metal substrate (20) at this manufacturing stage has a plane size of a hybrid integrated circuit device of several to ten or more units, and a slit (not shown) is formed in consideration of division into the unit hybrid integrated circuit device. ing. On one main surface of the insulating metal substrate (20), a thermosetting insulating resin (28) having adhesiveness such as a polyimide resin and a copper foil having a thickness of about 35 μm are formed.
The clad material (26) consisting of (30) has a temperature of 150 ° C to 170 ° C.
Hot pressed at a temperature of 50 to 100 kg per square centimeter. By this hot pressing process,
The thermosetting insulating resin (30) is completely cured to form an insulating layer (28) having a thickness of about 35 μm.
【００１６】図４を参照すると、ホットプレスされた銅
箔(30)をホトエッチングする等して各種パッド(32)(34)
(36)および図示しない導電路が所定パターンに形成さ
れ、接地導電路を絶縁金属基板(20)に接続するためのア
ルミニウム(22)に達する孔(38)が穿設される。その後、
搭載回路素子を固着するための銀ペースト、半田ペース
ト等のソルダーペースト(40)がダイボンドパッド(32)に
順次、選択的にスクリーン印刷される。Referring to FIG. 4, various pads (32) (34) are formed by photo-etching the hot-pressed copper foil (30).
(36) and a conductive path (not shown) are formed in a predetermined pattern, and a hole (38) reaching the aluminum (22) for connecting the ground conductive path to the insulating metal substrate (20) is formed. afterwards,
A solder paste (40) such as a silver paste and a solder paste for fixing the mounted circuit elements is sequentially and selectively screen-printed on the die bond pad (32).
【００１７】図５を参照すると、集積回路素子(42)、そ
の他の小信号半導体素子は先のソルダーペースト(40)に
一時的に付着させた後、リフローして完全固着され、パ
ワー回路素子(44)のためのヒートシンク(46)、そのパワ
ー回路素子(44)およびチップコンデンサ、あるいはチッ
プ抵抗(48)等は半田等、他のソルダーペーストのスクリ
ーン印刷、当該回路素子の一時的付着、リフローという
工程を繰り返して固着される。この際、後述する外部リ
ードが固着されるパッド上にソルダーペーストがスクリ
ーン印刷される。その後、集積回路素子(42)、パワー回
路素子(44)の電極と所定のパッド(34)および孔(38)と接
地導電路に連続するパッド(34)がボンディングワイア(5
0)で接続される。なお、上記回路素子の固着順序はその
各種ソルダーの溶融温度を考慮して決定される。Referring to FIG. 5, the integrated circuit device (42) and other small signal semiconductor devices are temporarily adhered to the solder paste (40) and then reflowed to be completely fixed to the power circuit device ( The heat sink (46) for 44), the power circuit element (44) and the chip capacitor, or the chip resistor (48), etc. are referred to as screen printing of other solder paste, temporary attachment of the circuit element, and reflow. It is fixed by repeating the process. At this time, the solder paste is screen-printed on a pad to which external leads, which will be described later, are fixed. After that, the electrodes of the integrated circuit element (42), the power circuit element (44), the predetermined pad (34) and the hole (38) and the pad (34) continuous to the ground conductive path are connected to the bonding wire (5).
Connected with 0). The order of fixing the circuit elements is determined in consideration of the melting temperatures of the various solders.
【００１８】図６に先の工程により半完成した混成集積
回路装置の絶縁金属基板(20)をプレス加工する工程を示
す。同図を参照すると、プレス加工装置は絶縁金属基板
(20)の厚さに略等しい幅を残して、絶縁金属基板(20)の
４辺の周辺部を押圧する上金型(60)と抑え金型(62)、絶
縁金属基板(20)の厚さに略等しい幅の４辺の周辺部を剪
断加工する下金型(64)から構成され、アルミニウム(22)
の剪断強度を越す圧力が上金型(60)あるいは下金型(64)
に付与される。この上金型(60)あるいは下金型(64)の行
程は絶縁金属基板(20)を完全剪断しないような、例えば
絶縁金属基板(20)の厚さの略８０％に設定される。絶縁
金属基板(20)の回路パターン形成面の所定の領域を窪ま
せるこのプレス加工により、図７に示すように、絶縁金
属基板(20)にはその周辺部に段部(52)が形成され、この
段部(52)により形成される凹部内に搭載回路素子が収容
される。FIG. 6 shows a step of pressing the insulating metal substrate (20) of the hybrid integrated circuit device semi-finished by the previous step. Referring to the figure, the pressing machine is an insulating metal substrate.
The upper mold (60) for pressing the peripheral portions of the four sides of the insulating metal substrate (20), the pressing mold (62), and the insulating metal substrate (20) while leaving a width approximately equal to the thickness of (20). It is composed of a lower mold (64) that shears the peripheral part of four sides with a width approximately equal to the thickness, and is made of aluminum (22).
The pressure exceeding the shear strength of the upper mold (60) or the lower mold (64)
Granted to. The process of the upper die (60) or the lower die (64) is set to, for example, about 80% of the thickness of the insulating metal substrate (20) so that the insulating metal substrate (20) is not completely sheared. As shown in FIG. 7, a step portion (52) is formed on the peripheral portion of the insulating metal substrate (20) by this press working for recessing a predetermined region of the circuit pattern forming surface of the insulating metal substrate (20). The mounted circuit element is housed in the recess formed by the step (52).
【００１９】前述したように凹部内に回路素子を収容し
た後、リフロー工程等により絶縁金属基板(20)の１以上
の辺に、同図に実線で示すクランク形状の外部リード(5
4)、あるいは同図に破線で示すＬ字形状の外部リードを
固着する。この理由は外部リード固着後のプレス加工が
技術的に困難であるからである。After the circuit element is housed in the recess as described above, the crank-shaped external lead (5) shown by the solid line in the figure is provided on one or more sides of the insulating metal substrate (20) by a reflow process or the like.
4) Or, fix the L-shaped external lead shown by the broken line in the figure. The reason for this is that press working after fixing the external leads is technically difficult.
【００２０】外部リード(54)をパッド(36)上に固着した
後、凹部内の領域にエポキシ樹脂等の比較的流動性が高
い絶縁樹脂(58)を充填、硬化させて、凹部内に配置され
た回路素子、回路パターン等を絶縁樹脂(58)で埋没、配
置する。このように構成された混成集積回路装置では、
回路素子等は上記したように、絶縁樹脂(58)で埋没され
るために、従来のように、密封封止のためのケースが不
要である。従って、本発明では、極めて薄型の混成集積
回路装置を実現することができる。After fixing the external lead (54) on the pad (36), the region in the recess is filled with an insulating resin (58) having a relatively high fluidity such as epoxy resin and hardened, and then placed in the recess. The circuit elements, circuit patterns, etc. thus formed are buried and arranged in an insulating resin (58). In the hybrid integrated circuit device configured as above,
Since the circuit element and the like are buried in the insulating resin (58) as described above, a case for hermetically sealing is not required unlike the conventional case. Therefore, the present invention can realize an extremely thin hybrid integrated circuit device.
【００２１】また、本発明は絶縁金属基板(20)の凹部形
成にプレス（剪断）加工を使用するため、絞加工により
凹部を形成する場合に生ずるアルミニウム(22)、その酸
化膜(24)、絶縁層(28)並びに銅箔回路パターンからなる
積層構造の破壊が生じない特徴を有する。Further, since the present invention uses the press (shear) process for forming the concave portion of the insulating metal substrate (20), the aluminum (22) generated when the concave portion is formed by the drawing process, its oxide film (24), It has a feature that the laminated structure including the insulating layer (28) and the copper foil circuit pattern does not break.
【００２２】図８に本発明の第２の実施例を断面図で示
す。本実施例は第１の実施例の混成集積回路装置の絶縁
樹脂(58)上部を金属ケース(66)で被覆するものであっ
て、それ以前の製造工程は先の実施例と同一である。金
属ケース(66)はその固定と、電気的遮蔽を完全にするた
め、外部リード(54)導出辺を除く絶縁金属基板(20)の加
工断部(52)の側面の複数点でカシメ加工され、絶縁金属
基板(20)と同一電位にされる。FIG. 8 is a sectional view showing the second embodiment of the present invention. In this embodiment, the upper part of the insulating resin (58) of the hybrid integrated circuit device of the first embodiment is covered with the metal case (66), and the manufacturing process before that is the same as the previous embodiment. The metal case (66) is crimped at multiple points on the side surface of the cut portion (52) of the insulating metal substrate (20) excluding the lead-out side of the external lead (54) in order to fix it completely and to electrically shield it. , The same potential as the insulating metal substrate (20).
【００２３】図９に本発明の第３の実施例を断面図で示
す。本実施例は前記第２の実施例の外部リード(54)とし
てリードとその支持、絶縁部を一体成形したファストン
ピン形状の外部リードを使用するものであって、金属ケ
ース(66)の一辺はこの外部リード(54)の支持、絶縁部と
当接配置され、他の辺は先の実施例と同様に、絶縁金属
基板(20)の加工断部(52)の側面の複数点でカシメ加工さ
れ、絶縁金属基板(20)と同一電位にされる。FIG. 9 is a sectional view showing the third embodiment of the present invention. This embodiment uses a faston pin-shaped outer lead in which a lead, its support, and an insulating portion are integrally molded as the outer lead (54) of the second embodiment. One side of the metal case (66) is The outer leads (54) are supported and arranged so as to be in contact with the insulating portion, and the other sides are caulked at a plurality of points on the side surface of the cut portion (52) of the insulating metal substrate (20) as in the previous embodiment. To the same potential as the insulating metal substrate (20).
【００２４】本発明の上記第２および第３の実施例によ
れば、第１の実施例の利点の他、電気的遮蔽が完全に行
われる利点および図９に示すように、厚肉のヒートシン
ク(47)が使用される場合等、搭載高が絶縁金属基板(20)
の凹部の深さより大きい回路素子をも実装できる利点を
有する。According to the above-mentioned second and third embodiments of the present invention, in addition to the advantages of the first embodiment, the advantage of complete electrical shielding and the thick heat sink as shown in FIG. Insulated metal substrate (20) with a mounting height such as when (47) is used
There is an advantage that a circuit element larger than the depth of the concave portion can be mounted.
【００２５】図１０に本発明の第４の実施例を断面図で
示す。本実施例は厚肉のヒートシンク(47)が使用される
場合等、搭載高が絶縁金属基板(20)の凹部の深さより大
きい回路素子を実装する場合の樹脂封止構造を提供する
ものである。露出部の封止樹脂が流動性が高い場合に
は、図示するように、絶縁金属基板(20)の凹部に絶縁樹
脂(58)を充填、硬化した後、露出部を囲む枠体(57)内に
樹脂(59)が充填される。なお、流動性が低い樹脂が使用
される場合にはポッティングによる封止が可能である。FIG. 10 is a sectional view showing the fourth embodiment of the present invention. This embodiment provides a resin sealing structure for mounting a circuit element whose mounting height is larger than the depth of the recess of the insulating metal substrate (20), such as when a thick heat sink (47) is used. .. When the sealing resin of the exposed portion has high fluidity, as shown in the figure, after the insulating resin (58) is filled in the concave portion of the insulating metal substrate (20) and cured, a frame body (57) surrounding the exposed portion is provided. Resin (59) is filled inside. When a resin having low fluidity is used, it can be sealed by potting.
【００２６】第１から第４の実施例では凹部が絶縁金属
基板の略全面にわたって形成されたが、比較的大型の絶
縁金属基板を用いる場合には、基板の変形を考慮して、
凹部をその領域内で複数のブロックに区画してもよい。In the first to fourth embodiments, the concave portion is formed over substantially the entire surface of the insulating metal substrate, but when a relatively large insulating metal substrate is used, the deformation of the substrate is taken into consideration.
The recess may be divided into a plurality of blocks within the area.
【００２７】[0027]
【発明の効果】以上述べたように本発明の混成集積回路
装置は、搭載回路素子を気密封止するためのケース材が
不要であり、従って、その接着のための長時間の熱処理
工程が不要であるため製造に要する時間が短縮される利
点を有する。また、回路素子搭載後の熱処理が削減され
るため、搭載回路素子への熱的影響を考慮する煩雑な温
度管理が不要となる利点も有する。As described above, the hybrid integrated circuit device of the present invention does not require a case material for hermetically sealing the mounted circuit elements, and therefore does not require a long heat treatment step for adhering the same. Therefore, there is an advantage that the time required for manufacturing is shortened. Further, since the heat treatment after mounting the circuit element is reduced, there is also an advantage that complicated temperature control considering the thermal influence on the mounted circuit element becomes unnecessary.
【００２８】外部リードの引き出し方向に制限がないた
め表面実装方式に容易に対応できる利点も有する。さら
に、搭載回路素子を封止樹脂により直接封止するため、
ケース材と搭載回路素子間にマージンが不要になって混
成集積回路装置が薄型に形成できる利点を有する。Since there is no limitation on the direction of pulling out the external leads, there is an advantage that the surface mounting method can be easily applied. Further, since the mounted circuit element is directly sealed with the sealing resin,
There is an advantage that a margin is not required between the case material and the mounted circuit element and the hybrid integrated circuit device can be formed thin.
【図１】本発明の第１の実施例を上部からみた斜視図。FIG. 1 is a perspective view of a first embodiment of the present invention viewed from above.
【図２】本発明の第１の実施例を裏面からみた斜視図。FIG. 2 is a perspective view of the first embodiment of the present invention seen from the back surface.
【図３】実施例の製造工程を説明する断面図。FIG. 3 is a cross-sectional view illustrating the manufacturing process of the example.
【図４】実施例の製造工程を説明する断面図。FIG. 4 is a cross-sectional view illustrating the manufacturing process of the example.
【図５】実施例の製造工程を説明する断面図。FIG. 5 is a cross-sectional view illustrating the manufacturing process of the example.
【図６】実施例の製造工程を説明する断面図。FIG. 6 is a cross-sectional view illustrating the manufacturing process of the example.
【図７】実施例の製造工程を説明する断面図。FIG. 7 is a cross-sectional view illustrating the manufacturing process of the example.
【図８】本発明の第２の実施例の断面図。FIG. 8 is a sectional view of a second embodiment of the present invention.
【図９】本発明の第３の実施例の断面図。FIG. 9 is a sectional view of a third embodiment of the present invention.
【図１０】本発明の第４の実施例の断面図。FIG. 10 is a sectional view of a fourth embodiment of the present invention.
【図１１】従来例の断面図。FIG. 11 is a sectional view of a conventional example.
２０ 絶縁金属基板 ２２ アルミニウム ２４ 酸化膜 ２６ クラッド材 ３２ パッド ３４ パッド ３６ パッド ３８ 孔 ４２ 集積回路素子 ４４ パワー回路素子 ４６ ヒートシンク ４８ チップ抵抗 ５０ ボンディングワイア ５２ 段部 ５４ 外部リード ５８ 絶縁樹脂 20 Insulating Metal Substrate 22 Aluminum 24 Oxide Film 26 Clad Material 32 Pad 34 Pad 36 Pad 38 Hole 42 Integrated Circuit Element 44 Power Circuit Element 46 Heat Sink 48 Chip Resistor 50 Bonding Wire 52 Step 54 External Lead 58 Insulating Resin
Claims (6)
と、 前記回路パターン上に固着、接続された複数の回路素子
および外部リードを備え、 前記絶縁金属基板の回路パターン形成面の所定領域を、
プレス加工して凹部を形成し、この凹部に絶縁樹脂を充
填して前記回路素子を埋設したことを特徴とする混成集
積回路装置。1. An insulating metal substrate, a circuit pattern formed in a predetermined shape on the insulating metal substrate, and a plurality of circuit elements fixedly connected to the circuit pattern and external leads, the insulating metal substrate comprising: Predetermined area of the circuit pattern formation surface,
A hybrid integrated circuit device characterized in that a recess is formed by press working, and the circuit element is buried by filling the recess with an insulating resin.
と、 前記回路パターン上に固着、接続された複数の回路素子
およびクランク形状の表面実装型の外部リードを備え、 前記絶縁金属基板の回路パターン形成面の所定領域を、
プレス加工して凹部を形成し、この凹部に絶縁樹脂を充
填して前記回路素子を埋設したことを特徴とする混成集
積回路装置。2. An insulating metal substrate, a circuit pattern formed in a predetermined shape on the insulating metal substrate, a plurality of circuit elements fixedly connected to the circuit pattern, and a crank-shaped surface-mounted external lead. The predetermined area of the circuit pattern forming surface of the insulating metal substrate,
A hybrid integrated circuit device characterized in that a recess is formed by press working, and the circuit element is buried by filling the recess with an insulating resin.
と、 前記回路パターン上に固着、接続された複数の回路素子
および外部リードを備え、 前記絶縁金属基板の回路パターン形成面の所定領域を、
プレス加工して凹部を形成し、この凹部に絶縁樹脂を充
填して前記回路素子を埋設すると共にこの絶縁樹脂上部
を、絶縁金属基板と同電位の金属ケースで被覆したこと
を特徴とする混成集積回路装置。3. An insulating metal substrate, a circuit pattern formed in a predetermined shape on the insulating metal substrate, and a plurality of circuit elements fixed and connected to the circuit pattern and external leads, the insulating metal substrate comprising: Predetermined area of the circuit pattern formation surface,
A hybrid integrated device characterized in that a recess is formed by pressing, the recess is filled with an insulating resin to embed the circuit element, and the upper portion of the insulating resin is covered with a metal case having the same potential as the insulating metal substrate. Circuit device.
と、 前記回路パターン上に固着、接続された複数の回路素子
およびリードとその支持、絶縁部が一体成形されたファ
スントピン形状の外部リードを備え、 前記絶縁金属基板の回路パターン形成面の所定領域を、
プレス加工して凹部を形成し、この凹部に絶縁樹脂を充
填して前記回路素子を埋設すると共にこの絶縁樹脂上部
を、前記外部リードの支持、絶縁部と一端が当接配置さ
れ、他端で前記絶縁金属基板と同電位となるように接続
される金属ケースで被覆したことを特徴とする混成集積
回路装置。4. An insulating metal substrate, a circuit pattern formed in a predetermined shape on the insulating metal substrate, a plurality of circuit elements and leads fixed and connected to the circuit pattern, their supports, and an insulating portion are integrally molded. A fast pin-shaped external lead, the predetermined area of the circuit pattern forming surface of the insulating metal substrate,
The concave portion is formed by press working, the concave portion is filled with an insulating resin to embed the circuit element, and the upper portion of the insulating resin is disposed so as to support the external lead and one end is in contact with the insulating portion, and the other end is A hybrid integrated circuit device characterized by being covered with a metal case connected so as to have the same potential as the insulating metal substrate.
と、 前記回路パターン上に固着、接続された小信号用回路素
子、ヒートシンク上に搭載されるパワー回路素子、およ
び前記回路パターン上に固着、接続される外部リードを
備え、 前記絶縁金属基板の回路パターン形成面の所定領域を、
プレス加工して凹部を形成し、この凹部に絶縁樹脂を充
填して前記小信号用回路素子を埋設させたことを特徴と
する混成集積回路装置。5. An insulating metal substrate, a circuit pattern formed in a predetermined shape on the insulating metal substrate, a small-signal circuit element fixed and connected to the circuit pattern, and a power circuit element mounted on a heat sink. , And an external lead fixedly connected to the circuit pattern, the predetermined area of the circuit pattern forming surface of the insulating metal substrate,
A hybrid integrated circuit device characterized in that a recess is formed by press working, and the recess is filled with an insulating resin to embed the small signal circuit element.
状に形成する工程と、 前記回路パターン上の所定位置に複数の回路素子を固
着、搭載する工程と、 前記絶縁金属基板の回路パターン形成面の所定の領域を
プレス加工して凹部を形成した後、外部リードを固着す
る工程と、 前記絶縁金属基板の凹部に絶縁樹脂を充填して、前記回
路素子を埋設する工程からなる混成集積回路装置の製造
方法。6. A step of forming a circuit pattern in a predetermined shape on an insulating metal substrate, a step of fixing and mounting a plurality of circuit elements at predetermined positions on the circuit pattern, and a circuit pattern forming surface of the insulating metal substrate. Of a predetermined integrated region of the insulating metal substrate after pressing to form a recess and then fixing external leads, and a step of filling the recess of the insulating metal substrate with an insulating resin and burying the circuit element. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3313586A JPH05129742A (en) | 1991-10-31 | 1991-10-31 | Hybrid integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3313586A JPH05129742A (en) | 1991-10-31 | 1991-10-31 | Hybrid integrated circuit device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129742A true JPH05129742A (en) | 1993-05-25 |
Family
ID=18043099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3313586A Pending JPH05129742A (en) | 1991-10-31 | 1991-10-31 | Hybrid integrated circuit device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129742A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003103355A1 (en) * | 2002-05-30 | 2003-12-11 | 太陽誘電株式会社 | Composite multi-layer substrate and module using the substrate |
| US10396261B2 (en) | 2016-06-30 | 2019-08-27 | Nichia Corporation | Light emitting device and method of manufacturing the light emitting device |
-
1991
- 1991-10-31 JP JP3313586A patent/JPH05129742A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003103355A1 (en) * | 2002-05-30 | 2003-12-11 | 太陽誘電株式会社 | Composite multi-layer substrate and module using the substrate |
| US7348662B2 (en) | 2002-05-30 | 2008-03-25 | Taiyo Yuden Co., Ltd. | Composite multi-layer substrate and module using the substrate |
| CN100435604C (en) * | 2002-05-30 | 2008-11-19 | 太阳诱电株式会社 | Composite multi-layer substrate and module using the substrate |
| US7745926B2 (en) | 2002-05-30 | 2010-06-29 | Taiyo Yuden Co., Ltd. | Composite multi-layer substrate and module using the substrate |
| US7928560B2 (en) | 2002-05-30 | 2011-04-19 | Taiyo Yuden Co., Ltd. | Composite multi-layer substrate and module using the substrate |
| USRE45146E1 (en) | 2002-05-30 | 2014-09-23 | Taiyo Yuden Co., Ltd | Composite multi-layer substrate and module using the substrate |
| US10396261B2 (en) | 2016-06-30 | 2019-08-27 | Nichia Corporation | Light emitting device and method of manufacturing the light emitting device |
| US11227983B2 (en) | 2016-06-30 | 2022-01-18 | Nichia Corporation | Light emitting device and method of manufacturing the light emitting device |
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