JPH05121615A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05121615A JPH05121615A JP30682791A JP30682791A JPH05121615A JP H05121615 A JPH05121615 A JP H05121615A JP 30682791 A JP30682791 A JP 30682791A JP 30682791 A JP30682791 A JP 30682791A JP H05121615 A JPH05121615 A JP H05121615A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- terminal
- connection
- connection terminal
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置関する。さら
に詳しくは、外部接続端子の少なくとも一つがリード線
を用いることなく半導体素子の接続端子と接続されてい
る半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device in which at least one of external connection terminals is connected to a connection terminal of a semiconductor element without using a lead wire.
【０００２】[0002]
【従来の技術】従来より半導体装置においては、図７に
示すように外部接続端子１０１、１０３と半導体素子１
０５の接続端子との接続は、リード線１０４を用いて行
われている。2. Description of the Related Art Conventionally, in a semiconductor device, as shown in FIG. 7, external connection terminals 101 and 103 and a semiconductor element 1 are provided.
The lead wire 104 is used for connection with the connection terminal 05.
【０００３】このリード線１０４の材質には金が使用さ
れているので、製品のコスト増大の要因となっている。
また、リード線１０４と必要以外の端子との無用の接続
を避けるために、リード線には、図７に示すようにルー
プを設ける必要があるので、製品の薄型化を妨げる要因
になっている。Since gold is used as the material of the lead wire 104, this is a factor of increasing the cost of the product.
Further, in order to avoid unnecessary connection between the lead wire 104 and an unnecessary terminal, the lead wire needs to be provided with a loop as shown in FIG. 7, which is a factor that hinders the product from becoming thinner. ..
【０００４】さらに、ヒートシンクとしては、外部接続
端子１０２しか寄与していないという問題もある。Further, there is a problem that only the external connection terminal 102 contributes to the heat sink.
【０００５】[0005]
【発明が解決しようとする課題】本発明はかかる従来技
術の問題点に鑑みなされたものであって、製品コストの
増大を招来している貴金属の使用量が削減されるととも
に、製品の薄型化傾向に対応できる半導体装置を提供す
ることを主目的としている。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art. It reduces the amount of precious metal used, which causes an increase in product cost, and makes the product thinner. The main purpose is to provide a semiconductor device which can cope with the tendency.
【０００６】さらに、本発明は放熱効率の改善された半
導体装置を提供することをも目的としている。A further object of the present invention is to provide a semiconductor device having improved heat dissipation efficiency.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置は、
２またはそれ以上の外部接続端子を有する半導体装置で
あって、前記外部接続端子のうちの少なくとも一つが接
続部材を有し、該接続部材が直接半導体素子の接続端子
と接続されてなることを特徴としている。The semiconductor device of the present invention comprises:
A semiconductor device having two or more external connection terminals, wherein at least one of the external connection terminals has a connection member, and the connection member is directly connected to the connection terminal of the semiconductor element. I am trying.
【０００８】また、本発明の半導体装置においては、外
部接続端子の接続部材を有する部分の面積が拡大されて
いるのが好ましい。Further, in the semiconductor device of the present invention, it is preferable that the area of the portion having the connection member of the external connection terminal is enlarged.
【０００９】[0009]
【作用】本発明の半導体装置においては、外部接続端子
に接続部材を設け、それを半導体装置の接続端子に直接
接続させているので、リード線が不用となるとともに、
リード線のショートを避けるためのループも不用とな
る。In the semiconductor device of the present invention, the external connecting terminal is provided with the connecting member and is directly connected to the connecting terminal of the semiconductor device. Therefore, the lead wire becomes unnecessary and
Loops for avoiding lead wire shorts are also unnecessary.
【００１０】また、外部接続端子の接続部材を有する面
を拡大すれば、結果的に放熱面積が拡大されるので、放
熱効率を改善することができる。Further, if the surface of the external connection terminal having the connection member is enlarged, the heat radiation area is consequently enlarged, so that the heat radiation efficiency can be improved.
【００１１】[0011]
【実施例】以下、添付図面を参照しながら本発明を実施
例に基づいて説明するが、本発明はかかる実施例のみに
限定されるものではない。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the accompanying drawings, but the present invention is not limited to such embodiments.
【００１２】図１は本発明の第１実施例の概略図、図２
は本発明の第２実施例の概略図、図３は第１〜２実施例
の端子接続部の説明図、図４は第３実施例の概略図、図
５は第３実施例における熱拡散の状態の説明図、図６は
第４実施例の概略図である。図において、１は第１接続
端子、２は第２接続端子、３は第３接続端子、４は半導
体素子、５は接続部材、６はリード線を示す。また、図
５における矢印は熱の伝導拡散方向を示す。FIG. 1 is a schematic view of a first embodiment of the present invention, FIG.
Is a schematic diagram of the second embodiment of the present invention, FIG. 3 is an explanatory diagram of the terminal connecting portions of the first and second embodiments, FIG. 4 is a schematic diagram of the third embodiment, and FIG. 5 is thermal diffusion in the third embodiment. And FIG. 6 is a schematic view of the fourth embodiment. In the figure, 1 is a first connecting terminal, 2 is a second connecting terminal, 3 is a third connecting terminal, 4 is a semiconductor element, 5 is a connecting member, and 6 is a lead wire. Moreover, the arrow in FIG. 5 shows the heat conduction diffusion direction.
【００１３】図１に示すように、第１実施例においては
第１接続端子１Ａおよび第３接続端子３Ａは、一方の先
端部の一部が第１接続端子１Ａおよび第３接続端子３Ａ
の長手方向に対しては略直角方向に、かつ略ステップ状
に互いに向き合うように***せしめられている。このス
テップ状に***せしめられた部分には、図３に示すよう
に接続部材５が配設されている。この接続部材５は、直
径が概略５０〜７０μｍの金ボ−ルまたはペ−スト状半
田などからなり、第１接続端子１Ａおよび第３接続端子
３Ａと半導体素子４Ａの間に位置する金ボ−ルは、熱圧
着により接続端子１Ａ，３Ａと半導体素子４Ａ間の電気
導電性を確保する。ペ−スト状半田の場合は、半田の表
面張力現象により、接続端子１Ａ，３Ａと半導体素子４
Ａ間に位置し、ひき続き熱処理を施されることにより、
電気導電性を確保する。そして、この接続部材５は、図
３に示すように半導体素子４Ａの接続端子に直接接続さ
れている。第１接続端子１Ａおよび第３接続端子３Ａの
その余の構成は、従来より半導体装置に用いられている
外部接続端子と同様であるので、その構成の詳細な説明
は省略する。As shown in FIG. 1, in the first embodiment, the first connecting terminal 1A and the third connecting terminal 3A have a first connecting terminal 1A and a third connecting terminal 3A with a part of one end portion thereof.
Are raised so as to face each other in a substantially stepwise manner in a direction substantially perpendicular to the longitudinal direction of the. A connecting member 5 is provided in the stepped portion, as shown in FIG. The connecting member 5 is made of gold ball or paste solder having a diameter of approximately 50 to 70 μm, and is located between the first connecting terminal 1A and the third connecting terminal 3A and the semiconductor element 4A. The thermoelectric bonding ensures the electrical conductivity between the connection terminals 1A and 3A and the semiconductor element 4A. In the case of paste-like solder, the connection terminals 1A and 3A and the semiconductor element 4 are caused by the surface tension phenomenon of the solder.
It is located between A and is continuously heat treated,
Ensure electrical conductivity. The connecting member 5 is directly connected to the connecting terminal of the semiconductor element 4A as shown in FIG. The other configurations of the first connection terminal 1A and the third connection terminal 3A are similar to those of the external connection terminals conventionally used in semiconductor devices, and thus detailed description of the configurations is omitted.
【００１４】なお、接続部材５と半導体素子４Ａの接続
端子との導通は、第１接続端子１Ａおよび第３接続端子
３Ａと半導体素子４Ａの間に位置する金ボ−ルを熱圧着
することにより、接続端子１Ａ，３Ａと半導体素子４Ａ
間の電気導電性を確保する。ペ−スト状半田の場合は、
半田の表面張力現象により、接続端子と半導体素子間に
位置し、ひき続き熱処理を施されることにより、電気導
電性を確保する。The connection between the connection member 5 and the connection terminal of the semiconductor element 4A is achieved by thermocompression bonding of a gold ball located between the first connection terminal 1A and the third connection terminal 3A and the semiconductor element 4A. , Connection terminals 1A, 3A and semiconductor element 4A
Ensure electrical conductivity between. In the case of paste solder,
It is located between the connection terminal and the semiconductor element due to the surface tension phenomenon of the solder, and is subsequently subjected to heat treatment to ensure electrical conductivity.
【００１５】前述のように、第１実施例によればリード
線を用いることなく外部接続端子と半導体素子の接続端
子とを接続することができる。As described above, according to the first embodiment, the external connection terminal and the connection terminal of the semiconductor element can be connected without using a lead wire.
【００１６】図２に示す第２実施例では、接続部材５を
有する第１接続端子１Ｂおよび第３接続端子３Ｂが長手
方向にステップ状に***せしめられている。このように
構成された第１および第３接続端子を用いれば、該端子
間の間隔を狭めることができ、半導体装置を小型化する
ことができる。第２実施例のその余の構成は、第１実施
例と同様であるので、その構成の詳細な説明は省略す
る。In the second embodiment shown in FIG. 2, the first connecting terminal 1B and the third connecting terminal 3B having the connecting member 5 are raised in a step shape in the longitudinal direction. By using the first and third connection terminals configured as described above, the distance between the terminals can be narrowed, and the semiconductor device can be downsized. The rest of the configuration of the second embodiment is similar to that of the first embodiment, so a detailed description of that configuration will be omitted.
【００１７】図４に示す第３実施例においては、第１接
続端子１Ｃは、接続部材５Ｃを有する部分が拡大されて
いる他は、第１実施例のそれと略同様に形成されてい
る。一方、第３接続端子３Ｃは従来のそれと同様に形成
されている。そして、第３接続端子３Ｃと半導体素子４
Ｃとはリード線６により接続されている。In the third embodiment shown in FIG. 4, the first connection terminal 1C is formed in substantially the same manner as that of the first embodiment except that the portion having the connection member 5C is enlarged. On the other hand, the third connection terminal 3C is formed similarly to the conventional one. Then, the third connection terminal 3C and the semiconductor element 4
It is connected to C by a lead wire 6.
【００１８】第３実施例によれば、リード線の本数を従
来のものと比較して半減できるとともに、第１接続端子
１Ｃは、接続部材５Ｃを有する部分が拡大されており、
この部分はヒートシンクとしても作用するので、熱拡散
効率が改善される（図５参照）。According to the third embodiment, the number of lead wires can be halved as compared with the conventional one, and the first connecting terminal 1C has an enlarged portion having the connecting member 5C.
Since this portion also functions as a heat sink, the heat diffusion efficiency is improved (see FIG. 5).
【００１９】図６に示す第４実施例においては、第３の
接続端子３Ｄが第１実施例のそれと略同様に形成されて
いる他は、第３実施例と同様に形成されている。The fourth embodiment shown in FIG. 6 is formed in the same manner as the third embodiment except that the third connection terminal 3D is formed in substantially the same manner as that of the first embodiment.
【００２０】第４実施例によれば、リード線が不用とな
るばかりでなく、第３実施例同様熱拡散効率も改善され
る。According to the fourth embodiment, not only is the lead wire unnecessary, but the thermal diffusion efficiency is improved as in the third embodiment.
【００２１】[0021]
【発明の効果】以上説明したように、本発明によればリ
ード線を用いることなく外部接続端子と半導体素子の接
続端子との接続を行っているので、製品のコスト削減が
達成できるとともに製品の薄型化にも対処できる。さら
に、外部接続端子の接続部材が配設された部分の面積が
拡大された実施例によれば熱拡散効率も改善することが
できる。As described above, according to the present invention, since the external connection terminal and the connection terminal of the semiconductor element are connected without using the lead wire, the cost reduction of the product can be achieved and the product It can also be made thinner. Furthermore, according to the embodiment in which the area of the portion of the external connection terminal where the connection member is disposed is enlarged, the heat diffusion efficiency can be improved.
【図１】本発明の第１実施例の概略図である。FIG. 1 is a schematic diagram of a first embodiment of the present invention.
【図２】本発明の第２実施例の概略図である。FIG. 2 is a schematic diagram of a second embodiment of the present invention.
【図３】第１〜２実施例の端子接続部の説明図である。FIG. 3 is an explanatory diagram of a terminal connecting portion according to first and second embodiments.
【図４】第３実施例の概略図である。FIG. 4 is a schematic diagram of a third embodiment.
【図５】第３実施例における熱伝導拡散の状態の説明図
である。FIG. 5 is an explanatory diagram of a state of heat conduction diffusion in the third embodiment.
【図６】第４実施例の概略図である。FIG. 6 is a schematic diagram of a fourth embodiment.
【図７】従来の半導体装置の概略図である。FIG. 7 is a schematic view of a conventional semiconductor device.
１ 第１接続端子 ２ 第２接続端子 ３ 第３接続端子 ４ 半導体素子 ５ 接続部材 ６ リード線 1 1st connection terminal 2 2nd connection terminal 3 3rd connection terminal 4 Semiconductor element 5 Connection member 6 Lead wire
Claims (2)
る半導体装置であって、前記外部接続端子のうちの少な
くとも一つが接続部材を有し、該接続部材が直接半導体
素子の接続端子と接続されてなることを特徴とする半導
体装置。1. A semiconductor device having two or more external connection terminals, wherein at least one of the external connection terminals has a connection member, and the connection member is directly connected to a connection terminal of a semiconductor element. A semiconductor device characterized by the following.
分の面積が拡大されてなることを特徴とする請求項１記
載の半導体装置。2. The semiconductor device according to claim 1, wherein the area of the portion having the connection member of the external connection terminal is enlarged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30682791A JP2941523B2 (en) | 1991-10-25 | 1991-10-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30682791A JP2941523B2 (en) | 1991-10-25 | 1991-10-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05121615A true JPH05121615A (en) | 1993-05-18 |
| JP2941523B2 JP2941523B2 (en) | 1999-08-25 |
Family
ID=17961739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30682791A Expired - Fee Related JP2941523B2 (en) | 1991-10-25 | 1991-10-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2941523B2 (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821611A (en) * | 1994-11-07 | 1998-10-13 | Rohm Co. Ltd. | Semiconductor device and process and leadframe for making the same |
| WO2001031704A1 (en) * | 1999-10-28 | 2001-05-03 | Rohm Co., Ltd. | Semiconductor device |
| US6479888B1 (en) | 1999-02-17 | 2002-11-12 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
| US6573119B1 (en) | 1999-02-17 | 2003-06-03 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
| US6774466B1 (en) | 1999-01-28 | 2004-08-10 | Renesas Technology Corp. | Semiconductor device |
| JP2004349347A (en) * | 2003-05-20 | 2004-12-09 | Rohm Co Ltd | Semiconductor device |
| US7138673B2 (en) | 2002-08-19 | 2006-11-21 | Nec Electronics Corporation | Semiconductor package having encapsulated chip attached to a mounting plate |
| EP1246243A3 (en) * | 2001-03-29 | 2009-03-11 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
| US9425122B2 (en) | 2012-12-21 | 2016-08-23 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing the same |
| US9449944B2 (en) | 2012-12-21 | 2016-09-20 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing same |
| US9595651B2 (en) | 2012-12-21 | 2017-03-14 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing same |
| CN106684152A (en) * | 2017-01-11 | 2017-05-17 | 山东天岳晶体材料有限公司 | Cooling type field effect tube |
| US9825209B2 (en) | 2012-12-21 | 2017-11-21 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing the same |
| WO2021002225A1 (en) * | 2019-07-01 | 2021-01-07 | ローム株式会社 | Semiconductor device |
-
1991
- 1991-10-25 JP JP30682791A patent/JP2941523B2/en not_active Expired - Fee Related
Cited By (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821611A (en) * | 1994-11-07 | 1998-10-13 | Rohm Co. Ltd. | Semiconductor device and process and leadframe for making the same |
| US8816411B2 (en) | 1999-01-28 | 2014-08-26 | Renesas Electronics Corporation | Mosfet package |
| US7332757B2 (en) | 1999-01-28 | 2008-02-19 | Renesas Technology Corp. | MOSFET package |
| US7394146B2 (en) | 1999-01-28 | 2008-07-01 | Renesas Tehcnology Corp. | MOSFET package |
| US7985991B2 (en) | 1999-01-28 | 2011-07-26 | Renesas Electronics Corporation | MOSFET package |
| US6774466B1 (en) | 1999-01-28 | 2004-08-10 | Renesas Technology Corp. | Semiconductor device |
| US8183607B2 (en) | 1999-01-28 | 2012-05-22 | Renesas Electronics Corporation | Semiconductor device |
| US7400002B2 (en) | 1999-01-28 | 2008-07-15 | Renesas Technology Corp. | MOSFET package |
| US8455986B2 (en) | 1999-01-28 | 2013-06-04 | Renesas Electronics Corporation | Mosfet package |
| US7342267B2 (en) | 1999-01-28 | 2008-03-11 | Renesas Technology Corp. | MOSFET package |
| US6812554B2 (en) | 1999-02-17 | 2004-11-02 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US7160760B2 (en) | 1999-02-17 | 2007-01-09 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US7385279B2 (en) | 1999-02-17 | 2008-06-10 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US6573119B1 (en) | 1999-02-17 | 2003-06-03 | Hitachi, Ltd. | Semiconductor device and method of manufacture thereof |
| US6479888B1 (en) | 1999-02-17 | 2002-11-12 | Hitachi, Ltd. | Semiconductor device and a method of manufacturing the same |
| US7812464B2 (en) | 1999-02-17 | 2010-10-12 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing for high output MOSFET |
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| US6650004B1 (en) | 1999-10-28 | 2003-11-18 | Rohm Co., Ltd. | Semiconductor device |
| EP1246243A3 (en) * | 2001-03-29 | 2009-03-11 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
| US7138673B2 (en) | 2002-08-19 | 2006-11-21 | Nec Electronics Corporation | Semiconductor package having encapsulated chip attached to a mounting plate |
| US7449370B2 (en) | 2002-08-19 | 2008-11-11 | Nec Electronics Corporation | Production process for manufacturing such semiconductor package |
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| US9425122B2 (en) | 2012-12-21 | 2016-08-23 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing the same |
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| US9595651B2 (en) | 2012-12-21 | 2017-03-14 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing same |
| US9825209B2 (en) | 2012-12-21 | 2017-11-21 | Panasonic Intellectual Property Management Co., Ltd. | Electronic component package and method for manufacturing the same |
| CN106684152A (en) * | 2017-01-11 | 2017-05-17 | 山东天岳晶体材料有限公司 | Cooling type field effect tube |
| WO2021002225A1 (en) * | 2019-07-01 | 2021-01-07 | ローム株式会社 | Semiconductor device |
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