JPH0511010A - Method and device for testing semiconductor device - Google Patents
Method and device for testing semiconductor deviceInfo
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- JPH0511010A JPH0511010A JP3164331A JP16433191A JPH0511010A JP H0511010 A JPH0511010 A JP H0511010A JP 3164331 A JP3164331 A JP 3164331A JP 16433191 A JP16433191 A JP 16433191A JP H0511010 A JPH0511010 A JP H0511010A
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- semiconductor device
- capacitance
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高集積で多機能化した
半導体デバイスの試験に有効な、リレー回路を削減し実
装密度を高めた半導体デバイスの試験方法および半導体
デバイス試験装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device testing method and a semiconductor device testing apparatus which are effective for testing highly integrated and multifunctionalized semiconductor devices and which have a reduced number of relay circuits and have a higher packaging density. .
【０００２】[0002]
【従来の技術】近年、半導体デバイスの高集積化と多機
能化は著しく、半導体デバイスの試験装置および試験方
法は、いかに高い保証レベルで機能の計測を実現するか
重要になってきた。2. Description of the Related Art In recent years, semiconductor devices have become highly integrated and multifunctional, and it has become important for semiconductor device test apparatuses and test methods to realize function measurement at a high assurance level.
【０００３】以下に、従来の半導体デバイスの試験方法
および試験装置について説明する。図３は一つの端子に
ついて示した、一般的な従来の半導体デバイスの試験装
置の試験回路図である。被測定用デバイス１の端子２へ
は、試験装置３が接続される。試験装置３上には２系統
のリレー４，５を配してある。前者の直流試験用リレー
４にはインピーダンス６を経て直流信号伝送路７の一端
が接続され、直流信号伝送路７のもう一端には直流計測
系８が接続される。直流計測系８は直流の電圧計や電圧
印加電流測定電源、又は電流印加電圧測定電源で構成さ
れる。一方、後者の交流試験用リレー５へはキャパシタ
ンス９を経て、接地したインピーダンス１０と交流信号
伝送路１１の一端が接続され、交流信号伝送路１１のも
う一端には交流信号源１２が接続される。交流信号源１
２の内部インピーダンスＺ１２と交流信号伝送路１１の
特性インピーダンスＺ１１、及びインピーダンス１０の
値Ｚ１０は、つぎのように、
Ｚ１２＝Ｚ１１＝Ｚ１０
という、整合のとれた関係である。交流信号源１２は正
弦波や方形波、又は任意波形を発生させる。A conventional semiconductor device testing method and testing apparatus will be described below. FIG. 3 is a test circuit diagram of a general conventional semiconductor device test apparatus showing one terminal. The test apparatus 3 is connected to the terminal 2 of the device under test 1. Two relays 4 and 5 are arranged on the test apparatus 3. The former DC test relay 4 is connected to one end of a DC signal transmission line 7 via an impedance 6, and the DC measurement system 8 is connected to the other end of the DC signal transmission line 7. The DC measuring system 8 is composed of a DC voltmeter, a voltage applied current measuring power source, or a current applied voltage measuring power source. On the other hand, the latter AC test relay 5 is connected to the grounded impedance 10 and one end of the AC signal transmission line 11 via the capacitance 9, and the AC signal source 12 is connected to the other end of the AC signal transmission line 11. . AC signal source 1
The internal impedance Z12 of No. 2, the characteristic impedance Z11 of the AC signal transmission line 11, and the value Z10 of the impedance 10 have a matched relationship of Z12 = Z11 = Z10 as follows. The AC signal source 12 generates a sine wave, a square wave, or an arbitrary waveform.
【０００４】以上のように構成された半導体デバイスの
試験装置および試験方法について、以下にその動作につ
いて説明する。The operation of the semiconductor device testing apparatus and testing method configured as described above will be described below.
【０００５】まず、直流試験用リレー４を閉じて直流計
測系８から直流の電圧等を印加し、被測定用デバイス１
の直流試験を実施する。次に、直流試験用リレー４を開
き、交流試験用リレー５を閉じて交流信号源１２から交
流信号を印加し、被測定用デバイス１の交流試験を実施
する。First, the DC test relay 4 is closed and a DC voltage or the like is applied from the DC measurement system 8 to measure the device under test 1
Conduct the DC test of. Next, the direct-current test relay 4 is opened, the alternating-current test relay 5 is closed, an alternating-current signal is applied from the alternating-current signal source 12, and the alternating-current test of the device under test 1 is performed.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら上記の従
来の構成では、被測定用デバイス１で直流と交流の試験
が必要な場合、一つの端子２へは、直流試験用リレー４
と交流試験用リレー５の二つのリレーを接続する必要が
あった。高集積化と多機能化した被測定用デバイス１で
直流と交流の試験が多くの端子で必要な場合、接続する
リレー４，５は端子に比例して増加し、試験装置３の実
装面積とサイズが大きくなるという欠点を有していた。However, in the above-mentioned conventional configuration, when the device under test 1 needs to be tested for direct current and alternating current, one terminal 2 is connected to the direct current test relay 4
It was necessary to connect the two relays of AC test relay 5 and. When the DC and AC tests are required at many terminals in the highly integrated and multifunctional device under test 1, the number of relays 4 and 5 to be connected increases in proportion to the terminals, and the mounting area of the test apparatus 3 is It had the drawback of being large in size.
【０００７】本発明は、上記従来の課題を解決するもの
で、一つの端子へ接続する二つのリレーを削除し、試験
装置の実装面積とサイズを小さくすることのできる半導
体デバイスの試験方法および試験装置を提供することを
目的とする。The present invention solves the above-mentioned conventional problems, and eliminates two relays connected to one terminal, thereby reducing the mounting area and size of a test apparatus and a semiconductor device test method and test. The purpose is to provide a device.
【０００８】[0008]
【課題を解決するための手段】この目的を達成するため
に本発明の半導体デバイスの試験方法および試験装置
は、被測定用半導体デバイスの端子に対し２系統の伝送
系を備え、一方の伝送系は直列インピーダンスＺ１の一
端を上記半導体デバイスの端子に接続し、上記直列イン
ピーダンスＺ１の他端に一端を接地したキャパシタンス
Ｃ１の他端と直流信号伝送路の一端を接続し、他方の伝
送系は直列キャパシタンスＣ２の一端を上記半導体デバ
イスの端子に接続し、上記直列キャパシタンスＣ２の他
端に一端を接地したインピーダンスＺ２の他端と特性イ
ンピーダンスＺ０の交流信号伝送路の一端を接続し、そ
の交流信号伝送路の特性インピーダンスＺ０と、インピ
ーダンスＺ１とインピーダンスＺ２の合成インピーダン
スＺ１In order to achieve this object, a semiconductor device testing method and testing apparatus according to the present invention are provided with two transmission systems for terminals of a semiconductor device to be measured, and one transmission system is provided. Is one end of the series impedance Z1 is connected to the terminal of the semiconductor device, the other end of the series impedance Z1 is connected to the other end of the capacitance C1 whose one end is grounded and one end of the DC signal transmission path, and the other transmission system is in series. One end of the capacitance C2 is connected to the terminal of the semiconductor device, the other end of the series capacitance C2 is connected to the other end of the impedance Z2 whose one end is grounded, and one end of the AC signal transmission path of the characteristic impedance Z0, and the AC signal transmission is performed. Characteristic impedance Z0 of the path and combined impedance Z1 of impedance Z1 and impedance Z2
【０００９】[0009]
【外５】 [Outside 5]
【００１０】Ｚ２とが等しく（Ｚ０＝Ｚ１Z2 is equal to (Z0 = Z1
【００１１】[0011]
【外６】 [Outside 6]
【００１２】Ｚ２）、上記キャパシタンスＣ１，Ｃ２は
交流信号に対し、充分小さいインピーダンス値をとるよ
うにした構成による。Z2) The capacitances C1 and C2 have a sufficiently small impedance value for an AC signal.
【００１３】[0013]
【作用】この構成によって、キャパシタンスＣ２を設け
たことにより、直流試験の実施時に、直流成分が遮断さ
れ以降の交流試験用伝送系には影響を及ぼさず、又キャ
パシタンスＣ１を設けたことにより、交流試験の実施時
に、交流成分が遮断され以降の直流試験用伝送系には影
響を及ぼさない。更にＺ０＝Ｚ１With this configuration, by providing the capacitance C2, the direct current component is cut off during the execution of the direct current test, and the transmission system for alternating current test after that is not affected, and by providing the capacitance C1, the alternating current When the test is carried out, the AC component is cut off, and the transmission system for DC test after that is not affected. Furthermore, Z0 = Z1
【００１４】[0014]
【外７】 [Outside 7]
【００１５】Ｚ２という整合条件が成立しているので、
リレーを用いなくとも従来例と同様の試験をすることが
できる。Since the matching condition of Z2 is established,
The same test as the conventional example can be performed without using a relay.
【００１６】[0016]
【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【００１７】図１は本発明の一実施例における一つの端
子について示した半導体デバイスの試験装置の試験回路
図である。被測定用半導体デバイス２１の端子２２へは
試験装置２３が接続される。試験装置２３上には２系統
の伝送系を配してある。前者の直流試験用伝送系はイン
ピーダンス２４を経て、接地したキャパシタンス２５と
直流信号伝送路２６の一端が接続され、直流信号伝送路
２６のもう一端には直流計測系２７が接続される。直流
計測系２７は直流の電圧計や電圧印加電流測定電源、又
は電流印加電圧測定電源で構成される。一方、後者の交
流試験用伝送系はキャパシタンス２８を経て、接地した
インピーダンス２９と交流信号伝送路３０の一端が接続
され、交流信号伝送路３０のもう一方の一端には交流信
号源３１が接続される。交流信号源３１の内部インピー
ダンスＺ３１と交流信号伝送路３０の特性インピーダン
スＺ０とが等しく、その値とインピーダンス２４，２９
の並列インピーダンスＺ１FIG. 1 is a test circuit diagram of a semiconductor device test apparatus showing one terminal in one embodiment of the present invention. The test apparatus 23 is connected to the terminal 22 of the semiconductor device 21 to be measured. Two transmission systems are arranged on the test apparatus 23. In the former DC test transmission system, a grounded capacitance 25 and one end of a DC signal transmission line 26 are connected via an impedance 24, and a DC measurement system 27 is connected to the other end of the DC signal transmission line 26. The DC measuring system 27 is composed of a DC voltmeter, a voltage applied current measuring power supply, or a current applied voltage measuring power supply. On the other hand, in the latter AC test transmission system, the grounded impedance 29 and one end of the AC signal transmission line 30 are connected via the capacitance 28, and the AC signal source 31 is connected to the other end of the AC signal transmission line 30. It The internal impedance Z31 of the AC signal source 31 and the characteristic impedance Z0 of the AC signal transmission line 30 are equal to each other, and their values and the impedances 24 and 29 are equal to each other.
Parallel impedance Z1
【００１８】[0018]
【外８】 [Outside 8]
【００１９】Ｚ２が等しい。すなわちＺ３１＝Ｚ０＝Ｚ
１Z2 is equal. That is, Z31 = Z0 = Z
1
【００２０】[0020]
【外９】 [Outside 9]
【００２１】Ｚ２のように整合のとれた関係であり、キ
ャパシタンス２８，２５は交流信号に対し、充分に小さ
いインピーダンス値をとる。交流信号源３１は正弦波や
方形波、又は任意波形を発生させる。The capacitances 28 and 25 have a matched relationship like Z2, and have sufficiently small impedance values with respect to an AC signal. The AC signal source 31 generates a sine wave, a square wave, or an arbitrary waveform.
【００２２】以上のように構成された半導体デバイスの
試験装置について、以下にその動作について説明する。
まず、直流計測系２７から直流の電圧等を印加し、被測
定用半導体デバイス２１の直流試験を実施する。次に、
交流信号源３１から交流信号を印加し、被測定用半導体
デバイス２１の交流試験を実施する。The operation of the semiconductor device testing apparatus configured as described above will be described below.
First, a DC voltage or the like is applied from the DC measurement system 27, and a DC test of the semiconductor device to be measured 21 is performed. next,
An alternating current signal is applied from the alternating current signal source 31, and an alternating current test of the semiconductor device for measurement 21 is performed.
【００２３】以上のように本実施例によれば、キャパシ
タンス２８を設けたことにより、直流試験の実施時に、
直流成分が遮断され以降の交流試験用伝送系には影響を
及ぼさず、又キャパシタンス２５を設けたことにより、
交流試験の実施時に、交流成分が遮断され以降の直流試
験用伝送系には影響を及ぼさない。更に、Ｚ３１＝Ｚ０
＝Ｚ１As described above, according to the present embodiment, since the capacitance 28 is provided, when the DC test is performed,
Since the direct current component is cut off, it does not affect the transmission system for alternating current test after that, and by providing the capacitance 25,
When the AC test is performed, the AC component is cut off, and the transmission system for DC test after that is not affected. Furthermore, Z31 = Z0
= Z1
【００２４】[0024]
【外１０】 [Outside 10]
【００２５】Ｚ２という整合条件が成立しているので、
リレーを用いなくとも従来例と同様の試験効果が得られ
る。なお、実施例では並列インピーダンスＺ１Since the matching condition of Z2 is established,
The same test effect as the conventional example can be obtained without using a relay. In the embodiment, the parallel impedance Z1
【００２６】[0026]
【外１１】 [Outside 11]
【００２７】Ｚ２について述べたが、各種の組合せが存
在し、広く合成インピーダンスの場合にも適用できる。Although Z2 has been described, there are various combinations and it can be widely applied to the case of combined impedance.
【００２８】図２は本発明の一実施例における、半導体
デバイスの試験方法の手順である。まず、始めに直流系
の試験を行ない、つぎに交流系の試験を行なう。本発明
の独特の効果として、直流試験と交流試験を同時に実施
することもできる。例えば、交流信号を印加しながら直
流動作点の測定や、直流動作電圧を印加してそのうえに
交流信号を重畳する印加試験ができる。FIG. 2 shows a procedure of a semiconductor device testing method according to an embodiment of the present invention. First, a DC system test is performed first, and then an AC system test is performed. As a unique effect of the present invention, the DC test and the AC test can be simultaneously performed. For example, a DC operating point can be measured while applying an AC signal, or an application test in which a DC operating voltage is applied and an AC signal is superimposed thereon can be performed.
【００２９】以上のように、高集積化と多機能化した被
測定用半導体デバイスで、直流と交流の試験が多くの端
子で必要な場合でも、端子へ接続するリレーを削除し、
試験装置の実装面積とサイズを小さくすることのできる
半導体デバイスの試験方法および試験装置を実現するこ
とができる。As described above, in the highly integrated and multifunctional semiconductor device under test, even if the test of direct current and alternating current is required in many terminals, the relay connected to the terminals is deleted,
It is possible to realize a semiconductor device test method and a test apparatus that can reduce the mounting area and size of the test apparatus.
【００３０】[0030]
【発明の効果】以上のように本発明は、被測定用半導体
デバイスの端子に対し２系統の伝送系を備え、一方の伝
送系は直列インピーダンスＺ１の一端を上記半導体デバ
イスの端子に接続し、上記直列インピーダンスＺ１の他
端に一端を接地したキャパシタンスＣ１の他端と直流信
号伝送路の一端を接続し、他方の伝送系は直列キャパシ
タンスＣ２の一端を上記半導体デバイスの端子に接続
し、上記直列キャパシタンスＣ２の他端に一端を接地し
たインピーダンスＺ２の他端と特性インピーダンスＺ０
の交流信号伝送路の一端を接続し、その交流信号伝送路
の特性インピーダンスＺ０と、インピーダンスＺ１とイ
ンピーダンスＺ２の合成インピーダンスＺ１As described above, the present invention is provided with two transmission systems for the terminals of the semiconductor device to be measured, and one transmission system has one end of the series impedance Z1 connected to the terminals of the semiconductor device, The other end of the capacitance C1 whose one end is grounded is connected to the other end of the series impedance Z1 and one end of the DC signal transmission line, and the other transmission system is such that one end of the series capacitance C2 is connected to the terminal of the semiconductor device. The other end of the impedance Z2 whose one end is grounded to the other end of the capacitance C2 and the characteristic impedance Z0
One end of the AC signal transmission line is connected, and the characteristic impedance Z0 of the AC signal transmission line and the combined impedance Z1 of the impedance Z1 and the impedance Z2.
【００３１】[0031]
【外１２】 [Outside 12]
【００３２】Ｚ２とが等しく（Ｚ０＝Ｚ１Z2 is equal (Z0 = Z1
【００３３】[0033]
【外１３】 [Outside 13]
【００３４】Ｚ２）、上記キャパシタンスＣ１，Ｃ２は
交流信号に対し、充分小さいインピーダンス値をとるよ
うにした構成によるので、端子へ接続するリレーを削除
でき、実装面積とサイズを小さくした直流試験と交流試
験が同時に実施できる優れた半導体デバイスの試験方法
および半導体デバイスの試験装置を提供できる。Z2) Since the capacitances C1 and C2 have a structure in which the impedance value is sufficiently small for an AC signal, the relay connected to the terminal can be eliminated, and the DC test and the AC with the mounting area and size reduced. It is possible to provide an excellent semiconductor device test method and a semiconductor device test apparatus capable of performing tests simultaneously.
【図１】本発明の一実施例における半導体デバイスの試
験方法を実施するための試験装置の回路図FIG. 1 is a circuit diagram of a test apparatus for carrying out a semiconductor device test method according to an embodiment of the present invention.
【図２】図１の回路図を用いた半導体デバイスの試験方
法の手順図FIG. 2 is a procedure diagram of a semiconductor device testing method using the circuit diagram of FIG.
【図３】従来の半導体デバイスの試験方法を実施するた
めの試験装置の回路図FIG. 3 is a circuit diagram of a test apparatus for performing a conventional semiconductor device test method.
２１ 被測定用半導体デバイス ２２ 端子 ２３ 試験装置 ２４ インピーダンス（インピーダンスＺ１） ２５ キャパシタンス（キャパシタンスＣ１） ２６ 直流信号伝送路 ２７ 直流計測系 ２８ キャパシタンス（キャパシタンスＣ２） ２９ インピーダンス（インピーダンスＺ２） ３０ 交流信号伝送路 ３１ 交流信号源 21 Semiconductor device for measurement 22 terminals 23 Test equipment 24 impedance (impedance Z1) 25 Capacitance (Capacitance C1) 26 DC signal transmission path 27 DC measurement system 28 Capacitance (Capacitance C2) 29 Impedance (impedance Z2) 30 AC signal transmission line 31 AC signal source
Claims (3)
系統の伝送系を備え、一方の伝送系は直列インピーダン
スＺ１の一端を前記半導体デバイスの端子に接続し、前
記直列インピーダンスＺ１の他端に一端を接地したキャ
パシタンスＣ１の他端と直流信号伝送路の一端を接続
し、他方の伝送系は直列キャパシタンスＣ２の一端を前
記半導体デバイスの端子に接続し、前記直列キャパシタ
ンスＣ２の他端に一端を接地したインピーダンスＺ２の
他端と特性インピーダンスＺ０の交流信号伝送路の一端
を接続し、その交流信号伝送路の特性インピーダンスＺ
０と、インピーダンスＺ１とインピーダンスＺ２の合成
インピーダンスＺ１ 【外１】 Ｚ２とが等しく（Ｚ０＝Ｚ１ 【外２】 Ｚ２）、前記キャパシタンスＣ１，Ｃ２は交流信号に対
し、充分小さいインピーダンス値をとるようにしたこと
を特徴とする半導体デバイスの試験方法。1. The number of terminals for a semiconductor device under test is 2
A system transmission system is provided, and one transmission system has one end of a series impedance Z1 connected to a terminal of the semiconductor device, the other end of the series impedance Z1 having one end grounded, and the other end of a DC signal transmission line. One end is connected, and the other transmission system connects one end of the series capacitance C2 to the terminal of the semiconductor device, and the other end of the series capacitance C2 is grounded at one end, and the other end of the impedance Z2 and the characteristic impedance Z0 are transmitted as AC signals. Characteristic impedance Z of the AC signal transmission line connecting one end of the line
0, combined impedance Z1 of impedance Z1 and impedance Z2 Z2 is equal (Z0 = Z1 Z2), a method for testing a semiconductor device, wherein the capacitances C1 and C2 are set to have sufficiently small impedance values with respect to an AC signal.
が交流試験であり、その直流試験と交流試験とを同時に
行うことを特徴とする請求項１記載の半導体デバイスの
試験方法。2. The method for testing a semiconductor device according to claim 1, wherein one transmission system is a direct current test and the other transmission system is an alternating current test, and the direct current test and the alternating current test are performed simultaneously.
系統の伝送系を備え、一方の伝送系が前記半導体デバイ
スの端子に一端を接続した直列インピーダンスＺ１と、
その直列インピーダンスＺ１の他端に接続した一端を接
地したキャパシタンスＣ１と、そのキャパシタンスＣ１
と並列に前記直列インピーダンスＺ１の他端に接続した
直流信号伝送路とを少なくとも有し、他方の伝送系が前
記半導体デバイスの端子に一端を接続した直列キャパシ
タンスＣ２と、その直列キャパシタンスＣ２の他端に接
続した一端を接地したインピーダンスＺ２と、そのイン
ピーダンスＺ２と並列に前記直列キャパシタンスＣ２の
他端に接続した特性インピーダンスＺ０の交流信号伝送
路とを少なくとも有し、その交流信号伝送路の特性イン
ピーダンスＺ０と、インピーダンスＺ１とインピーダン
スＺ２の合成インピーダンスＺ１ 【外３】 Ｚ２とが等しく（Ｚ０＝Ｚ１ 【外４】 Ｚ２）、前記キャパシタンスＣ１，Ｃ２は交流信号に対
し、充分小さいインピーダンス値をとるようにしたこと
を特徴とする半導体デバイスの試験装置。3. Two terminals are provided for the terminals of the semiconductor device under test.
A series impedance Z1, one end of which is connected to a terminal of the semiconductor device,
A capacitance C1 whose one end connected to the other end of the series impedance Z1 is grounded, and the capacitance C1
A series capacitance C2 having at least a DC signal transmission line connected in parallel to the other end of the series impedance Z1 and the other transmission system having one end connected to a terminal of the semiconductor device, and the other end of the series capacitance C2. The impedance Z2 having one end grounded and the AC signal transmission line having the characteristic impedance Z0 connected to the other end of the series capacitance C2 in parallel with the impedance Z2, and the characteristic impedance Z0 of the AC signal transmission line are included. And the combined impedance Z1 of the impedance Z1 and the impedance Z2. Z2 is equal (Z0 = Z1 Z2), The semiconductor device testing apparatus characterized in that the capacitances C1 and C2 have sufficiently small impedance values with respect to an AC signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3164331A JP2922020B2 (en) | 1991-07-04 | 1991-07-04 | Semiconductor device test method and semiconductor device test apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3164331A JP2922020B2 (en) | 1991-07-04 | 1991-07-04 | Semiconductor device test method and semiconductor device test apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0511010A true JPH0511010A (en) | 1993-01-19 |
| JP2922020B2 JP2922020B2 (en) | 1999-07-19 |
Family
ID=15791143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3164331A Expired - Fee Related JP2922020B2 (en) | 1991-07-04 | 1991-07-04 | Semiconductor device test method and semiconductor device test apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2922020B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020231363A1 (en) * | 2019-05-16 | 2020-11-19 | Unimak Makina Sanayii Ve Ticaret A.S. | A die casting machine for vitrified products |
-
1991
- 1991-07-04 JP JP3164331A patent/JP2922020B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020231363A1 (en) * | 2019-05-16 | 2020-11-19 | Unimak Makina Sanayii Ve Ticaret A.S. | A die casting machine for vitrified products |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2922020B2 (en) | 1999-07-19 |
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