JPH05109704A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH05109704A JPH05109704A JP26982091A JP26982091A JPH05109704A JP H05109704 A JPH05109704 A JP H05109704A JP 26982091 A JP26982091 A JP 26982091A JP 26982091 A JP26982091 A JP 26982091A JP H05109704 A JPH05109704 A JP H05109704A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- integrated circuit
- semiconductor integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路装置の製
造方法に関し、特に多層配線の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for forming multi-layer wiring.
【０００２】[0002]
【従来の技術】近年半導体集積回路装置の高機能化，高
集積化に伴い配線の多層化が図られてきており、３層ま
たは４層配線構造を有する半導体集積回路装置が製品化
されている。ところが配線の多層化が進むにつれて配線
に起因する不良が多発し、半導体集積回路装置の不良原
因の大半を占めるに至っている。これは段差部における
配線の被覆形状（いわゆるカバレッジ）の悪さに起因し
ていると共に配線材料そのものにも起因している。一般
には下層配線端および配線間における上層配線のカバレ
ッジ不足やスルーホール部における上層配線のカバレッ
ジ不足に起因したエレクトロマイグレーション（以下Ｅ
／Ｍと記す）による断線故障や配線材料と層間絶縁膜の
両者に起因したストレスマイグレーション（以下Ｓ／Ｍ
と記す）による断線故障が良く知られている。2. Description of the Related Art In recent years, wiring has been multi-layered in accordance with higher functionality and higher integration of semiconductor integrated circuit devices, and semiconductor integrated circuit devices having a three-layer or four-layer wiring structure have been commercialized. .. However, as the number of wiring layers increases, defects due to wirings frequently occur, and most of the causes of defects in semiconductor integrated circuit devices are reached. This is due to the poor wiring covering shape (so-called coverage) in the step portion and also to the wiring material itself. Generally, electromigration due to insufficient coverage of the upper layer wiring between the lower layer wiring end and between the wiring and insufficient coverage of the upper layer wiring in the through hole portion (hereinafter referred to as E
/ M) due to disconnection failure and stress migration due to both wiring material and interlayer insulating film (hereinafter referred to as S / M).
Disconnection failure due to
【０００３】図３は従来の多層配線を有する半導体集積
回路装置の製造方法の一例を説明するための断面図であ
る。まず素子が形成されたシリコン基板１の上の第１の
Ｓｉ０2 膜２上にアルミニウム膜を被着し、フォトリソ
グラフィ技術をＲＩＥ法（リアクティブイオンエッチン
グ法）により選択的に１層目アルミニウム配線１２Ａ，
１２Ｂ，１２Ｃを形成する。次にプラズマＣＶＤ法（以
下ＰＣＶＤ法と記す）によりＳｉＯＮ膜（Ｓｉ−Ｏ−Ｎ
系絶縁膜）１３を被着した後塗布焼成法によりＳＯＧ膜
（ｓｐｉｎ ｏｎ ｇｌａｓｓ膜）１４を被着し、更に
ＰＣＶＤ法によりＳｉＯＮ膜１５を被着する。その後フ
ォトリソグラフィ技術とプラズマによる等方的エッチン
グ技術とＰＩＥ法を用い１層目アルミニウム配線１２Ｂ
上にスルーホール１６を形成する。その後全面にアルミ
ニウム膜をスパッタ法により被着したのちフォトリソグ
ラフィ技術とＲＩＥ法を用いて２層目アルミニウム配線
１７を形成することにより２層配線構造を実現してい
た。FIG. 3 is a sectional view for explaining an example of a conventional method for manufacturing a semiconductor integrated circuit device having multi-layer wiring. First, an aluminum film is deposited on the first SiO 2 film 2 on the silicon substrate 1 on which the element is formed, and the first layer aluminum wiring is selectively formed by the photolithography technique by the RIE method (reactive ion etching method). 12A,
12B and 12C are formed. Next, a SiON film (Si-O-N) is formed by a plasma CVD method (hereinafter referred to as PCVD method).
After the system insulating film 13 is deposited, the SOG film (spin on glass film) 14 is deposited by the coating and firing method, and the SiON film 15 is further deposited by the PCVD method. After that, the first layer aluminum wiring 12B is formed by using the photolithography technique, the isotropic etching technique using plasma, and the PIE method.
A through hole 16 is formed above. After that, an aluminum film is deposited on the entire surface by a sputtering method, and then a second layer aluminum wiring 17 is formed by using a photolithography technique and an RIE method to realize a two-layer wiring structure.
【０００４】[0004]
【発明が解決しようとする課題】この従来の多層配線を
有する半導体集積回路装置ではスルーホール部で上層配
線のカバレッジが悪いという問題がある。層間絶縁膜厚
が０．８μｍの場合、１層２層間のスルーホールでのカ
バレッジは４０％程度になるためこの部分に電流の集中
が生じ断線故障の原因になっていた。また、１層２層間
スルーホールの直上に２層３層間スルーホールを形成す
るとカバレッジは２０％しか得られない。このため３層
以上の多層配線を行う際１層２層間のスルーホールの直
上に２層３層間のスルーホールを形成することはカバレ
ッジが悪くなりすぎ物理的な断線，電流の集中による断
線をひき起こすため事実上不可能である。これにより配
線のレイアウト設計に際してスルーホール直上に別層の
スルーホールを設けないよう制約を加えるようになり集
積度の向上を阻害していた。However, this conventional semiconductor integrated circuit device having a multilayer wiring has a problem that the coverage of the upper wiring is poor in the through hole portion. When the interlayer insulating film thickness is 0.8 μm, the coverage in the through holes between the first and second layers is about 40%, so that current concentration occurs in this portion, which causes a disconnection failure. Further, if the two-layer, three-layer through-holes are formed immediately above the one-layer, two-layer through-holes, only 20% coverage is obtained. Therefore, when performing multi-layer wiring of three or more layers, forming a through hole between two layers and three layers directly above a through hole between one layer and two layers leads to poor coverage and physical disconnection and disconnection due to current concentration. It is virtually impossible because it happens. As a result, when designing the layout of the wiring, a constraint is imposed so as not to provide a through hole in a different layer immediately above the through hole, which hinders the improvement of the degree of integration.
【０００５】さらに、従来の半導体集積回路装置では製
造においてＰＣＶＤ法，ＲＩＥ法を用いているが、これ
らは共に真空プロセスとなるためプロセス中でのパーテ
ィクル発生や搬送中でのパーティクル発生を低レベルに
抑えるためには高度の装置設計製造管理能力が要求され
る。このため装置に要するコストは増大と一途どってい
る。Further, in the conventional semiconductor integrated circuit device, the PCVD method and the RIE method are used in manufacturing, but since both of them are vacuum processes, the generation of particles during the process and the generation of particles during the transportation are reduced to a low level. In order to suppress it, a high level of equipment design and manufacturing management capability is required. Therefore, the cost required for the device is increasing.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体集積回路
装置の製造方法は、（１）．半導体基板上のシリコン酸
化膜上にパターニングした金属膜をマスクとして液相成
長法によりシリコン酸化膜を該金属膜を除く部分へ選択
的に形成する工程を有するという特徴を有する。ここで
（２）．前記金属膜が第１の金属膜上に第２の金属膜を
順次形成して成ることができる。この場合（３）．前記
第２の金属膜上に第３の金属膜を形成することにより前
記第１の金属膜と該第３の金属膜と前記第２の金属膜に
よって接続することができる。又、（４）．前記第２の
金属膜を無電解メッキ法によりフォトレジストをマスク
にして選択的に形成することも好ましい。そして
（５）．前記第１と第２の金属膜が金または銀または銅
であることが好ましい。The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises (1). It has a feature of having a step of selectively forming a silicon oxide film on a portion excluding the metal film by liquid phase epitaxy using a patterned metal film on the silicon oxide film on the semiconductor substrate as a mask. Here (2). The metal film may be formed by sequentially forming a second metal film on the first metal film. In this case (3). By forming a third metal film on the second metal film, the first metal film, the third metal film and the second metal film can be connected to each other. Also, (4). It is also preferable that the second metal film is selectively formed by an electroless plating method using a photoresist as a mask. And (5). The first and second metal films are preferably gold, silver or copper.
【０００７】かかる本発明は、金属膜をマスクにして絶
縁膜を液相中で選択的に成長させることにより平坦性の
極めて優れた多層配線を有する半導体集積回路装置を実
現することができる。According to the present invention, a semiconductor integrated circuit device having a multi-layered wiring having an extremely flatness can be realized by selectively growing an insulating film in a liquid phase using a metal film as a mask.
【０００８】[0008]
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ）〜（ｈ）は本発明の第１の実施例を説明
するため工程順に示した半導体チップの断面図である。The present invention will be described below with reference to the drawings. 1A to 1H are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention.
【０００９】まず、図１（ａ）に示すように素子が形成
されたシリコン基板１上に第１のＳｉＯ2 膜２を被着
し、次にスパッタ法を用いチタンタングステン膜３を約
３０ｎｍ被着し、さらにスパッタ法により第１のＡｕ膜
４を約０．８μｍ被着する。次に図１（ｂ）に示すよう
にフォトレジスト５をパターニングした後このフォトレ
ジスト５をマスクにイオンミリング法により第１のＡｕ
膜４およびチタンタングステン膜３を異法的にエッチン
グする。次に図１（ｃ）に示すように第１のＡｕ膜４お
よびチタンタングステン膜３をマスクに液相成長法によ
り第２のＳｉＯ2 膜６を選択的に約０．８μｍ成長させ
る。次に図１（ｄ）に示すようにフォトレジスト５を剥
離する。次に図１（ｅ）に示すように第３のＳｉＯ2 膜
７をＰＣＶＤ法により形成し、フォトレジスト８を塗布
しパターニングを行う。次に図１（ｆ）に示すようにフ
ォトレジスト８をマスクに第３のＳｉＯ2 膜７をＲＩＥ
法により異法的にエッチングした後、無電解メッキ法に
よりＡｕメッキ膜９を形成する。次に図１（ｇ）に示す
ようにフォトレジスト８を剥離した後Ａｕメッキ膜９を
マスクにして液相成長法により第４のＳｉＯ2 膜１０を
選択的に形成する。次に図１（ｈ）に示すようにスパッ
タ法により第２のＡｕ膜１１を被着しフォトリソグラフ
ィ技術によりパターニングを行う。First, as shown in FIG. 1A, a first SiO 2 film 2 is deposited on a silicon substrate 1 on which elements are formed, and then a titanium tungsten film 3 is deposited to a thickness of about 30 nm by a sputtering method. Then, the first Au film 4 is deposited by about 0.8 μm by the sputtering method. Next, as shown in FIG. 1B, the photoresist 5 is patterned, and then the first Au is formed by ion milling using the photoresist 5 as a mask.
The film 4 and the titanium tungsten film 3 are illegally etched. Next, as shown in FIG. 1C, a second SiO 2 film 6 is selectively grown by about 0.8 μm by a liquid phase growth method using the first Au film 4 and the titanium tungsten film 3 as a mask. Next, the photoresist 5 is peeled off as shown in FIG. Next, as shown in FIG. 1E, a third SiO 2 film 7 is formed by PCVD, a photoresist 8 is applied and patterning is performed. Next, as shown in FIG. 1F, the third SiO 2 film 7 is RIEed using the photoresist 8 as a mask.
After the etching is performed by the method described above, the Au plating film 9 is formed by the electroless plating method. Next, as shown in FIG. 1G, the photoresist 8 is peeled off, and then the fourth SiO 2 film 10 is selectively formed by the liquid phase growth method using the Au plating film 9 as a mask. Next, as shown in FIG. 1H, the second Au film 11 is deposited by the sputtering method and patterned by the photolithography technique.
【００１０】図２（ａ）〜（ｇ）は本発明の第２の実施
例を説明するため工程順に示した半導体チップの断面図
である。図２（ａ），（ｂ）は第１の実施例の図１
（ａ），（ｂ）と同じ工程である。本実施例では図２
（ｃ）に示すようにパターニングされた第１のＡｕ膜４
上にフォトレジスト８を塗布する。次に図２（ｄ）に示
すようにフォトレジスト８をパターニングした後無電解
メッキ法によりＡｕメッキ膜９を形成する。次に図２
（ｅ）に示すようにフォトレジスト８を剥離する。次に
図２（ｆ）に示すように液相成長法により第２のＳｉＯ
2 膜６を形成する。次に図２（ｇ）に示すようにスパッ
タ法により第２のＡｕ膜１１を被着しフォトリソグラフ
ィ技術によりパターニングを行う。この実施例では液相
成長によるＳｉＯ2 膜形成が一度で済むため工期の短縮
に効果がある。FIGS. 2A to 2G are sectional views of a semiconductor chip shown in the order of steps for explaining the second embodiment of the present invention. 2 (a) and 2 (b) are the same as FIG. 1 of the first embodiment.
This is the same process as (a) and (b). In this embodiment, FIG.
First Au film 4 patterned as shown in FIG.
A photoresist 8 is applied on top. Next, as shown in FIG. 2D, after patterning the photoresist 8, an Au plating film 9 is formed by electroless plating. Next in FIG.
The photoresist 8 is peeled off as shown in FIG. Next, as shown in FIG. 2 (f), a second SiO 2 is formed by a liquid phase epitaxy method.
2 The film 6 is formed. Next, as shown in FIG. 2G, the second Au film 11 is deposited by the sputtering method and patterned by the photolithography technique. In this embodiment, the SiO 2 film can be formed only once by liquid phase growth, which is effective in shortening the construction period.
【００１１】本実施例で形成する液相成長法によるＳｉ
Ｏ2 膜は平坦性にすぐれている。このため配線Ａｕと同
じ厚さまでＳｉＯ2 膜を形成することでチップ全面の平
坦性を飛躍的に同上させることができる。Si by the liquid phase growth method formed in this embodiment
The O 2 film has excellent flatness. Therefore, the flatness of the entire surface of the chip can be dramatically improved by forming the SiO 2 film to the same thickness as the wiring Au.
【００１２】本実施例では金属配線にＡｕに用いたがＡ
ｇやＣｕでも同様の方法で製造できる。In the present embodiment, Au was used for the metal wiring.
g and Cu can be manufactured by the same method.
【００１３】[0013]
【発明の効果】以上説明したように本発明は半導体基板
上に形成パターニングした金属膜をマスクに液相成長に
よりＳｉＯ2 膜を金属膜と同程度の厚さまで選択的に形
成したことにより、チップ全面の段差を０．３μｍ以下
におさえることができ、平坦性を飛躍的に向上させるこ
とができる。これによりカバレッジの悪い箇所がなくな
り配線の寿命が大きく延びるため、半導体集積回路装置
の信頼性が飛躍的に向上する。また配線材にＡｕ，Ａ
ｇ，Ｃｕを用いることによりＥ／Ｍ，Ｓ／Ｍ耐性が向上
する。そのほかスルーホールを重ね合わせて配置するこ
とが可能となるため集積度の向上を図ることができる。
さらに絶縁膜形成に真空プロセスを用いないため、設備
に要するコストが低減できるという効果も有する。As described above, according to the present invention, the SiO 2 film is selectively formed by liquid phase epitaxy to the same thickness as the metal film by using the patterned metal film formed on the semiconductor substrate as a mask. The step difference on the entire surface can be suppressed to 0.3 μm or less, and the flatness can be dramatically improved. As a result, a portion with poor coverage is eliminated and the life of the wiring is greatly extended, so that the reliability of the semiconductor integrated circuit device is dramatically improved. In addition, the wiring material is Au, A
The use of g and Cu improves the E / M and S / M resistance. In addition, since the through holes can be arranged so as to overlap each other, the degree of integration can be improved.
Further, since the vacuum process is not used for forming the insulating film, there is an effect that the cost required for equipment can be reduced.
【図１】本発明の第１の実施例を説明するための半導体
チップの断面図。FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明するための半導体
チップの断面図。FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
【図３】従来の半導体集積回路装置の製造方法を説明す
るための断面図。FIG. 3 is a sectional view for explaining a conventional method for manufacturing a semiconductor integrated circuit device.
１ シリコン基板 ２ 第１のＳｉＯ2 膜 ３ チタンタングステン膜 ４ 第１のＡｕ膜 ５，８ フォトレジスト膜 ６ 第２のＳｉＯ2 膜 ７ 第３のＳｉＯ2 膜 ９ Ａｕメッキ膜 １０ 第４のＳｉＯ2 膜 １１ 第２のＡｕ膜 １２Ａ，１２Ｂ，１２Ｃ １層目アルミニウム配線 １３，１５ ＳｉＯＮ膜 １４ ＳＯＧ膜 １６ スルーホール １７ ２層目アルミニウム配線1 Silicon Substrate 2 First SiO 2 Film 3 Titanium Tungsten Film 4 First Au Film 5, 8 Photoresist Film 6 Second SiO 2 Film 7 Third SiO 2 Film 9 Au Plating Film 10 Fourth SiO 2 Film 11 Second Au film 12A, 12B, 12C First layer aluminum wiring 13,15 SiON film 14 SOG film 16 Through hole 17 Second layer aluminum wiring
Claims (6)
ーニング形成した金属膜をマスクとして液相成長法によ
りシリコン酸化膜を該金属膜を除く部分へ選択的に形成
する工程を有することを特徴とする半導体集積回路装置
の製造方法。1. A method of selectively forming a silicon oxide film on a portion excluding the metal film by liquid phase epitaxy using a metal film patterned on a silicon oxide film on a semiconductor substrate as a mask. Method for manufacturing semiconductor integrated circuit device.
属膜を順次形成して成ることを特徴とする請求項１に記
載の半導体集積回路装置の製造方法。2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the metal film is formed by sequentially forming a second metal film on the first metal film.
成することにより前記第１の金属膜と該第３の金属膜を
前記第２の金属膜によって接続したことを特徴とする請
求項２に記載の半導体集積回路装置の製造方法。3. A third metal film is formed on the second metal film, whereby the first metal film and the third metal film are connected by the second metal film. The method for manufacturing a semiconductor integrated circuit device according to claim 2.
りフォトレジストをマスクにして選択的に形成すること
を特徴とする請求項２に記載の半導体集積回路装置の製
造方法。4. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the second metal film is selectively formed by a non-electrolytic plating method using a photoresist as a mask.
または銅であることを特徴とする請求項１に記載の半導
体集積回路装置の製造方法。5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first and third metal films are gold, silver, or copper.
であることを特徴とする請求項２に記載の半導体集積回
路装置の製造方法。6. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the second metal film is gold, silver or copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26982091A JPH05109704A (en) | 1991-10-18 | 1991-10-18 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26982091A JPH05109704A (en) | 1991-10-18 | 1991-10-18 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05109704A true JPH05109704A (en) | 1993-04-30 |
Family
ID=17477632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26982091A Pending JPH05109704A (en) | 1991-10-18 | 1991-10-18 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05109704A (en) |
-
1991
- 1991-10-18 JP JP26982091A patent/JPH05109704A/en active Pending
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