JPH05102348A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05102348A
JPH05102348A JP3257895A JP25789591A JPH05102348A JP H05102348 A JPH05102348 A JP H05102348A JP 3257895 A JP3257895 A JP 3257895A JP 25789591 A JP25789591 A JP 25789591A JP H05102348 A JPH05102348 A JP H05102348A
Authority
JP
Japan
Prior art keywords
semiconductor device
substrate
wiring pattern
leads
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3257895A
Other languages
Japanese (ja)
Inventor
Toshiki Nakayama
敏紀 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP3257895A priority Critical patent/JPH05102348A/en
Publication of JPH05102348A publication Critical patent/JPH05102348A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Abstract

PURPOSE:To improve the stability at mounting of a semiconductor device or after mounting by providing a projection on the semiconductor device, and bonding the projection of the semiconductor device with the board having a wiring pattern. CONSTITUTION:In a semiconductor device 1, it is characterized by having at least one projection 22, at the facing side of a board, when mounting the semiconductor device on the board 41.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置および半導
体装置の形状に関し、特にガルウイング状のアウターリ
ードをもつ表面実装型の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and the shape of the semiconductor device, and more particularly to a surface mount type semiconductor device having gull wing-shaped outer leads.

【０００２】[0002]

【従来の技術】従来の半導体装置は、ワイヤボンディン
グを用い、樹脂封止した半導体装置を例にとると、図５
に示すように、半導体装置４は、ダイパッド１１上に搭
載された半導体集積回路１２は、各インナーリード１４
と、導電性細線１３により電気的接続をとり、樹脂２１
によって封止される。その後、半田メッキを行い、アウ
ターリードをフォーミングした後、半導体装置４のアウ
ターリード３１を配線等を施した基板４１上の配線パタ
ーン４２と、半田リフロー等によって接続し基板実装し
ていた。2. Description of the Related Art A conventional semiconductor device is shown in FIG.
As shown in FIG. 1, the semiconductor device 4 includes the semiconductor integrated circuit 12 mounted on the die pad 11 and the inner leads 14
And a conductive thin wire 13 to make an electrical connection, and a resin 21
Sealed by. After that, solder plating is performed to form the outer leads, and then the outer leads 31 of the semiconductor device 4 are connected to the wiring pattern 42 on the substrate 41 on which wiring is provided by solder reflow or the like, and mounted on the substrate.

【０００３】[0003]

【発明が解決しようとする課題】従来の半導体装置を示
す図５において、アウターリード３１は、曲げ部３２、
および曲げ部３３の２箇所を曲げた後、すなわち、フォ
ーミングした後、基板４１上の配線パターン４２に半田
付けするため、アウターリード３１は、かなり長くな
る。そのため、リードコープラナリティー、ベントリー
ド等の、ばらつきを小さくすることは、非常に困難を極
めるものであった。また、近年の半導体装置の大型化、
アウターリードピッチの縮小化は、アウターリード３１
の加工を更に困難にしている。In FIG. 5, which shows a conventional semiconductor device, an outer lead 31 has a bent portion 32,
Since the bent portion 33 is bent at two places, that is, after forming, the solder is soldered to the wiring pattern 42 on the substrate 41, so that the outer lead 31 becomes considerably long. Therefore, it has been extremely difficult to reduce variations in lead coplanarity, bent leads, and the like. In addition, the recent increase in the size of semiconductor devices,
To reduce the outer lead pitch, use the outer lead 31
Processing is becoming more difficult.

【０００４】特に、リードコープラナリティーの悪化
は、基板４１への実装時に、配線パターン４２へ、接続
出来ないアウターリードを発生させることになった。In particular, the deterioration of the lead coplanarity results in the generation of outer leads that cannot be connected to the wiring pattern 42 when mounted on the substrate 41.

【０００５】また、基板４１上に実装した後も、わずか
な外部力により、容易にアウターリード３１が変形し、
アウターリード３１と配線パターン４２の半田付け性が
低下した。Even after mounting on the substrate 41, the outer leads 31 are easily deformed by a slight external force,
The solderability of the outer lead 31 and the wiring pattern 42 deteriorated.

【０００６】本発明は、前述した、リードコープラナリ
ティーの悪化により基板上配線パターンに接続できない
問題、さらに、実装後にアウターリードの変形により半
田付け性が低下する問題を解決するところにある。The present invention is to solve the above-mentioned problem that the lead coplanarity is deteriorated so that the wiring pattern cannot be connected to the wiring pattern on the substrate and that the solderability is deteriorated due to the deformation of the outer lead after mounting.

【０００７】[0007]

【課題を解決するための手段】本発明の半導体装置は、
半導体集積回路と前記半導体集積回路の周囲に配された
リードと、半導体チップとリードを接続する導電性細
線、あるいは非導電性物質上に形成された導電性配線を
有し、これらを樹脂封止、あるいはガラス等により気密
封止された半導体装置において、前記半導体装置を基板
実装する際、前記基板にあい対する面に、少なくとも１
つの凸部を持つことを特徴とする。The semiconductor device of the present invention comprises:
It has a semiconductor integrated circuit, leads arranged around the semiconductor integrated circuit, conductive thin wires connecting the semiconductor chip and the leads, or conductive wiring formed on a non-conductive substance, and these are resin-sealed. In a semiconductor device hermetically sealed with glass or the like, when mounting the semiconductor device on a substrate, at least 1
It is characterized by having two convex portions.

【０００８】[0008]

【作用】本発明を実施することにより、リードコープラ
ナリティーの品質の多少悪い半導体装置でも、確実に基
板上の配線パターンに、全アウターリードとも半田付が
可能になり、また、半導体素子を基板に実装した後も、
外部力によりアウターリードが変形して、半田付け性を
低下させることがなくなる。By implementing the present invention, it becomes possible to reliably solder all the outer leads to the wiring pattern on the substrate even in a semiconductor device having a somewhat poor quality of lead coplanarity. Even after implementing
The outer lead will not be deformed by the external force, and the solderability will not be deteriorated.

【０００９】[0009]

【実施例】図１は、ワイヤボンディングを用い、樹脂封
止した半導体装置において、本発明を実施した場合の半
導体装置の断面図であり、以下その詳細を説明してい
く。図１において、半導体集積回路１２は、ダイパッド
１１上に搭載されており、インナーリード１４と導電性
細線１３により、接続されている。樹脂２１は、ダイパ
ッド１１、半導体集積回路１２、導電性細線１３、イン
ナーリード１４を封止しており、この半導体装置１は突
起部２２を持っている。アウターリード３１は、半田５
１により基板４１上の配線パターン４２と接続されてい
る。また、突起部２２は接着剤５２により基板４１に接
続されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a semiconductor device in which the present invention is implemented in a resin-sealed semiconductor device using wire bonding, and the details will be described below. In FIG. 1, the semiconductor integrated circuit 12 is mounted on the die pad 11 and is connected to the inner leads 14 by the conductive thin wires 13. The resin 21 seals the die pad 11, the semiconductor integrated circuit 12, the conductive thin wires 13, and the inner leads 14, and the semiconductor device 1 has a protrusion 22. The outer leads 31 are solder 5
1 connects to the wiring pattern 42 on the substrate 41. The protrusion 22 is connected to the substrate 41 with an adhesive 52.

【００１０】この様な構成において、突起部２２と基板
４１が接着し固定されたことにより、半導体装置２を基
板へ実装した後に外部力がかかった際、外部力は従来の
ようにアウターリード３１と半田５１へ集中することが
なくなり、アウターリード３１の変形や半田付け性が低
下することはなくなる。In such a structure, the protrusion 22 and the substrate 41 are adhered and fixed to each other, so that when an external force is applied after the semiconductor device 2 is mounted on the substrate, the external force is the same as in the conventional case. Therefore, the outer lead 31 will not be deformed and the solderability will not be reduced.

【００１１】図２は、リードコープラナリティーの悪い
半導体装置２を平面板４３へ置いた模式図である。この
時、全てのアウターリード３１が平面板５に接すること
なく、平面板から浮く、浮きアウターリードリード３５
が存在してしまう。またこの時、半導体装置２の突起部
２２は、平面板４３に接していないように設計してあ
る。FIG. 2 is a schematic diagram in which the semiconductor device 2 having poor lead coplanarity is placed on the plane plate 43. At this time, all the outer leads 31 do not come into contact with the plane plate 5 and float from the plane plate, and the floating outer lead leads 35
Will exist. At this time, the projection 22 of the semiconductor device 2 is designed so as not to contact the flat plate 43.

【００１２】図３は、半導体装置２を基板４１へ、実装
したときの図である。FIG. 3 is a diagram when the semiconductor device 2 is mounted on the substrate 41.

【００１３】半導体装置２の突起部２２は、平面板４３
へ置いたときは、平面板４３に接していないが、半導体
装置２を基板４１へ実装時に、突起部２２が基板４１へ
接するように上部より外部力を加え、突起部２２を基板
４１へ接着するとともに、アウターリード３１を配線パ
ターン４２と半田５１により、接続することにより、ア
ウターリード３５は、アウターリード３１とともに配線
パターン４２へ押しつけられる。よって、リードコープ
ラナリティが悪く、浮きアウターリード３５がを発生し
ている半導体装置２においても、浮きアウターリード３
５が、配線パターン４２へ接続可能である。The projection 22 of the semiconductor device 2 has a flat plate 43.
However, when the semiconductor device 2 is mounted on the substrate 41, an external force is applied from above so that the protrusion 22 contacts the substrate 41, and the protrusion 22 is bonded to the substrate 41. In addition, by connecting the outer lead 31 to the wiring pattern 42 by the solder 51, the outer lead 35 is pressed against the wiring pattern 42 together with the outer lead 31. Therefore, even in the semiconductor device 2 in which the lead coplanarity is poor and the floating outer leads 35 are generated, the floating outer leads 3 are
5 can be connected to the wiring pattern 42.

【００１４】図４は、図１と異なる突起部を持つ半導体
装置の一例である。図４の突起部２３は、基板への位置
合わせも考慮し、基板挿入形式をとっている。複数ある
突起部２２を全て、基板４１へ貫通する方法である。突
起部２２は、半導体装置３の実装時の高さ方向の安定性
を確保するために、段突きになっている。また、複数あ
る突起部の内の特定の突起部のみを基板４１へ貫通する
長さにし、半導体装置３が異なる方向には、挿入できな
い用にする方法もある。FIG. 4 shows an example of a semiconductor device having a protrusion different from that shown in FIG. The protrusion 23 of FIG. 4 is of a board insertion type in consideration of alignment with the board. This is a method of penetrating all the plurality of protrusions 22 into the substrate 41. The protrusion 22 is a step protrusion in order to ensure stability in the height direction when the semiconductor device 3 is mounted. In addition, there is also a method in which only a specific protrusion of a plurality of protrusions is penetrated into the substrate 41 so that the semiconductor device 3 cannot be inserted in different directions.

【００１５】本実施例では、突起部２２、２３を、樹脂
成形により一体成形したものを用いているが、本発明
は、これに限定されるものではない。すなわち、別に成
形された突起部を用い、半導体装置に接着する方法、あ
るいは、挿入する方法等がある。In this embodiment, the protrusions 22 and 23 are integrally formed by resin molding, but the present invention is not limited to this. That is, there is a method of adhering to a semiconductor device or a method of inserting it by using a separately formed protrusion.

【００１６】また、本実施例は樹脂封止型半導体装置を
用いているが、本発明は、これに限定されるものではな
い。すなわち、ガラス等を用いた気密封止型半導体装置
等でも良い。Although this embodiment uses a resin-sealed semiconductor device, the present invention is not limited to this. That is, a hermetically sealed semiconductor device using glass or the like may be used.

【００１７】[0017]

【発明の効果】以上のように、本発明によれば、半導体
装置に突起部を設け、基板に固定されたことにより、リ
ードコープラナリティーの品質の多少悪く、浮いている
アウターリードがある半導体装置でも、確実に基板上の
配線パターンに、全アウターリードとも半田付が可能に
なり、また、半導体素子を基板に実装した後も、外部力
によりアウターリードが変形して、半田付け性を低下さ
せることがなくなる。As described above, according to the present invention, since the semiconductor device is provided with the projecting portion and is fixed to the substrate, the quality of the lead coplanarity is somewhat poor and the semiconductor device has the floating outer lead. Even in the device, all outer leads can be reliably soldered to the wiring pattern on the board, and even after the semiconductor element is mounted on the board, the outer leads are deformed by external force and solderability deteriorates. There is nothing to do.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明実施例の断面図。FIG. 1 is a sectional view of an embodiment of the present invention.

【図２】本発明実施例の模式図。FIG. 2 is a schematic diagram of an example of the present invention.

【図３】本発明実施例を基板実装した模式図。FIG. 3 is a schematic view of an embodiment of the present invention mounted on a substrate.

【図４】本発明実施例の断面図。FIG. 4 is a sectional view of an embodiment of the present invention.

【図５】従来の半導体装置の断面図。FIG. 5 is a sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１、２、３ 半導体装置 １１ ダイパッド １２ 半導体集積回路 １３ 導電性細線 １４ インナーリード ２１ 樹脂 ２２、２３ 突起部 ３１ アウターリード ３２、３３ 曲げ部 ３５ 浮きアウターリード ４１ 基板 ４２ 配線パターン ４３ 平面板 ５１ 半田 ５２ 接着剤 1, 2 and 3 Semiconductor device 11 Die pad 12 Semiconductor integrated circuit 13 Conductive thin wire 14 Inner lead 21 Resin 22, 23 Projection portion 31 Outer lead 32, 33 Bent portion 35 Floating outer lead 41 Substrate 42 Wiring pattern 43 Plane plate 51 Solder 52 adhesive

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体集積回路と半導体集積回路の周囲
に配されたインナーリードと、半導体集積回路とインナ
ーリードを接続する導電性細線、あるいは非導電性物質
上に形成された導電性配線を有し、これらを樹脂封止、
あるいはガラス等により封止された半導体装置におい
て、前記半導体装置の実装する基板にあい対する面に、
少なくとも１つの突起部を持つことを特徴とする半導体
装置。1. A semiconductor integrated circuit, an inner lead arranged around the semiconductor integrated circuit, a conductive thin wire connecting the semiconductor integrated circuit and the inner lead, or a conductive wiring formed on a non-conductive material. And seal them with resin,
Alternatively, in a semiconductor device sealed with glass or the like, on the surface facing the substrate on which the semiconductor device is mounted,
A semiconductor device having at least one protrusion.
JP3257895A 1991-10-04 1991-10-04 Semiconductor device Pending JPH05102348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3257895A JPH05102348A (en) 1991-10-04 1991-10-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3257895A JPH05102348A (en) 1991-10-04 1991-10-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05102348A true JPH05102348A (en) 1993-04-23

Family

ID=17312684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3257895A Pending JPH05102348A (en) 1991-10-04 1991-10-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05102348A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5986337A (en) * 1997-11-17 1999-11-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor element module and semiconductor device which prevents short circuiting

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5986337A (en) * 1997-11-17 1999-11-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor element module and semiconductor device which prevents short circuiting

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