JPH0499372A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0499372A JPH0499372A JP2217512A JP21751290A JPH0499372A JP H0499372 A JPH0499372 A JP H0499372A JP 2217512 A JP2217512 A JP 2217512A JP 21751290 A JP21751290 A JP 21751290A JP H0499372 A JPH0499372 A JP H0499372A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductor
- semiconductor substrate
- dielectric layer
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000004020 conductor Substances 0.000 claims abstract description 42
- 239000003990 capacitor Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 6
- 238000000206 photolithography Methods 0.000 abstract description 5
- 230000002411 adverse Effects 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229920005591 polysilicon Polymers 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 61
- 238000000034 method Methods 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要］
半導体装置及びその製造方法に係り、特にダイナミック
・ランダム・アクセス・メモリ及びその製造方法に関し
。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a dynamic random access memory and a manufacturing method thereof.
セルが微細化されても大きな電荷蓄積容量を持つ構造及
びその実現方法の提供を目的とし。The purpose is to provide a structure that has a large charge storage capacity even when cells are miniaturized, and a method for realizing it.
半導体基板に下面を密着する導電体柱と、該導電体柱の
側面及び上面に密着する誘電体層と、該誘電体層に密着
する導電体層とを有し、該導電体柱と該誘電体層と該導
電体層は蓄積容量部をなす半導体装置により構成する。It has a conductive column whose lower surface is in close contact with the semiconductor substrate, a dielectric layer which is in close contact with the side and top surfaces of the conductive column, and a conductive layer which is in close contact with the dielectric layer, and the conductive column and the dielectric layer are in close contact with the dielectric layer. The body layer and the conductor layer are constituted by a semiconductor device forming a storage capacitor section.
また、半導体基板上に絶縁層を形成する工程と該絶縁層
に該半導体基板を露出するコンタクトホールを形成する
工程と、該コンタクトホールを導電体で埋込んだ後、前
記絶縁層を選択的にエツチングして除去し、前記半導体
基板上に突き出る導電体柱を形成する工程と、該導電体
柱の側面及び上面にＦｐ、を体層を形成する工程と、該
誘電体層上に導電体層を形成する工程とを有し、該導電
体柱と該誘電体層と該導電体層が蓄積容量部となる半導
体装置の製造方法により構成する。The method also includes a step of forming an insulating layer on the semiconductor substrate, a step of forming a contact hole in the insulating layer to expose the semiconductor substrate, and a step of filling the contact hole with a conductor, and then selectively removing the insulating layer. a process of etching and removal to form a conductor column protruding onto the semiconductor substrate; a process of forming a Fp body layer on the side and top surfaces of the conductor column; and a process of forming a conductor layer on the dielectric layer. A method for manufacturing a semiconductor device in which the conductive pillar, the dielectric layer, and the conductive layer form a storage capacitor section is provided.
本発明は半導体装置及びその製造方法に係り特にダイナ
ミック・ランダム・アクセス・メモリ（ＤＲＡＭ）及び
その製造方法に関する。The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a dynamic random access memory (DRAM) and a method of manufacturing the same.
近年、半導体装１においては高集積化が進められ、メモ
リセルの微細化が要求されている。In recent years, the semiconductor device 1 has become highly integrated, and there is a demand for miniaturization of memory cells.
ＤＲＡＭのメモリセルの微細化に伴い、電荷を蓄積する
容量も小さくなるが、できるだけ基板の占有面積は小さ
（して、かつ電荷蓄積容量を太きくする工夫が種々なさ
れている。As DRAM memory cells become smaller, the capacity for storing charges also decreases, and various efforts are being made to minimize the area occupied by the substrate (and increase the size of the charge storage capacity).
〔従来の技術］
従来の半導体記憶装置においては７大別して二通りの構
造がある。一つはスタック型セルであり他の一つはトレ
ンチ型セルである。[Prior Art] Conventional semiconductor memory devices are classified into seven types, and there are two types of structures. One is a stack type cell and the other is a trench type cell.
第３図はスタック型セルの断面図であり、１は拡散層１
ａを含む半導体基板、２はゲート酸化膜。FIG. 3 is a cross-sectional view of a stacked cell, and 1 is a diffusion layer 1.
2 is a semiconductor substrate including a, and 2 is a gate oxide film.
３はゲート電極、４．８は絶縁層、９はＡＩ配線。3 is a gate electrode, 4.8 is an insulating layer, and 9 is an AI wiring.
ＩＩ、 １２はキャパシタ電極、 １３はキャパシタ絶
縁膜を表す。II, 12 represents a capacitor electrode, and 13 represents a capacitor insulating film.
スタック型セルは、容量をかせぐためにトランスファー
ゲート（ゲート電極３）の段差を利用し。Stacked cells use the step difference in the transfer gate (gate electrode 3) to increase capacitance.
キャパシタ電ｉｌｌ １２とキャパシタ絶縁膜１３との
接触面積を広げているが、容量の大幅な増加は望めない
。Although the contact area between the capacitor electric field 12 and the capacitor insulating film 13 is increased, a significant increase in capacitance cannot be expected.
第４図はトレンチ型セルの断面図であり、符号は第３図
と共通であり、さらに、 １４．１５はキャパシタ電極
１１６はキャパシタ絶縁膜を表す。FIG. 4 is a cross-sectional view of a trench type cell, and the reference numerals are the same as those in FIG.
トレンチ型セルでは、キャパシタ電極１４．１５とキャ
パシタ絶縁膜１６との接触面積を広げるために半導体基
板１を深くエツチングするが、その際多数の格子欠陥や
界面準位が発生し、リフレッシュ特性へ悪影響を及ぼす
。In a trench type cell, the semiconductor substrate 1 is deeply etched to widen the contact area between the capacitor electrodes 14, 15 and the capacitor insulating film 16, but this creates a large number of lattice defects and interface states, which adversely affects refresh characteristics. effect.
本発明は、格子欠陥や界面準位の発生をなくしかつ容量
の大幅な増加をもたらすＤＲＡＭのセル構造、及びその
製造方法を提供することを目的とする。An object of the present invention is to provide a DRAM cell structure that eliminates the occurrence of lattice defects and interface states and provides a significant increase in capacity, and a method for manufacturing the same.
〔課題を解決するための手段］
第１図は本発明の半導体装置の断面図、第２図（ａ）〜
（ｉ）は実施例を説明するための工程順断面図を示し、
１は半導体基板、 ｌａは拡散層、２はゲート酸化膜、
３はゲート電極、４は絶縁膜、５は導電体柱でキャパシ
タ電極、 ５ａは埋込み層、６は誘電体層、７は導電体
層でキャパシタ電極、８は絶縁層、９はＡ１配線、 １
０は保護層を表す。[Means for Solving the Problems] FIG. 1 is a cross-sectional view of a semiconductor device of the present invention, and FIGS.
(i) shows a step-by-step sectional view for explaining the example,
1 is a semiconductor substrate, la is a diffusion layer, 2 is a gate oxide film,
3 is a gate electrode, 4 is an insulating film, 5 is a conductor pillar and is a capacitor electrode, 5a is a buried layer, 6 is a dielectric layer, 7 is a conductor layer and is a capacitor electrode, 8 is an insulating layer, 9 is an A1 wiring, 1
0 represents a protective layer.
上記課題は、半導体基板１に下面を密着する導電体柱５
と、該導電体柱５の側面及び上面に密着する誘電体層６
と、該誘電体層６に密着する導電体層７とを存し、該導
電体柱５と該誘電体層６と該導電体層７は蓄積容量部を
なす半導体装置によって解決される。The above problem is solved by the conductor pillar 5 whose lower surface is in close contact with the semiconductor substrate 1.
and a dielectric layer 6 that is in close contact with the side and top surfaces of the conductor pillar 5.
and a conductor layer 7 that is in close contact with the dielectric layer 6, and the conductor column 5, the dielectric layer 6, and the conductor layer 7 form a storage capacitor section.
また、半導体基板１上に絶縁層４を形成する工程と、該
絶縁層４に該半導体基板ｌを露出するコンタクトホール
を形成する工程と、該コンタクトホールを導電体で埋込
んだ後、前記絶縁層４を選択的にエツチングして除去し
、前記半導体基板１上に突き出る導電体柱５を形成する
工程と、該導電体柱５の側面及び上面に誘電体層６を形
成する工程と１該誘電体層６上に導電体層７を形成する
工程とを有し、該導電体柱５と該誘電体層６と該導電体
層７が蓄積容量部となる半導体装置の製造方法によって
解決される。Further, the process includes a step of forming an insulating layer 4 on the semiconductor substrate 1, a step of forming a contact hole exposing the semiconductor substrate l in the insulating layer 4, and a step of filling the contact hole with a conductor, and then filling the insulating layer 4 with a conductor. A step of selectively etching and removing the layer 4 to form a conductor column 5 protruding above the semiconductor substrate 1; and a step of forming a dielectric layer 6 on the side and top surfaces of the conductor column 5. The present invention is solved by a method for manufacturing a semiconductor device, which includes a step of forming a conductor layer 7 on a dielectric layer 6, and in which the conductor pillar 5, the dielectric layer 6, and the conductor layer 7 form a storage capacitor section. Ru.
本発明では第１図に示すように半導体基板１上に突き出
る導電体柱５の側面と上面を利用して。In the present invention, as shown in FIG. 1, the side and top surfaces of conductor pillars 5 protruding above semiconductor substrate 1 are utilized.
誘電体層６及び導電体層７を形成し、キャパシタを構成
する。従って、導電体柱５の高さを高く形成することに
よりキャパシタ電極の面積を広げ。A dielectric layer 6 and a conductor layer 7 are formed to constitute a capacitor. Therefore, by increasing the height of the conductor pillars 5, the area of the capacitor electrode can be increased.
キャパシタ容量の増加を図ることができる。It is possible to increase the capacitor capacity.
この構造はトレンチ形成の場合と違って半導体基板ｌに
格子欠陥を生したり界面準位を生したりすることがない
から、リフレッシュ特性に悪影響を及ぼすことがない。Unlike the case of trench formation, this structure does not create lattice defects or interface states in the semiconductor substrate l, so it does not adversely affect refresh characteristics.
〔実施例］
以下、第２図（ａ）〜（ｉ）を参照しながら１本発明の
実施例について説明する。[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 2(a) to (i).
第２図（ａ）参照
通常の方法により、半導体基板にＭＯＳＦＥＴを形成す
る。即ち、半導体基板１に通常の方法により、ゲート酸
化膜２．ゲート電極３．拡散層１ａを形成する。半導体
基板１は１例えばＰ型Ｓｔ基板にＮ型拡散層を形成した
ものである。Ｎ型Ｓｉ基板にＰ型拡散層を形成したもの
でもよい。Referring to FIG. 2(a), a MOSFET is formed on a semiconductor substrate by a conventional method. That is, a gate oxide film 2. is formed on a semiconductor substrate 1 by a conventional method. Gate electrode 3. A diffusion layer 1a is formed. The semiconductor substrate 1 is, for example, a P-type St substrate on which an N-type diffusion layer is formed. A P-type diffusion layer may be formed on an N-type Si substrate.
ゲート電極３の高さは２例えば０．３μｍである。The height of the gate electrode 3 is, for example, 0.3 μm.
第２図（ｂ）参照
全面に絶縁層４として、ＣＶＤ法により厚さ０．５μｍ
のＳｉＯ□膜を形成し９その後通常のフォトリソグラフ
工程によりレジストにキャパシタ電極部、ビット線コン
タクト部の窓開きを行い。Refer to Fig. 2(b) An insulating layer 4 is formed on the entire surface with a thickness of 0.5 μm by CVD method.
A SiO□ film is formed, and then a window for the capacitor electrode part and the bit line contact part is opened in the resist by a normal photolithography process.
異方性エツチングにより窓開き部の５ｉｎ２を除去し、
半導体基板ｌを露出するのコンタクトホールを形成する
。その後、レジストを除去する。5in2 of the window opening was removed by anisotropic etching,
A contact hole is formed to expose the semiconductor substrate l. After that, the resist is removed.
第２図（ｃ）参照 ＣＶＤ法により、コンタクトホールを導電体。See Figure 2(c) The contact hole is made into a conductor using the CVD method.
例えばポυＳｉで完全に埋込み、絶縁層４の上まで覆う
ようにし、ポリＳｉの抵抗を下げるため。For example, it is completely buried with polySi to cover the top of the insulating layer 4 to lower the resistance of polySi.
りん（Ｐ゛）を熱拡散させる。Heat diffuses phosphorus (P゛).
第２図（ｄ）参照
異方性エツチングにより、ポリＳｉを全面エツチングす
る。すると、ポリＳｉはコンタクトホール内にのみ残る
。これにより、キャパシタ電極部に導電体柱５．ビット
線コンタクト部に埋込み層５ａが形成される。The entire surface of the poly-Si is etched by anisotropic etching as shown in FIG. 2(d). Then, poly-Si remains only in the contact hole. As a result, the conductor pillar 5. A buried layer 5a is formed in the bit line contact portion.
第２図（ｅ）参照
異方性エンチングにより、絶縁層４（７）ＳｉＯ□を選
択的にエツチングする。エツチング量は、ゲート電極３
の上面が現れるくらいまでとする。Referring to FIG. 2(e), the insulating layer 4 (7) SiO□ is selectively etched by anisotropic etching. The etching amount is the gate electrode 3
until the top of the surface is visible.
第２図（ｆ）参照
キャパシタ絶縁膜として熱酸化により５ｉｎ２を形成し
、導電体柱５と埋込み層５ａの表面に厚さ約１００人の
誘電体層６を形成する。Referring to FIG. 2(f), a capacitor insulating film having a thickness of 5 in 2 is formed by thermal oxidation, and a dielectric layer 6 having a thickness of about 100 mm is formed on the surfaces of the conductor pillars 5 and the buried layer 5a.
その後２ フォトリソグラフ工程によりビット線コンタ
クト部に窓開けを行い、異方性エツチングにより埋込み
層５ａ上面のＳｉＯ□を除去する。After that, a window is opened in the bit line contact portion by a 2 photolithography process, and SiO□ on the upper surface of the buried layer 5a is removed by anisotropic etching.
第２図（ｇ）参照
キャパシタ電極として全面にポリＳｉをＣＶＤ法により
成長させ、厚さ３０ｏｏλ程度の導電体層７を形成する
。Refer to FIG. 2(g) As a capacitor electrode, poly-Si is grown on the entire surface by the CVD method to form a conductive layer 7 having a thickness of about 3000λ.
その後、フォトリソグラフ工程によりビット線コンタク
ト部に窓開けを行い、異方性エツチングによりポリＳｉ
を除去する。After that, a window is opened in the bit line contact area using a photolithography process, and poly-Si is etched using anisotropic etching.
remove.
第２図（ｈ）参照 全面にＰＳＧを成長させ、絶縁層８を形成する。See Figure 2 (h) PSG is grown on the entire surface to form an insulating layer 8.
その後、フォトリソグラフ工程によりビット線コンタク
ト部に窓開けを行い、ＰＳＧをエツチングして除去する
。Thereafter, a window is formed in the bit line contact portion by a photolithography process, and the PSG is etched and removed.
第２図（ｉ）参照
ビット線用配線材としてＰＶＤ法によりＡＩを成長させ
２それをパターニングしてＡＩ配線９を形成し、その上
に保護膜１０としてＰＳＧ、ＳｉＮ等をＣＶＤ法により
成長させる。Refer to FIG. 2(i) As a wiring material for a bit line, AI is grown by the PVD method 2 It is patterned to form an AI wiring 9, and PSG, SiN, etc. is grown on it as a protective film 10 by a CVD method. .
かくして、導電体柱５．誘電体層６．導電体層７を蓄積
容量部とするＤＲＡＭが実現する。Thus, the conductor column 5. Dielectric layer 6. A DRAM in which the conductor layer 7 serves as a storage capacitor section is realized.
誘電体層６の材料は５ｉｎ２に替えてそれより誘電率の
高いＳｉＮを用いてもよい。As the material of the dielectric layer 6, SiN having a higher dielectric constant may be used instead of 5in2.
なお、導電体層７は導電体柱５の上のみに誘電体層６を
介して形成すれば蓄積容量部としての機能を果たすこと
ができるが５表面の凹凸をなるべく小さくする目的で全
面に形成している。Note that if the conductor layer 7 is formed only on the conductor column 5 via the dielectric layer 6, it can function as a storage capacitor section, but it may be formed over the entire surface in order to minimize the unevenness of the surface of the conductor column 5. are doing.
以上説明したように９本発明によれば、トレンチ型で問
題となるリフレッシュ特性への悪影響のない、かつキャ
パシタ容量の大きいＤＲＡＭを提供することができる。As described above, according to the present invention, it is possible to provide a DRAM that does not have an adverse effect on the refresh characteristics, which is a problem with the trench type, and has a large capacitor capacity.
本発明はＤＲＡＭの高密度化に寄与するところが大きい
。The present invention greatly contributes to increasing the density of DRAM.
第１図は本発明の半導体装置の断面図
第２図（ａ）〜（ｉ）は実施例を説明するための工程順
断面図。
第３図はスタック型セルの断面図
第４図はトレンチ型セルの断面図
である。
図において。
ｌは半導体基板。
１ａは拡散層。
２はゲート酸化膜。
３はゲート電極。
４は絶縁層であってＳｉＯ□
５は導電体柱であってキャパシタ電極。
５ａは埋込み層。
６は誘電体層。
７は導電体層であってキャパシタ電極。
８は絶縁層であってＰＳＧ。
９はＡＩ配線。
１０は保護層。
１１、１２．１４．１５はキャパシタ電極。
１３、１６はキャパシタ絶縁膜
慕 １ 図
更＃イ列Σ啄明１３たｈの１稈）ｌ頃断面図射２図（ブ
の１）
実務例！説明Ｔ：５月澱の工打順断面図案２配（’ｆｉ
ｔ’）２）
Ｘり・ソフ型セルの断面図
佑３図
第４図FIG. 1 is a cross-sectional view of a semiconductor device of the present invention. FIGS. 2(a) to (i) are cross-sectional views in the order of steps for explaining an embodiment. FIG. 3 is a sectional view of a stack type cell, and FIG. 4 is a sectional view of a trench type cell. In fig. l is a semiconductor substrate. 1a is a diffusion layer. 2 is the gate oxide film. 3 is the gate electrode. 4 is an insulating layer, SiO□ 5 is a conductor column, and is a capacitor electrode. 5a is a buried layer. 6 is a dielectric layer. 7 is a conductor layer, which is a capacitor electrode. 8 is an insulating layer, which is PSG. 9 is AI wiring. 10 is a protective layer. 11, 12, 14, and 15 are capacitor electrodes. 13 and 16 are capacitor insulating films. Explanation T: May lees hammering order cross-sectional design 2 layouts ('fi
t') 2) Cross-sectional view of X-ri/soft type cell Figure 3 Figure 4
Claims (1)
）と、該導電体柱（５）の側面及び上面に密着する誘電
体層（６）と、該誘電体層（６）に密着する導電体層（
７）とを有し、 該導電体柱（５）と該誘電体層（６）と該導電体層（７
）は蓄積容量部をなすことを特徴とする半導体装置。 〔２〕半導体基板（１）上に絶縁層（４）を形成する工
程と、 該絶縁層（４）に該半導体基板（１）を露出するコンタ
クトホールを形成する工程と、 該コンタクトホールを導電体で埋込んだ後、前記絶縁層
（４）を選択的にエッチングして除去し、前記半導体基
板（１）上に突き出る導電体柱（５）を形成する工程と
、 該導電体柱（５）の側面及び上面に誘電体層（６）を形
成する工程と、 該誘電体層（６）上に導電体層（７）を形成する工程と
を有し、 該導電体柱（５）と該誘電体層（６）と該導電体層（７
）が蓄積容量部となることを特徴とする半導体装置の製
造方法。[Scope of Claims] [1] Conductor pillar (5) whose lower surface is in close contact with the semiconductor substrate (1)
), a dielectric layer (6) in close contact with the side and top surfaces of the conductive pillar (5), and a conductive layer (6) in close contact with the dielectric layer (6).
7), the conductor column (5), the dielectric layer (6), and the conductor layer (7).
) is a semiconductor device characterized by forming a storage capacitor section. [2] A step of forming an insulating layer (4) on the semiconductor substrate (1), a step of forming a contact hole exposing the semiconductor substrate (1) in the insulating layer (4), and a step of making the contact hole conductive. a step of selectively etching and removing the insulating layer (4) to form a conductive column (5) protruding above the semiconductor substrate (1); ) a step of forming a dielectric layer (6) on the side and top surfaces of the conductor column (5), and a step of forming a conductor layer (7) on the dielectric layer (6); The dielectric layer (6) and the conductor layer (7)
) is a storage capacitor portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2217512A JPH0499372A (en) | 1990-08-17 | 1990-08-17 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2217512A JPH0499372A (en) | 1990-08-17 | 1990-08-17 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0499372A true JPH0499372A (en) | 1992-03-31 |
Family
ID=16705394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2217512A Pending JPH0499372A (en) | 1990-08-17 | 1990-08-17 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0499372A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001003166A1 (en) * | 1999-06-29 | 2001-01-11 | Infineon Technologies Ag | Method for producing an electrode |
| US7579553B2 (en) * | 2000-07-27 | 2009-08-25 | Fujitsu Limited | Front-and-back electrically conductive substrate |
-
1990
- 1990-08-17 JP JP2217512A patent/JPH0499372A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001003166A1 (en) * | 1999-06-29 | 2001-01-11 | Infineon Technologies Ag | Method for producing an electrode |
| US7579553B2 (en) * | 2000-07-27 | 2009-08-25 | Fujitsu Limited | Front-and-back electrically conductive substrate |
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