JPH0498850A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0498850A JPH0498850A JP21615590A JP21615590A JPH0498850A JP H0498850 A JPH0498850 A JP H0498850A JP 21615590 A JP21615590 A JP 21615590A JP 21615590 A JP21615590 A JP 21615590A JP H0498850 A JPH0498850 A JP H0498850A
- Authority
- JP
- Japan
- Prior art keywords
- concentration
- isolation region
- element isolation
- impurity
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 150000004767 nitrides Chemical class 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
Landscapes
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体装置の素子分離
領域の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of an element isolation region of a semiconductor device.
従来の半導体装置は、第2図に示す様に、N型もしくは
P型トランジスタ形成領域の素子分離領域下は、半導体
基板に比べ、半導体基板と同型の不純物濃度が全て濃か
った。In the conventional semiconductor device, as shown in FIG. 2, the concentration of impurities of the same type as the semiconductor substrate is higher than that of the semiconductor substrate under the element isolation region of the N-type or P-type transistor formation region.
この従来の半導体装置は素子分離領域下の全域の不純物
濃度が全て濃く、第2図に示すようにトランジスタを形
成する、基板と逆型の不純物層4と素子分離領域下の基
板と同型の不純物層3の濃度の差が大きい為、接合面の
空乏層の幅が狭くなり、寄生容量が大きくなる。この為
半導体装置の動作速度の低下をもたらしていた。In this conventional semiconductor device, the impurity concentration in the entire area under the isolation region is high, and as shown in FIG. Since the difference in the concentration of layer 3 is large, the width of the depletion layer at the junction surface becomes narrow, and the parasitic capacitance becomes large. This has resulted in a reduction in the operating speed of the semiconductor device.
本発明の目的は、トランジスタを形成する基板と逆型の
不純物層と素子分離領域下でトランジスタを形成する不
純物層との接合面の濃度差を小さくし、空乏層を広くし
、その結果寄生容量を小さくし、半導体装置の動作速度
を速くできる半導体装置を提供することにある。An object of the present invention is to reduce the concentration difference at the junction surface between the impurity layer of the opposite type to the substrate forming the transistor and the impurity layer forming the transistor under the element isolation region, widening the depletion layer, and thereby reducing the parasitic capacitance. An object of the present invention is to provide a semiconductor device that can reduce the size of the semiconductor device and increase the operating speed of the semiconductor device.
本発明の半導体装置の素子分離領域は、素子分離領域下
の基板と同型の不純物層の濃度を一部のみ濃くすること
により、基板と同型の高濃度不純物層と基板と逆型の不
純物層とが分離されトランジスタを形成することを特徴
として構成され、その結果基板と逆型の不純物層のまわ
りにできる空芝屑の幅が接合部全面で大きくなる事によ
り、接合部の寄生容量が小さくなるという効果が得られ
る。In the element isolation region of the semiconductor device of the present invention, by increasing the concentration of only a portion of the impurity layer of the same type as the substrate under the element isolation region, a high concentration impurity layer of the same type as the substrate and an impurity layer of the opposite type to the substrate can be formed. As a result, the width of the air debris formed around the impurity layer of the opposite type to the substrate increases over the entire surface of the junction, reducing the parasitic capacitance at the junction. This effect can be obtained.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(ao)〜(c)は本発明の一実施例の構造及び
その製造方法を説明するために工程順に示した半導体装
置の断面図である。FIGS. 1A to 1C are cross-sectional views of a semiconductor device shown in the order of steps for explaining the structure and manufacturing method of an embodiment of the present invention.
本発明の半導体装置の製造方法は、まず第1図(a)に
示すように、シリコン基板上に酸化膜。In the method for manufacturing a semiconductor device of the present invention, first, as shown in FIG. 1(a), an oxide film is formed on a silicon substrate.
窒化膜を形成し素子分離領域となる部分の窒化膜をエツ
チングする0次に素子分離領域下の一部の基板と同型の
不純物層の濃度を濃くする以外の所をフォトレジストで
覆い、イオン注入により、不純物層の濃度の濃い部分3
を形成する。Form a nitride film and etch the nitride film in the part that will become the device isolation region. Cover the parts under the device isolation region with photoresist except for increasing the concentration of the impurity layer of the same type as the substrate, and perform ion implantation. Therefore, the part 3 with high concentration of the impurity layer
form.
次に第1図(b)に示すように、フォトレジスト2を除
去し、窒化膜1をマスクとして酸化して素子分離領域7
を形成する。Next, as shown in FIG. 1(b), the photoresist 2 is removed, and the element isolation region 7 is oxidized using the nitride film 1 as a mask.
form.
次いで第1図(c)に示すように、窒化膜を除去し、公
知の方法によりゲート酸化膜、ゲート電極5、およびN
型不純物層4を形成し、半導体装置を完成する。Next, as shown in FIG. 1(c), the nitride film is removed, and the gate oxide film, gate electrode 5, and N
A type impurity layer 4 is formed to complete the semiconductor device.
素子分離領域下の一部の基板と同型の不純物層の濃度を
濃くすることにより、トランジスタを形成する基板と逆
型の不純物層と素子分離領域下の一部の基板と同型の不
純物層の接合面の不純物の濃度差が小さくなり、空乏層
の幅が従来より広くなる為、寄生容量が小さくなる。By increasing the concentration of the impurity layer of the same type as the part of the substrate under the element isolation region, it is possible to bond the impurity layer of the opposite type to the substrate forming the transistor and the impurity layer of the same type as the part of the substrate under the element isolation region. The difference in the concentration of impurities on the plane becomes smaller, and the width of the depletion layer becomes wider than before, so the parasitic capacitance becomes smaller.
以上説明したように本発明は、半導体の素子分離領域下
の一部のみで基板と同型の不純物層の濃度を濃くしたこ
とにより、トランジスタを形成する基板と逆型の不純物
層と素子分離領域下でトランジスタを形成する不純物層
との接合面の濃度差が小さくなる為、空乏層が広くなり
、寄生容量が小さくなり、半導体装置の動作速度を速く
するという効果を有する。As explained above, in the present invention, by increasing the concentration of the impurity layer of the same type as the substrate only in a part under the element isolation region of the semiconductor, the impurity layer of the opposite type to the substrate forming the transistor and the impurity layer under the element isolation region are formed. Since the concentration difference at the junction surface with the impurity layer forming the transistor becomes smaller, the depletion layer becomes wider, the parasitic capacitance becomes smaller, and the operating speed of the semiconductor device is increased.
第1図<a)〜(c)は、本発明の一実施例の構造およ
びその製造方法を説明するために工程順に示した半導体
装置のFr面図、第2図は従来の半導体装置の一例の断
面図である。
1・・・窒化膜、2・・・フォトレジスト、3・・・P
型不純物層、4・・・N型不純物層、5・・・ケート電
極、6、・・P型半導体基板、7・・・素子分離領域。FIGS. 1A to 1C are FR side views of a semiconductor device shown in order of steps to explain the structure and manufacturing method of an embodiment of the present invention, and FIG. 2 is an example of a conventional semiconductor device. FIG. 1...Nitride film, 2...Photoresist, 3...P
type impurity layer, 4... N type impurity layer, 5... Kate electrode, 6... P type semiconductor substrate, 7... Element isolation region.
Claims (1)
の不純物濃度を濃くしたことを特徴とする半導体装置。A semiconductor device characterized in that the concentration of an impurity of the same type as a substrate is increased only in a portion under an element isolation region of the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21615590A JPH0498850A (en) | 1990-08-16 | 1990-08-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21615590A JPH0498850A (en) | 1990-08-16 | 1990-08-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0498850A true JPH0498850A (en) | 1992-03-31 |
Family
ID=16684154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21615590A Pending JPH0498850A (en) | 1990-08-16 | 1990-08-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0498850A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5484742A (en) * | 1991-10-08 | 1996-01-16 | Nec Corporation | Process for preparing a semiconductor device with a narrow-channel MOS transistor |
-
1990
- 1990-08-16 JP JP21615590A patent/JPH0498850A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5484742A (en) * | 1991-10-08 | 1996-01-16 | Nec Corporation | Process for preparing a semiconductor device with a narrow-channel MOS transistor |
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