JPS6244862B2 - - Google Patents
Info
- Publication number
- JPS6244862B2 JPS6244862B2 JP57060545A JP6054582A JPS6244862B2 JP S6244862 B2 JPS6244862 B2 JP S6244862B2 JP 57060545 A JP57060545 A JP 57060545A JP 6054582 A JP6054582 A JP 6054582A JP S6244862 B2 JPS6244862 B2 JP S6244862B2
- Authority
- JP
- Japan
- Prior art keywords
- island
- semiconductor material
- material layer
- oxidizable
- shaped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 230000000295 complement effect Effects 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 238000002955 isolation Methods 0.000 description 11
- 108091006146 Channels Proteins 0.000 description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は相補型MOS半導体装置の製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a complementary MOS semiconductor device.
相補型MOS半導体集積回路（CMOS IC）は従
来、同一基板上にｐチヤンネルMOS Trとｎチヤ
ンネルMOS Trを形成したものである。こうした
ｐチヤンネルMOS TrとｎチヤンネルMOS Trを
分離するために半導体基板に該基板と逆導電型の
ウエル領域を設けている。ｎ型半導体基板を用い
たCOMS ICでは、ｎチヤンネルMOS Trを基板
中のｐ−ウエル領域上に、ｐチヤンネルMOS Tr
をウエル領域以外の基板上に形成している。
Conventionally, a complementary MOS semiconductor integrated circuit (CMOS IC) has a p-channel MOS Tr and an n-channel MOS Tr formed on the same substrate. In order to separate these p-channel MOS Tr and n-channel MOS Tr, a well region of a conductivity type opposite to that of the substrate is provided in the semiconductor substrate. In a COMS IC using an n-type semiconductor substrate, an n-channel MOS Tr is placed on a p-well region in the substrate, and a p-channel MOS Tr is placed on a p-well region in the substrate.
is formed on the substrate other than the well region.
しかしながら、上記従来構造のCMOS ICでは
P+型ソース領域（又はドレイン領域）とｎ型半
導体基板とp-ウエル領域とによる寄生pnp Trや
n+型ソース領域（又はドレイン領域）とp-ウエ
ル領域とｎ型半導体基板とによる寄生npn Trが
発生することによつてラツチアツプ現象が起き
る。ラツチアツプ現象は半導体基板及びウエル領
域の抵抗と少数キヤリアの到達確率より決まる。
到達確率はｎチヤンネルMOS Tr、ｐチヤンネル
MOS Trの素子領域間の距離で決まるために、微
細化すればラツチアツプ現象が起こり易くなり、
素子特性の低下を招く。
However, in the CMOS IC with the above conventional structure,
Parasitic pnp Tr and
The latch-up phenomenon occurs due to the generation of a parasitic npn Tr between the n + -type source region (or drain region), the p - well region, and the n-type semiconductor substrate. The latch-up phenomenon is determined by the resistance of the semiconductor substrate and well region and the probability of arrival of minority carriers.
The arrival probability is n channel MOS Tr, p channel
Since it is determined by the distance between the element regions of the MOS Tr, the latch-up phenomenon becomes more likely to occur as the size becomes smaller.
This leads to deterioration of device characteristics.
本発明はラツチアツプ現象の防止と素子の微細
化を達成した高性能、高集積度の相補型MOS半
導体装置の製造方法を提供しようとするものであ
る。
The present invention aims to provide a method for manufacturing a high-performance, highly integrated complementary MOS semiconductor device that prevents the latch-up phenomenon and achieves miniaturization of elements.
本発明は半導体基板上の被酸化性半導体材料層
の選択酸化による素子分離において、少なくとも
隣り合う島状の残存被酸化性半導体材料層の一方
を除去し、他方を残してウエル領域として利用
し、半導体材料層が除去された基板領域及びその
まま残した半導体材料層に異なるチヤンネルの
MOS Trを形成することによつて、ウエル分離を
不要としてラツチアツプ現象を防止した高性能、
高集積度のCMOS ICを得ることを骨子とするも
のである。
In device isolation by selective oxidation of an oxidizable semiconductor material layer on a semiconductor substrate, the present invention removes at least one of the remaining oxidizable semiconductor material layers in an adjacent island shape, leaving the other to be used as a well region, Different channels are formed in the substrate area from which the semiconductor material layer has been removed and in the semiconductor material layer that remains intact.
By forming a MOS Tr, high performance is achieved by eliminating the need for well isolation and preventing the latch-up phenomenon.
The main objective is to obtain a highly integrated CMOS IC.
(i) まず、ｐ型単結晶シリコン基板１を熱酸化し
て厚さ500Åの熱酸化膜２を成長させ、この熱
酸化膜２上に厚さ4000Åの多結晶シリコン層３
を気相成長させた後、厚さ3000Åのシリコン窒
化膜４を堆積した（第１図図示）。つづいて、
前記シリコン窒化膜４をリアクテイブイオンテ
ツチングを用いたフオトエツチング技術により
パターニングして素子領域予定部に対応する多
結晶シリコン層３上にシリコン窒化膜パターン
５１，５２……を形成した。ひきつづき、これ
らパターン５１，５２……をマスクとしてｐ型
不純物、例えばボロンを多結晶シリコン層３、
熱酸化膜２を通して基板１にイオン注入し、活
性化してｐ−型のチヤンネルストツパ領域６…
…を形成した（第２図図示）。
(i) First, a p-type single crystal silicon substrate 1 is thermally oxidized to grow a thermal oxide film 2 with a thickness of 500 Å, and a polycrystalline silicon layer 3 with a thickness of 4000 Å is grown on this thermal oxide film 2.
After vapor phase growth, a silicon nitride film 4 with a thickness of 3000 Å was deposited (as shown in FIG. 1). Continuing,
The silicon nitride film 4 was patterned by a photoetching technique using reactive ion etching to form silicon nitride film patterns 5 1 , 5 2 . . . on the polycrystalline silicon layer 3 corresponding to the intended device region. Subsequently, using these patterns 5 1 , 5 2 . . . as masks, a p-type impurity such as boron is applied to the polycrystalline silicon layer 3,
Ions are implanted into the substrate 1 through the thermal oxide film 2 and activated to form p-type channel stopper regions 6...
... was formed (as shown in Figure 2).
(ii) 次いで、シリコン窒化膜パターン５１，５２
……を耐酸化性マスクとして多結晶シリコン層
３を選択酸化した。この時、多結晶シリコン層
３の露出部付近が酸化されて寸法変換差が0.15
μｍの素子間分離用の厚さ8000Åの厚い酸化膜
７……が形成された。なお、シリコン窒化膜パ
ターン５１，５２……下には島状の多結晶シリ
コン層８１，８２……が残存した（第３図図
示）。つづいて、シリコン窒化膜パターン５
１，５２……をCF4系のドライエツチングによ
り除去した（第４図図示）。(ii) Next, silicon nitride film patterns 5 1 , 5 2
... was used as an oxidation-resistant mask to selectively oxidize the polycrystalline silicon layer 3. At this time, the vicinity of the exposed part of the polycrystalline silicon layer 3 is oxidized and the dimensional conversion difference is 0.15.
A thick oxide film 7 with a thickness of 8000 Å for isolation between μm elements was formed. Note that island-shaped polycrystalline silicon layers 8 1 , 8 2 . . . remained below the silicon nitride film patterns 5 1 , 5 2 . . . (as shown in FIG. 3). Next, silicon nitride film pattern 5
1 , 5 2 . . . were removed by CF 4 -based dry etching (as shown in Figure 4).
(iii) 次いで、隣り合う島状の残存多結晶シリコン
層８１，８２の一方の残存多結晶シリコン層８
１を含む厚い酸化膜７……上に写真蝕刻法によ
りレジストパターン９を形成し、このレジスト
パターン９及び厚い酸化膜７……をマスクとし
て露出した残存多結晶シリコン層８２をCCl4
系のリアクテイブイオンエツチングにより除去
した。この時、厚い酸化膜７……に対してセル
フアラインで残存多結晶シリコン層８２が略垂
直にエツチングされ、第５図に示す如く厚い酸
化膜７……の素子領域予定部側のオーバーハン
グ部に多結晶シリコン層１０が残存した。つづ
いて、レジストパターン９を除去した後、熱酸
化処理を施した。この時、オーバーハング部に
残存した多結晶シリコン層１０が酸化膜とな
り、前記厚い酸化膜と共にオーバーハング部の
ない素子分離膜１１が形成された。なお、同時
に島状の残存知結晶シリコン層８１表面及び残
存多結晶シリコン層８２が存在していた基板１
領域の表面に酸化膜（図示せず）が成長され
た。ひきつづき、残存多結晶シリコン層８２上
の酸化膜及び基板１上の熱酸化膜をエツチング
除去した（第６図図示）。(iii) Next, one of the remaining polycrystalline silicon layers 8 of the adjacent island-shaped remaining polycrystalline silicon layers 8 1 and 8 2
A resist pattern 9 is formed by photolithography on the thick oxide film 7 containing 1 , and using this resist pattern 9 and the thick oxide film 7 as a mask, the exposed remaining polycrystalline silicon layer 82 is etched with CCl 4
It was removed by reactive ion etching. At this time, the remaining polycrystalline silicon layer 82 is etched substantially perpendicularly to the thick oxide film 7 in self-alignment, and as shown in FIG. A polycrystalline silicon layer 10 remained in some areas. Subsequently, after removing the resist pattern 9, thermal oxidation treatment was performed. At this time, the polycrystalline silicon layer 10 remaining in the overhang portion became an oxide film, and together with the thick oxide film, an element isolation film 11 without an overhang portion was formed. Note that at the same time, the surface of the island-shaped residual intellectual crystal silicon layer 8 1 and the residual polycrystalline silicon layer 8 2 were present on the substrate 1.
An oxide film (not shown) was grown on the surface of the region. Subsequently, the oxide film on the remaining polycrystalline silicon layer 82 and the thermal oxide film on the substrate 1 were removed by etching (as shown in FIG. 6).
(iv) 次いで、再度熱酸化処理を施して島状の残存
多結晶シリコン層８１表面、及び露出した島状
の基板１領域上に夫々ゲート酸化膜１２１，１
２２を形成した。つづいて島状の残存多結晶シ
リコン層８１のチヤンネル予定部に閾値制御の
ためのｎ型不純物、例えば砒素を選択的にイオ
ン注入した。ひきつづき、全面に厚さ4000〜
6000Åの多結晶シリコン層を気相成長し、導電
性を与えるための高濃度不純物拡散を行なつた
後、パターニングしてゲート酸化膜１２１，１
２２上に夫々選択的にゲート電極１３１，１３
２を形成した（第７図図示）。(iv) Next, thermal oxidation treatment is performed again to form gate oxide films 12 1 , 1 on the island-shaped remaining polycrystalline silicon layer 8 1 surface and the exposed island-shaped substrate 1 region, respectively.
2 2 was formed. Subsequently, an n-type impurity such as arsenic was selectively ion-implanted into the channel portion of the island-shaped remaining polycrystalline silicon layer 81 for threshold control. Continuing to coat the entire surface with a thickness of 4000~
A 6000 Å polycrystalline silicon layer is grown in a vapor phase, and after high-concentration impurity diffusion is performed to provide conductivity, it is patterned to form gate oxide films 12 1 , 1
Gate electrodes 13 1 , 13 are selectively formed on 2 2 , respectively.
2 was formed (as shown in Figure 7).
(v) 次いで、光蝕刻法により残存多結晶シリコン
層８１側をレジストパターン（図示せず）で覆
つた後、該レジストパターン、素子間分離膜１
１及びゲート電極１２２をマスクとしてｐ型単
結晶シリコン基板１にｎ型不純物、例えば砒素
をイオン注入し、活性化してソース、ドレイン
領域となるn+型領域１４，１４を形成してｎ
チヤンネルMOS Tr１５を作つた。ひきつづ
き、前記レジストパターンを除去し、再度光蝕
刻法によりｎチヤンネルMOS Tr１５側をレジ
ストパターン（図示せず）で覆つた後、該レジ
ストパターン、素子間分離膜１１及びゲート電
極１２１をマスクとして島状の残存多結晶の残
存多結晶シリコン層８１にｐ型純物、例えばボ
ロンをイオン注入し、活性化してソース、ドレ
イン領域となるp+型領域１６，１６を形成し
てｐチヤンネルMOS Tr１７を作つた。こうし
た方法によりOMOS ICを製造した（第８図図
示）。(v) Next, the remaining polycrystalline silicon layer 8 1 side is covered with a resist pattern (not shown) by photoetching, and then the resist pattern and the inter-element isolation film 1 are covered with a resist pattern (not shown).
1 and gate electrode 12 2 as a mask, an n-type impurity, for example, arsenic, is ion-implanted into the p-type single crystal silicon substrate 1, and activated to form n + -type regions 14, 14, which will become source and drain regions.
I made channel MOS Tr15. Subsequently, the resist pattern is removed, and the n-channel MOS transistor 15 side is again covered with a resist pattern (not shown) by photolithography, and then an island is formed using the resist pattern, the isolation film 11, and the gate electrode 121 as a mask. A p-type pure dopant, for example, boron, is ion-implanted into the remaining polycrystalline silicon layer 81 to form p + -type regions 16, 16 which will be activated and become source and drain regions, thereby forming a p-channel MOS Tr17. I made it. An OMOS IC was manufactured using this method (as shown in Figure 8).
しかして、本発明方法によれば次のような種種
の効果を有する。 Therefore, the method of the present invention has the following various effects.
得られたCMOS ICはｐ型単結晶シリコン基
板１上に多結晶シリコン層３の選択酸化により
形成された素子間分離膜１１が設けられ、かつ
該分離膜１１で分離された島状の基板１領域に
ｎチヤンネルMOS Tr１５を、前記選択酸化に
より残存した島状の多結晶シリコン層８１にｐ
チヤンネルMOS Tr１７を夫々設けると共に、
ｐチヤンネルMOS Tr１７が形成される島状の
残存多結晶シリコン層８１が基板１に対して熱
酸化膜２で分離された構造になつている。つま
り、ウエル領域がなくなる構造となつている。
このため、従来の如くウエル領域を有する基板
からCMOS ICを造つた場合のような寄生
npnTrの発生がなく、ラツチアツプ現象のない
高性能のCMOS ICを得ることができる。 The obtained CMOS IC has an isolation film 11 formed by selective oxidation of a polycrystalline silicon layer 3 on a p-type single crystal silicon substrate 1, and an island-shaped substrate 1 separated by the isolation film 11. An n-channel MOS transistor 15 is formed in the region, and a p
In addition to providing each channel MOS Tr17,
The island-shaped residual polycrystalline silicon layer 81 in which the p-channel MOS transistor 17 is formed is separated from the substrate 1 by a thermal oxide film 2. In other words, the structure is such that there is no well region.
For this reason, parasitic
A high-performance CMOS IC without npnTr generation and latch-up phenomenon can be obtained.
ウエル現象形成に必要な高温ドライブイン処
理が不要なため、プロセスの低温化が可能とな
り、素子特性の向上化を達成できる。 Since the high-temperature drive-in process required to form a well phenomenon is not required, the process can be carried out at a lower temperature and device characteristics can be improved.
ウエル領域形成に必要な分離帯が不要となる
ためCMOS ICの高集積化を図ることができ
る。 Since there is no need for isolation bands required for forming well regions, it is possible to achieve higher integration of CMOS ICs.
素子分離膜１１はｐ型単結晶シリコン基板１
上の多結晶シリコン層３の選択酸化により形成
されるため、従来法の如く基板を直接選択酸化
する方法のように基板へのストレス発生を抑制
でき、ひいては基板１の島状領域に形成される
MOS Tr（ここではｎチヤンネルMOS Tr１
５）の電気特性等を著しく改善できる。 Element isolation film 11 is p-type single crystal silicon substrate 1
Since it is formed by selective oxidation of the upper polycrystalline silicon layer 3, stress generation on the substrate can be suppressed unlike the conventional method of selectively oxidizing the substrate directly, and as a result, the polycrystalline silicon layer 3 is formed in the island-like region of the substrate 1.
MOS Tr (here n-channel MOS Tr1)
5) The electrical characteristics etc. can be significantly improved.
なお、上記実施例では基板としてｐ型のものを
用いたが、ｎ型半導体基板を用いてCMOS ICを
製造してもよい。 Note that although a p-type substrate was used as the substrate in the above embodiment, a CMOS IC may be manufactured using an n-type semiconductor substrate.
また、上記実施例では被酸化性半導体材料層と
して多結晶シリコン層を用いたが、非晶質シリコ
ン層を用いてCMOS ICを製造してもよい。 Further, in the above embodiment, a polycrystalline silicon layer is used as the oxidizable semiconductor material layer, but a CMOS IC may be manufactured using an amorphous silicon layer.
以上詳述した如く、本発明によればラツチアツ
プ現象の防止、素子の微細化等を達成した高性
能、高集積度の相補型MOS半導体装置の製造方
法を提供できるものである。
As detailed above, according to the present invention, it is possible to provide a method for manufacturing a high-performance, highly integrated complementary MOS semiconductor device that achieves prevention of the latch-up phenomenon, miniaturization of elements, etc.
第１図〜第８図は本発明の実施例における
CMOS ICの製造工程を示す断面図である。
１……ｐ型単結晶シリコン基板、２……熱酸化
膜、３……多結晶シリコン層、５１，５２……シ
リコン窒化膜パターン、６……p-型チヤンネル
ストツパ領域、７……厚い酸化膜、８１，８２…
…島状の残存多結晶シリコン層、１１……素子間
分離膜、１２１，１２２……ゲート酸化膜、１３
１，１３２……ゲート電極、１４……n+型領
域、１５……ｎチヤンネルMOS Tr、１６……
p+型領域、１７……ｐチヤンネルMOS Tr。
FIGS. 1 to 8 show examples of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of a CMOS IC. DESCRIPTION OF SYMBOLS 1...p-type single crystal silicon substrate, 2...thermal oxide film, 3...polycrystalline silicon layer, 51 , 52 ...silicon nitride film pattern, 6...p - type channel stopper region, 7... ...thick oxide film, 8 1 , 8 2 ...
... Island-shaped residual polycrystalline silicon layer, 11 ... Inter-element isolation film, 12 1 , 12 2 ... Gate oxide film, 13
1 , 13 2 ... gate electrode, 14 ... n + type region, 15 ... n channel MOS Tr, 16 ...
p + type region, 17...p channel MOS Tr.
Claims (1)
材料層を形成する工程と、この半導体材料層上に
複数の耐酸化性マスク材を選択的に形成する工程
と、これらの耐酸化性マスク材を用いて露出する
被酸化性半導体材料層を選択酸化して厚い酸化膜
を形成した後、これらの耐酸化性マスク材を除去
する工程と、少なくとも隣り合う二つの残存被酸
化性半導体材料層の一方をリアクテイブイオンエ
ツチングにより選択的に除去して前記半導体基板
を島状に露出させた後、前記リアクテイブイオン
エツチングにより厚い酸化膜のオーバハング部に
残存した被酸化性半導体材料層を酸化処理して島
状の半導体基板領域周囲の厚い酸化膜の側面をテ
ーパ状にする工程と、前記島状の半導体基板領域
表面及び島状の被酸化性半導体材料層表面の酸化
膜を除去した後、露出した島状の半導体基板表面
及び島状の被酸化性半導体材料層表面を再度、酸
化してゲート酸化膜を形成する工程と、これらゲ
ート酸化膜上にゲート電極を選択的に形成する工
程と、島状の半導体基板領域に第２導電型の高濃
度不純物領域を、島状の残存被酸化性半導体材料
層に第１導電型の高濃度不純物領域を、夫々少な
くともゲート電極をマスクとして形成する工程と
を具備したことを特徴とする相補型MOS半導体
装置の製造方法。 ２ 第１導電型の半導体基板上に熱酸化膜を介し
て被酸化性半導体材料層を形成することを特徴と
する特許請求の範囲第１項記載の相補型MOS半
導体装置の製造方法。 ３ 被酸化性半導体材料として多結晶シリコン又
は非晶質シリコンを用いることを特徴とする特許
請求の範囲第１項記載の相補型MOS半導体装置
の製造方法。 ４ 耐酸化性マスク材がシリコン窒化膜をパター
ニングしたものであることを特徴とする特許請求
の範囲第１項記載の相補型MOS半導体装置の製
造方法。[Claims] 1. A step of forming an oxidizable semiconductor material layer on a semiconductor substrate of a first conductivity type, and a step of selectively forming a plurality of oxidation-resistant mask materials on this semiconductor material layer, After forming a thick oxide film by selectively oxidizing the exposed oxidizable semiconductor material layer using these oxidation-resistant mask materials, a process of removing these oxidation-resistant mask materials and removing at least two adjacent remaining After selectively removing one of the oxidizable semiconductor material layers by reactive ion etching to expose the semiconductor substrate in an island shape, the oxidizability remaining in the overhang portion of the thick oxide film by the reactive ion etching is removed. oxidizing the semiconductor material layer to make the sides of the thick oxide film around the island-shaped semiconductor substrate region tapered; and oxidizing the surface of the island-shaped semiconductor substrate region and the island-shaped oxidizable semiconductor material layer. After removing the film, the exposed island-shaped semiconductor substrate surface and the island-shaped oxidizable semiconductor material layer surface are oxidized again to form a gate oxide film, and a gate electrode is selected on these gate oxide films. forming a highly concentrated impurity region of the second conductivity type in the island-shaped semiconductor substrate region and a highly concentrated impurity region of the first conductivity type in the island-shaped remaining oxidizable semiconductor material layer, respectively at least at the gate. 1. A method for manufacturing a complementary MOS semiconductor device, comprising the step of forming an electrode as a mask. 2. A method for manufacturing a complementary MOS semiconductor device according to claim 1, characterized in that an oxidizable semiconductor material layer is formed on a semiconductor substrate of a first conductivity type via a thermal oxide film. 3. A method for manufacturing a complementary MOS semiconductor device according to claim 1, characterized in that polycrystalline silicon or amorphous silicon is used as the oxidizable semiconductor material. 4. The method for manufacturing a complementary MOS semiconductor device according to claim 1, wherein the oxidation-resistant mask material is a patterned silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57060545A JPS58176964A (en) | 1982-04-12 | 1982-04-12 | Preparation of complementary mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57060545A JPS58176964A (en) | 1982-04-12 | 1982-04-12 | Preparation of complementary mos semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58176964A JPS58176964A (en) | 1983-10-17 |
| JPS6244862B2 true JPS6244862B2 (en) | 1987-09-22 |
Family
ID=13145359
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57060545A Granted JPS58176964A (en) | 1982-04-12 | 1982-04-12 | Preparation of complementary mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58176964A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6113662A (en) * | 1984-06-28 | 1986-01-21 | Nippon Telegr & Teleph Corp <Ntt> | Complementary type mis transistor device and manufacture thereof |
| JPS63117460A (en) * | 1986-11-05 | 1988-05-21 | Nec Corp | Manufacture of semiconductor integrated circuit device |
| JP2812388B2 (en) * | 1988-01-18 | 1998-10-22 | 富士通株式会社 | Method of manufacturing SOI semiconductor device |
| JP4803866B2 (en) * | 2000-07-31 | 2011-10-26 | ローム株式会社 | Semiconductor device |
-
1982
- 1982-04-12 JP JP57060545A patent/JPS58176964A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58176964A (en) | 1983-10-17 |
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