JPH049778A - Noise resistance evaluation method - Google Patents
Noise resistance evaluation methodInfo
- Publication number
- JPH049778A JPH049778A JP2114291A JP11429190A JPH049778A JP H049778 A JPH049778 A JP H049778A JP 2114291 A JP2114291 A JP 2114291A JP 11429190 A JP11429190 A JP 11429190A JP H049778 A JPH049778 A JP H049778A
- Authority
- JP
- Japan
- Prior art keywords
- radio wave
- antenna
- tester
- voltage source
- noise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011156 evaluation Methods 0.000 title claims description 9
- 238000012360 testing method Methods 0.000 claims description 4
- 230000007257 malfunction Effects 0.000 abstract description 13
- 238000012790 confirmation Methods 0.000 abstract 1
- 230000000644 propagated effect Effects 0.000 abstract 1
- 238000011158 quantitative evaluation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は集積回路装置のノイズ耐量評価方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for evaluating noise tolerance of an integrated circuit device.
（従来の技術）
第３図は従来の集積回路装置のノイズ耐量評価方法を示
す構成ブロック図である。図において、（１）は評価対
象物たる集積回路装置（以下ｒｃと呼ぶ）、（２）はＩ
Ｃ（１）を動作させるテスタ、（Ｆ）はＩＣ（１）の任
意の１つの端子とテスタ（２）とを接続する導線とアー
スとの間に設けられたコンデンサである。(Prior Art) FIG. 3 is a block diagram showing a conventional noise tolerance evaluation method for an integrated circuit device. In the figure, (1) is an integrated circuit device (hereinafter referred to as rc) that is the evaluation target, and (2) is an I
A tester that operates IC (1), (F) is a capacitor provided between the ground and a conducting wire connecting any one terminal of IC (1) and tester (2).
次に動作について説明する。テスタ（２）によってＩＣ
（１）のコンデンサ（Ｆ）が接続されている端子にハイ
レベルの電位を与えると、コンデンサ（Ｆ）が充電され
る。次いで、この端子にローレベルの電位をテスタ（２
）か与えると、コンデンサ（Ｆ）が充電し、ＩＣ（１）
のアース端子に電流が流わ込む。この電流がノイズ発生
源となる。このとき、テスタ（２）がＩＣ（１）の電気
的特性が期待されるタイミングとずれていたり、期待さ
れるファンクションを行っていない等の誤動作を確認す
ると、テスタ（２）はＩＣ（１）が誤動作を発生したこ
とを表示する。Next, the operation will be explained. IC by tester (2)
When a high-level potential is applied to the terminal connected to the capacitor (F) in (1), the capacitor (F) is charged. Next, apply a low level potential to this terminal using a tester (2
), the capacitor (F) charges and IC (1)
Current flows into the ground terminal of. This current becomes a noise generation source. At this time, if the tester (2) detects a malfunction such as the electrical characteristics of the IC (1) being out of sync with the expected timing or not performing the expected function, the tester (2) will test the IC (1). indicates that a malfunction has occurred.
そこで、コンデンサ（Ｅ）を変化させることによって放
電電流の値を変え、ノイズによるＩＣ（１）の誤動作の
発生を確認する。Therefore, by changing the capacitor (E), the value of the discharge current is changed, and the occurrence of malfunction of the IC (1) due to noise is confirmed.
従来の集積回路装置のノイズ耐量評価方法は以上のよう
に構成されていたので、ノイズによる誤動作の確認がな
されるだけで、ノイズ耐量を定量的に評価できないとい
う問題点があった。Since the conventional method for evaluating the noise tolerance of an integrated circuit device is configured as described above, there is a problem in that the noise tolerance cannot be quantitatively evaluated, but only a malfunction due to noise is confirmed.
この発明は上記のような問題点を解消するためになされ
たもので、集積回路装置のノイズ耐量を定量的に評価す
るノイズ耐量評価方法を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a noise tolerance evaluation method for quantitatively evaluating the noise tolerance of an integrated circuit device.
［課題を解決するための手段］
この発明に係るノイズ耐量評価方法は、集積回路装置を
テストするテスタと、電波発生回路と、この電波発生回
路に接続された電圧源と、前記電波発生回路に一接続さ
れたアンテナと、前記集積回路の任意の１端子に設けら
れたアンテナとを備えたものである。[Means for Solving the Problems] A noise tolerance evaluation method according to the present invention includes a tester for testing an integrated circuit device, a radio wave generation circuit, a voltage source connected to the radio wave generation circuit, and a voltage source connected to the radio wave generation circuit. The integrated circuit has one connected antenna and an antenna provided at any one terminal of the integrated circuit.
この発明におけるノイズ耐量評価方法は、集積回路装置
の任意の１端子に電波によるノイズを任意のタイミング
で与えた時、集積回路装置のノイズ耐量を電圧源の電圧
によって定量的に評価する。The noise tolerance evaluation method according to the present invention quantitatively evaluates the noise tolerance of an integrated circuit device using the voltage of a voltage source when radio wave noise is applied to any one terminal of the integrated circuit device at any timing.
以下、この発明の一実施例を図に従って説明する。第１
図はこの発明の一実施例であるノイズ耐量評価方法を示
す構成ブロック図、第２図（ａ）はテスタ（２）がＩＣ
（１）の任意の１端子に与える信号波形とパルス発生手
段が発生するパルスのタイミングを示すタイミンク図、
第２図（ｂ）はノイズ発生の状態を示すタイミング図で
ある。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing a noise tolerance evaluation method which is an embodiment of the present invention.
(1) A timing diagram showing the signal waveform applied to any one terminal and the timing of the pulse generated by the pulse generating means,
FIG. 2(b) is a timing diagram showing the state of noise generation.
なお、図中、前記従来のものと同一符号は同一部分を示
す。図において、（３）はテスタ（２）に接続された電
波発生回路、（４）は電波発生回路（３）に接続された
アンテナ、（５）はＩＣ（１）の任意の１端子に設けら
れたアンテナ、（６）は電波発生回路（３）に接続され
た電圧源、（Ａ）はテスタ（２）かＩＣ（１）の任意の
１端子に与える信号波形、（Ｂ）と（Ｃ）はパルス発生
手段（３）が発生するパルス、（Ｄ）と（Ｅ）はノイズ
が発生する状態である。In addition, in the figure, the same reference numerals as those in the conventional device indicate the same parts. In the figure, (3) is a radio wave generation circuit connected to the tester (2), (4) is an antenna connected to the radio wave generation circuit (3), and (5) is attached to any one terminal of the IC (1). (6) is the voltage source connected to the radio wave generation circuit (3), (A) is the signal waveform applied to any one terminal of the tester (2) or IC (1), (B) and (C ) is a pulse generated by the pulse generating means (3), and (D) and (E) are states in which noise is generated.
次に動作について説明する。テスタ（２）がＩＣ（１）
のアンテナ（５）が設けられている任意の１端子に（Ａ
）の信号波形を与える。次に、テスタ（２）が電波発生
回路（３）に（Ｂ）のパルスを与える。電波発生回路（
３）はこのパルス（Ｂ）を電波に変換する。この電波の
電波量は電圧源（６）によって変化できる。この電波を
アンテナ（４）がアンテナ（５）へ伝搬する。この電波
かノイズである。このノイズが発生した場合のｒｃ （
１）のアンテナ（５）が設けられている任意の１端子の
信号波形を（Ｄ）に示す。このようにノイズを発生させ
た場合に、テスタ（２）がＩＣ（１）の電気的特性が期
待されるタイミングとずれていたり１期待されるファン
クションを行っていない等の誤動作を確認すると、テス
タ（２）は１ｃ（１）が誤動作を発生したことを表示す
る。誤動作が発生していなければ電圧源（６）の電圧を
変化させ、同様にして測定を行う。この操作をＩＣ（１
）が誤動作を発生するまで繰り返す。ＩＣ（１）が初め
て誤動作を発生したときの電圧源（６）の電圧がＩＣ（
１）のノイズ耐量である。Next, the operation will be explained. Tester (2) is IC (1)
An antenna (5) of (A
) gives the signal waveform. Next, the tester (2) applies the pulse (B) to the radio wave generation circuit (3). Radio wave generation circuit (
3) converts this pulse (B) into radio waves. The amount of this radio wave can be changed by the voltage source (6). Antenna (4) propagates this radio wave to antenna (5). This is radio waves or noise. When this noise occurs, rc (
(D) shows the signal waveform of any one terminal provided with the antenna (5) of 1). When noise is generated in this way, if the tester (2) detects malfunctions such as the electrical characteristics of the IC (1) being out of sync with the expected timing, or the IC (1) not performing the expected function, the tester (2) (2) indicates that 1c(1) has malfunctioned. If no malfunction has occurred, the voltage of the voltage source (6) is changed and measurement is performed in the same manner. This operation is performed using IC(1
) is repeated until a malfunction occurs. When IC (1) malfunctions for the first time, the voltage of voltage source (6) is
1) is the noise tolerance.
また、上記実施例ではｒｃ（ｉ）のアンテナ（５）が設
けられている任意の１端子に与える信号波形（Ａ）のタ
イミンク゛と、テスタ（２）が発生するパルス（Ｂ）の
タイミングとが同時の場合について説明したが、タイミ
ングが同時でなくともよく、上記実施例と同様の効果を
奏する。タイミングが異なる場合のパルス発生手段が発
生するパルスを（Ｃ）に示す。また、電波発生回路（３
）がパルス（Ｃ）を電波に変換し、ノイズを発生させた
場合の、ＩＣ（１）のアンテナ（５）か設けられている
任意の１端子の信号波形を（Ｅ）に示す。Furthermore, in the above embodiment, the timing of the signal waveform (A) applied to any one terminal provided with the antenna (5) of rc(i) and the timing of the pulse (B) generated by the tester (2) are different. Although the explanation has been given on the case where the timings are simultaneous, the timings do not have to be simultaneous, and the same effects as in the above embodiment can be achieved. (C) shows pulses generated by the pulse generating means when the timings are different. In addition, the radio wave generation circuit (3
) converts the pulse (C) into a radio wave and generates noise, and (E) shows the signal waveform at any one terminal provided with the antenna (5) of the IC (1).
以上のようにこの発明によれば、ＩＣをテスト１−るテ
スタと、電波発生回路と、電波発生回路に接続された電
圧源と、電波発生回路に接続されたアンテナと、ＩＣの
任意の１端子に設けられたアンテナとを備えたことによ
り、ＩＣの任意のタイミングで加わるノイズに対するノ
イズ耐量を電圧源の電圧を代表特性として定量的に評価
かてきる。As described above, according to the present invention, there is provided a tester for testing an IC, a radio wave generation circuit, a voltage source connected to the radio wave generation circuit, an antenna connected to the radio wave generation circuit, and an arbitrary one of the ICs. By providing the antenna provided at the terminal, the noise tolerance against noise added to the IC at any timing can be quantitatively evaluated using the voltage of the voltage source as a representative characteristic.
第１図はこの発明の一実施例であるＩＣのノイズ耐量評
価方法を示す構成ブロック図、第２図（ａ）はテスタが
ＩＣの任意の１端子に与える信号波形とテスタが電圧発
生回路に与えるパルスのタイミングを示すタイミング図
、第２図（ｂ）はノイズ発生の状態を示すタイミング図
、第３図は従来のＩＣのノイズ耐量評価方法を示す構成
ブロック図である。
図において、（１）はｒｃ、（２）はテスタ、（３）は
電波発生回路、（４）はアンテナ、（５）はアンテナ、
（６）は電圧源を示す。
なお、図中、同一符号は同一、又は相当部分を示す。
第１図Fig. 1 is a block diagram showing a method for evaluating the noise tolerance of an IC, which is an embodiment of the present invention. FIG. 2(b) is a timing diagram showing the timing of pulses to be applied, FIG. 2(b) is a timing diagram showing the state of noise generation, and FIG. 3 is a block diagram showing a conventional IC noise tolerance evaluation method. In the figure, (1) is rc, (2) is tester, (3) is radio wave generation circuit, (4) is antenna, (5) is antenna,
(6) indicates a voltage source. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1
Claims (1)
この電波発生回路に接続された電圧源と、前記電波発生
回路に接続されたアンテナと、前記集積回路の任意の１
端子に設けられたアンテナとを備えたことを特徴とする
ノイズ耐量評価方法。A tester for testing integrated circuit devices, a radio wave generation circuit,
A voltage source connected to the radio wave generation circuit, an antenna connected to the radio wave generation circuit, and an arbitrary one of the integrated circuits.
A noise tolerance evaluation method characterized by comprising an antenna provided at a terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2114291A JPH049778A (en) | 1990-04-27 | 1990-04-27 | Noise resistance evaluation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2114291A JPH049778A (en) | 1990-04-27 | 1990-04-27 | Noise resistance evaluation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH049778A true JPH049778A (en) | 1992-01-14 |
Family
ID=14634179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2114291A Pending JPH049778A (en) | 1990-04-27 | 1990-04-27 | Noise resistance evaluation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH049778A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007295364A (en) * | 2006-04-26 | 2007-11-08 | Nec Electronics Corp | Pll circuit and semiconductor device provided with pll circuit |
| JP2008261709A (en) * | 2007-04-11 | 2008-10-30 | Denso Corp | Semiconductor evaluation device |
| US7616071B2 (en) | 2005-06-14 | 2009-11-10 | Nec Electronics Corporation | PLL circuit and semiconductor device provided with PLL circuit |
-
1990
- 1990-04-27 JP JP2114291A patent/JPH049778A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7616071B2 (en) | 2005-06-14 | 2009-11-10 | Nec Electronics Corporation | PLL circuit and semiconductor device provided with PLL circuit |
| JP2007295364A (en) * | 2006-04-26 | 2007-11-08 | Nec Electronics Corp | Pll circuit and semiconductor device provided with pll circuit |
| JP4566944B2 (en) * | 2006-04-26 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | PLL circuit and semiconductor device including PLL circuit |
| JP2008261709A (en) * | 2007-04-11 | 2008-10-30 | Denso Corp | Semiconductor evaluation device |
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