JPH0484318A - Rounding arithmetic circuit - Google Patents

Rounding arithmetic circuit

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Publication number
JPH0484318A
JPH0484318A JP2199552A JP19955290A JPH0484318A JP H0484318 A JPH0484318 A JP H0484318A JP 2199552 A JP2199552 A JP 2199552A JP 19955290 A JP19955290 A JP 19955290A JP H0484318 A JPH0484318 A JP H0484318A
Authority
JP
Japan
Prior art keywords
input signal
rounding
signal
bit
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2199552A
Other languages
Japanese (ja)
Inventor
Yoshitaka Chokai
鳥海　佳孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2199552A priority Critical patent/JPH0484318A/en
Publication of JPH0484318A publication Critical patent/JPH0484318A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49963—Rounding to nearest

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Interconnected Communication Systems, Intercoms, And Interphones (AREA)
  • Color Television Systems (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Abstract

PURPOSE:To attain a rounding calculation with one instruction so as to make the rounding calculation at a high speed by providing a decoding means, selective means, and arithmetic logic computing element. CONSTITUTION:This circuit is provided with a 1st input signal 7 expressed by the complement of 2 and a decoding means 3 generating two kinds of the decoding output signals based on a 2nd input signal 2 which designates the rounding position of the input signal 7 and selective means 6 for which when the most significant bit of the 1st signal 7 is '0', a first decoding output signal is selected and when the most significant bit is '1', a second decoding output signal is selected and on arithmetic logic computing element 8 which inputs the 1st input signal 7 and the output signal of the selective means 6 and makes addition. Thus, positive-negative symmetrical zero-out rounding can be performed to an arbitrary rounding position.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は信号処理プロセッサ、特に画像用の信号処理プ
ロセッサの算術論理演算ユニットに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic and logic unit of a signal processing processor, in particular a signal processing processor for images.

〔従来の技術〕[Conventional technology]

ＣＣＩＴＴのｐ　Ｘ　６４ｂｉｔ／ｓテレビ電話符号化
方式の勧告Ｈ，２６１改定版では、動き補償フレーム間
ＤＣＴ符号化方式が採用される見込みである。この勧告
ては、送受の複合画像のミスマツチを抑えるために逆Ｄ
ＣＴ演算誤差の許容範囲が規定されている。これらの詳
細については、以下の文献を参照されたい。In the revised version of Recommendation H, 261 of the CCITT's p x 64 bit/s video telephone coding system, a motion compensated interframe DCT coding system is expected to be adopted. This recommendation is to prevent mismatches in composite images sent and received.
A permissible range of CT calculation errors is defined. For details, please refer to the following documents.

”ＣＣＩＴＴ　５ＧＸＶ　ＷＰ　ＸＶ／Ｉ　５ｐｅｃｉ
ａｌｉｓｔｓ　Ｇｒｏｕｐ　ｏｎＣｏｄｉｎｇ　ｆｏｒ
　Ｖｉｓｕａｌ　Ｔｅ１ｅｐｈｏｎｙ、Ｄｏｃ、＃５８
４．（１９８８−１１）″この逆ＤＣＴ演算時に例えば
３１ビツト中の下から１５ビツト目に１を加算してから
上位１６ビツトを切り取るいわゆる丸め処理が入ってい
る。”CCITT 5GXV WP XV/I 5peci
alists Group on Coding for
Visual Telephony, Doc, #58
4. (1988-11)'' During this inverse DCT operation, for example, a so-called rounding process is included in which 1 is added to the 15th bit from the bottom among the 31 bits, and then the upper 16 bits are cut off.

丸め方法としては、様々な手段が考えられるが、正負対
称の丸め（即ち絶対値で４捨５人、２進数では０捨１人
）を行う事により上述した逆ＤＣＴ演算誤差が最小にな
る事が報告されている。例えば２の補数の１６ビツト長
の信号に対して小数点位置が８ビツト目と９ビツト目に
あるような場合、２の補数の１６ビツト長の信号が正な
らば”００００００００．ｌ０００［）０００”（＝　
Ｃ１，５）を加算し、負ならば”００００００００．０
１１１１１１１”（＝、４９６１）を加算し、その結果
の小数点以下を切捨てることで、小数点以下に対する丸
めを行える。詳細は、以下の文献を参照されたい。Various methods can be used for rounding, but the above-mentioned inverse DCT calculation error can be minimized by rounding with positive and negative symmetry (i.e., 5 roundings to the nearest 4 for absolute values, 1 round to 0 for binary numbers). has been reported. For example, if the decimal point is at the 8th and 9th bit for a 2's complement 16-bit signal, if the 2's complement 16-bit signal is positive, it will be "00000000.l000[)000". (=
C1,5), and if it is negative, “00000000.0
1111111" (=, 4961) and rounding down the decimal part of the result, rounding can be performed for the decimal part. For details, please refer to the following document.

６″望月他　動画像処理用ＶＩＳＰ−ＬＳＩでの逆ＤＣ
Ｔ演算　１９９０年信学全太” 次に、従来のプロセッサについて説明スる。文献ｌ　（
Ｔｅｘａｓ　Ｉｎｓｔｒｕｍｅｎｔｓ　Ｔｈ１ｒｄ−Ｇ
ｅｎｅｒａｔｉｏｎ　ＴＭＳ３２０Ｕｓｅｒ’ｓ　Ｇｕ
ｉｄｅ）に基づき説明する。本発明は、ｒＡｓｓｅｍｂ
ｌｙ　Ｌａｎｇｕａｇｅ　Ｉｎ５ｔｒｕｃｔｉｏｎｓＪ
の章のＩＲＮＤ″という命令から抜粋して説明する。命
令フォーマットを示す。6″ Mochizuki et al. Reverse DC in VISP-LSI for video image processing
Next, we will explain about conventional processors.Reference l (
Texas Instruments Th1rd-G
eneration TMS320User's Gu
ide). The present invention provides rAssemb
ly Language In5tructionsJ
This is an excerpt from the instruction ``IRND'' in the chapter.The instruction format is shown below.

ＲＮＤ　　＜ｓ　　ｒ　ｃ＞　　＜ｄ　ｓ　ｔ＞このよ
うに指定されると、ソースオペランド（＜ｓｒｃ＞）の
丸め演算の結果がディストネーションレジスタ（＜ｄｓ
ｔ））に格納される。丸め演算は、単精度の浮動小数点
（即ち整数の小数点以下８桁目）で最も近い値になるよ
うに丸められる。もし、ちょうど真ん中の値（即ちｘ、
ｘｘｘｘｘｘｘ５）の場合は、正の方向に丸めを行って
いる。具体例を以下に示す。RND <s r c><d s t> When specified like this, the result of the rounding operation of the source operand (<src>) is stored in the destination register (<ds
t)). Rounding operations are performed to the nearest value in single-precision floating point (ie, the 8th digit after the decimal point of an integer). If the value is exactly in the middle (i.e. x,
xxxxxxx5), rounding is performed in the positive direction. A specific example is shown below.

命令実行前 ＜ｓｒｃ＞＝０７３３Ｃ１６ＥＥＦｈ＝　１．７９７５
５５９９ｅ＋０２（ｄｓｔ）二ｏｈ 命令実行後 ＜ｓｒｃ＞　＝０７３３Ｃ１６ＥＥＦｈ　＝　１．７９
７５５５９９ｅ＋０２（ｄｓｔ）＝０７３３ＣＩ６ＦＯ
Ｏｈ＝　１．７９７５５６００ｅ＋０２次に文献２　（
ＤＳＰ５６０ＱＯＤｉｇｉｔａｌ　Ｓｉｇｎａｌ　Ｐｒ
ｏｃｅｓｓｏｒＵｓｅｒ’ｓ　Ｍａｎｕａｌ）に基づき
説明する。本発明は、ｒＩｎｓｔｒｕｃｔｉｏｎ　ｓｅ
ｔ　ｄｅｔａｌｌｓＪの章の”　ＲＮ　Ｄ”という命令
から抜粋して説明する。命令フォーマットを示す。Before instruction execution <src> = 0733C16EEFh = 1.7975
5599e+02(dst)2oh After instruction execution <src> =0733C16EEFh = 1.79
755599e+02(dst)=0733CI6FO
Oh= 1.79755600e+02 Next, literature 2 (
DSP560QODigital Signal Pr
The explanation will be based on the user's manual. The present invention is directed to rInstruction se
An excerpt from the command "RN D" in the chapter t detailsJ will be explained. Indicates the instruction format.

ＲＮＤ　＜ｄ　ｓ　ｔ＞ このように指定されると、ディストネーションレジスタ
（＜ｄＳｔ＞）の丸め演算の結果がそのままディストネ
ーションレジスタ（＜ｃ（ｓ　ｔ＞）　ニ格納される。RND <d s t> When specified in this way, the result of the rounding operation in the destination register (<dSt>) is stored as is in the destination register (<c(s t>)).

このプロセッサの丸め演算は、丸め演算を行うビットに
対して定数（以下この定数を丸め定数と呼ぶ）を加算す
る事によって実現している。丸め定数は、ステータスレ
ジスタのスケーリングビットの値によって決定される。The rounding operation of this processor is realized by adding a constant (hereinafter referred to as a rounding constant) to the bits on which the rounding operation is to be performed. The rounding constant is determined by the value of the scaling bits in the status register.

下記の表に、丸めを行う位置と加える値の対応を示す。The table below shows the correspondence between rounding positions and added values.

Ｘ′−“　　　８チー“　　　Ｘ？−！１７／　　　　
丸め位置　　　丸め定数レジスタ１　　　　レジスタ２
　　　　モード履 〔発明が解決しよ 文献ｌのプロセ ５５−４４゜ ３．２２・Ｏ Ｘ’ｒ−１）７グ　　　　　２３　　　　　　　ｈ−ｏ
　＋　ａ、−。X′-“8chi” X? -! 17/
Rounding position Rounding constant register 1 Register 2
Mode [Invention Solved Document I Process 55-44゜3.22・O X'r-1) 7g 23 h-o
+ a, -.

なし ダウ、　　　　　　　　　２４　　　　　　　ＨＯＱ−
０７、プ　　　　　　２２　　　　　　（Ｐ−ＯＱ　Ｉ
−Ｑうとする課題〕 ツサのＲＮＤ命令では上述した 丸めっきの演算を負の数で、ｘ、ｘｘｘｘｘｘｘ５’″
の場合に正の方に丸めてしまうため絶対値の４捨５入丸
めを実行する事ができず、また所望のビット位置で丸め
を行うことができないという欠点がある。None Dow, 24 HOQ-
07, P-22 (P-OQ I
-Q Problem to be solved] Tsusa's RND instruction performs the above-mentioned rounding operation with a negative number, x, xxxxxxx5'''
In the case of , rounding is performed in the positive direction, so rounding to the nearest whole number cannot be performed on the absolute value, and rounding cannot be performed at a desired bit position.

文献２のプロセッサのＲＮＤ命令でも、負の数の場合に
正の方に丸めてしまうため絶対値の４捨５入丸めを実行
する事ができず、また所望のビット位置で丸めを行うこ
とができないという欠点がある。Even with the RND instruction of the processor in Document 2, if the number is negative, it rounds toward the positive, so it is not possible to round the absolute value to the nearest whole number, and it is not possible to round to the desired bit position. The drawback is that it cannot be done.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の丸め演算回路は、２の補数で表現される第１の
入力信号と、前記第１の入力信号の丸め位置を指定する
第２の入力信号と、前記第２の入力信号に基づき、丸め
位置のビットが“１″でそれ以外は“０”であるような
第１のデコード出力信号、及び丸め位置のビットより下
位のビットが全て１”でそれ以外は““０”であるよう
な第２のデコード圧力信号の２種類の出力信号を生成す
るデコード手段と、前記デコード手段から出力された２
つの信号を前記第１の入力信号の最上位ビットが““０
”ならば前記第１のデコード出力信号を選択し、前記第
１の入力信号の最上位ビットが“１”ならば前記第２の
デコード出力信号を選択する選択手段と、前記第１の入
力信号と前記選択手段からの出力信号を入力とし、加算
を行う算術論理演算器を有し、任意の丸め位置に対して
正負対称のＯ捨１入丸めが行える事を特徴としている。The rounding operation circuit of the present invention is based on a first input signal expressed in two's complement, a second input signal specifying the rounding position of the first input signal, and the second input signal, A first decoded output signal in which the bit at the rounding position is “1” and all other bits are “0”, and the bits lower than the bit at the rounding position are all 1” and all other bits are “0” a decoding means for generating two types of output signals, a second decoded pressure signal;
The most significant bit of the first input signal is ““0”.
”, selecting means for selecting the first decoded output signal, and selecting the second decoded output signal if the most significant bit of the first input signal is “1”; The present invention is characterized in that it has an arithmetic and logic unit which inputs output signals from the selection means and performs addition, and is capable of performing positive/negative symmetrical rounding to the nearest 0 to 1 with respect to any rounding position.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の第１の実施例のブロック図で、第２図
は第１図中のデコーダ回路の構成である。FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is a configuration of the decoder circuit in FIG. 1.

第１図において、ｌは第１の１６ビツト長の入力信号、
２は第２の４ビツト長の入力信号、３はデコーダ回路、
４は第１のデコード出力信号、５は第２のデコード出力
信号、６は選択回路、７は第１の入力信号の最上位ビッ
ト、８は算術論理演算器、９は算術論理演算ユニットの
圧力である。第２図において、１１は４ビツトの入力信
号、１２は４ヒツトの入力信号を１６ビツト信号にテコ
ドする第１のデコーダ回路、１３は４ビツトの入力信号
を１６ビツト信号にデコードする第２のデコーダ回路、
１４は第１のデコーダの出力信号、１５は第２のデコー
ダの圧力信号である。また、第１のデコーダと第２のデ
コーダの真理値表を第４図に示す。In FIG. 1, l is the first 16-bit long input signal;
2 is a second 4-bit long input signal, 3 is a decoder circuit,
4 is the first decode output signal, 5 is the second decode output signal, 6 is the selection circuit, 7 is the most significant bit of the first input signal, 8 is the arithmetic logic unit, and 9 is the pressure of the arithmetic logic unit. It is. In Fig. 2, 11 is a 4-bit input signal, 12 is a first decoder circuit that decodes a 4-bit input signal into a 16-bit signal, and 13 is a second decoder circuit that decodes a 4-bit input signal into a 16-bit signal. decoder circuit,
14 is the output signal of the first decoder, and 15 is the pressure signal of the second decoder. Further, the truth table of the first decoder and the second decoder is shown in FIG.

次に、本実施例における本発明の演算回路の動作につい
て述べる。Next, the operation of the arithmetic circuit of the present invention in this embodiment will be described.

丸め演算を行う入力信号１に対し丸めを行うヒツトの位
置の情報を持つ入力信号２は、デコーダ回路３に入力さ
れる。デコーダ回路は表１と表２の真理値表に従い入力
信号２をデコートして２つの出力信号４，５を出力する
。出力信号４，５は、入力信号１の最上位ビットが“０
”ならば出力信号４を、入力信号ｌの最上位ビットが“
１″ならば出力信号５を選択する。選択された出力信号
と入力信号１を算術論理演算器８によって加算を行い、
その結果を圧力信号９として出力する。An input signal 2 having information on the position of a hit to be rounded with respect to an input signal 1 to be rounded is input to a decoder circuit 3. The decoder circuit decodes the input signal 2 according to the truth tables of Tables 1 and 2 and outputs two output signals 4 and 5. For output signals 4 and 5, the most significant bit of input signal 1 is “0”.
”, then the output signal 4 is output, and the most significant bit of the input signal l is “
1'', output signal 5 is selected.The selected output signal and input signal 1 are added by arithmetic logic operator 8,
The result is output as a pressure signal 9.

次に本発明の第２の実施例について図面を参照して説明
する。全体のフロックは第１図と同一だが、デコーダ回
路が、第３図のように構成されている。Next, a second embodiment of the present invention will be described with reference to the drawings. The entire block is the same as in FIG. 1, but the decoder circuit is constructed as in FIG. 3.

第３図において、１，４，５，６，７，８．９は前実施
倒と同様のものであり、２は正の１６ビツトの値に対し
丸め演算に必要な１６ビツトの値、３は１６ビツトの入
力信号に対するテコート回路である。第３図において、
２１は１６ビツトの入力信号、２２は１６ビツトの入力
信号を１６ビツトの信号にデコードするデコーダ回路、
２３は１６ビツトの入力信号２１の出力信号、２４はデ
コーダ回路の出力信号である。また、デコーダ回路２４
の真理値表を第５図に示す。In Figure 3, 1, 4, 5, 6, 7, 8.9 are the same as in the previous implementation, 2 is the 16-bit value necessary for rounding operation for a positive 16-bit value, and 3 is a techo circuit for a 16-bit input signal. In Figure 3,
21 is a 16-bit input signal; 22 is a decoder circuit that decodes the 16-bit input signal into a 16-bit signal;
23 is an output signal of the 16-bit input signal 21, and 24 is an output signal of the decoder circuit. In addition, the decoder circuit 24
The truth table for is shown in Figure 5.

次に、本実施例における本発明の演算回路の動作につい
て述べる。Next, the operation of the arithmetic circuit of the present invention in this embodiment will be described.

丸め演算を行う入力信号１に対して丸めを行う加算に必
要な具体的な値を持つ入力信号２は、デコーダ回路３に
入力される。デコーダ回路は表３の真理値表に従い入力
信号２をデコートして２つの出力信号４，５を出力する
。出力信号４，５は、入力信号１の最上位ビットが０“
ならば出力信号４を、入力信号ｌの最上位ビットが１′
ならば出力信号５を選択する。選択された圧力信号と入
力信号１を算術論理演算器５によって加算を行い、その
結果を出力する。An input signal 2 having a specific value necessary for rounding addition to an input signal 1 performing a rounding operation is input to a decoder circuit 3 . The decoder circuit decodes the input signal 2 according to the truth table shown in Table 3 and outputs two output signals 4 and 5. For output signals 4 and 5, the most significant bit of input signal 1 is 0"
If the most significant bit of the input signal l is 1', then the output signal 4 is
If so, select output signal 5. The selected pressure signal and the input signal 1 are added together by the arithmetic and logic operator 5, and the result is output.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の演算回路を用いることに
より、１つの命令で丸めっきの演算を行えるので従来の
算術論理演算器を用いて行う場合よりも高速に演算でき
る効果がある。As explained above, by using the arithmetic circuit of the present invention, a rounding operation can be performed with one instruction, which has the effect of allowing faster arithmetic operations than when using a conventional arithmetic and logic unit.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例図、第２図は第１図のデコー
ダ回路の構成図、第３図は第２実施例によるデコーダ回
路の構成図、第４図は第２図のデコート出力を示す図、
第５図は第３図のデコード出力を示す図である。 １・・・・・・第１の入力信号、２・・・・・・第２の
入力信号、３・・・・・・デコーダ回路、４・・・・・
・第１のデコード出力信号、５・・・・・第２のデコー
ド出力信号、６・・・・・選択回路、７・・・・・・第
１の入力信号の最上位ビット、８・・・・・・算術論理
演算器、９・・・・・・算術論理演算器８力、１１・・
・・・・４ビツトの入力信号、１２・・・・・・第１の
デコーダ回路、１３・山・・第２のデコーダ回路、１４
・・・・・・第１のデコーダ回路の出力、ユ５・・・・
・・第２のデコーダ回路の出力、２１・川・・１６ビツ
トの入力信号、２２・・・・・・デコーダ回路、２３・
・・、＝　１６ビツトの入力信号の出力、２４・・・・
・・デコーダ回路の出力。 代理人　弁理士　　内　原　　　晋 第２図 第３図 第１凶 第１のグコータ出力 ｏｏｏｏｏｏｏθθ００００θθ１ ＱＱＱＯＱＯＱＯＯＯＯＯＯＯＩＯ ｏｏｏｏｏｏｏｏｏｏｏｏｏｒｏ。 ｏｏｏｏｏθ００００００　／　００００θｏｏｏｏｏ
ｏｏθｏｒｏｏｏ。 ｏｏｏｏｏｏｏｏｏｏｔθθ０００ ０００００００００７０００θθ０ ｏｏｏｏｏｏｏｏｒｏｏｏｏｏｏ。 Ｏθθ０００θ７００００００θ０ ｏｏｏｏｏθｒｏｏｏｏｏｏｏｏθ ０θθθ０１θＯＯθθｏｏｏｏ。 ００００１００θｏｏｏｏｏｏｏ。 ０００１００００００００θ０Ｏ０ ０１Ｏθｏｏｏｏｏθｏｏｏｏｏ。 ｒｏｏｏｏｏｏｏｏｏｏｏｏｏｏ。 第２Ｑテコータ出力 θθθθσσθθθθθ６θθθθ ｏｏｏｏｏｏｏｏｏｏｏθｏｏｏｒ ｏｏｏｏｏｏｏｏｏｏｏｏｏｏｔｔ ００ＤＯＯＯＯｏθθＯ０θＩＩＩ ＱＱＯＯθ００００θθｏｍ１ ｏｏｏｏｏｏｏｏｏｏｏｒｒ ００００θθ００００ｍ Ｏθｏｏｏｏｏｏｏ　ｔ ００００θ０００ ｏｏｏｏθ０Ｏ ｏｏｏｏｏθ ｏｏｏｏｒ θθθＩＨＴ　　　Ｈ＋　７ θθｍＴＩ　　　Ｊ　　Ｈ７ ＱｊｍＴＴ　Ｎｕ　　ＩＮ 第４　図 ｌ６ヒ゛ット０人ｆｌ信号 ｏｏｏｏｏｏｏｏｏｏθＯＯθθｌ θθＯＯθ０６０θθθＯθθｌＯ θθθＯθ０００θθθθθ／θθ ０θ０００θｏｏｏｏｏθ１θ００ ０００θＯθθ００００１０θ０θ θｏｏｏｏｏθ０θθ１θＯθθθ θθθＯθｏｏｏｏｔθ０００θθ θＯθθＯθｏｏｔｏｏｏθθＯθ ０θθ０θ００１θθθθｏｏｏｏ θθθθ００　１０００００００００ ０θｏｏｏｒθ０００００００θＯ ｏｏｏｏｔｏｏｏθθθｏｏｏｏｏ ｏｒｏｏｏｏθ０００００００００ １ｏｏｏｏθ００θθθ０ρθ０θ テコータ出力 ０θθθＯＯθＯ０θＯＯθθＯθ θ０θＯθθｏｏｏｏθＯθθθｌ θθθθθ０６θθθθθθθ１１ ０θ００θＯＯθθθθω１１７ θθθθ０００θＯθ００１１　７　７０θθθθθ０
００θθＩＨＩＩ θＯＯθθθ０θθＯＨ７ｍ Ｏθθ００００００１　１１１１１１ ０θＯθ００００１１１７１７　ＩＩ ０θ０００００　１　／　７　１　１１　１１０００θ
θｍｎｒｙｎｎ Ｏθ００１１７ｌｌｌｌｌｌｌｌ７ ０００１１／ＩＩＩｌ７１１１ｆｌ ０１１１１１ＮＩＩＩＩＩＩＨ 第 Ｓ ロFIG. 1 is a diagram of one embodiment of the present invention, FIG. 2 is a block diagram of the decoder circuit of FIG. 1, FIG. 3 is a block diagram of a decoder circuit according to the second embodiment, and FIG. Diagram showing the output,
FIG. 5 is a diagram showing the decoded output of FIG. 3. 1...First input signal, 2...Second input signal, 3...Decoder circuit, 4...
・First decode output signal, 5... Second decode output signal, 6... Selection circuit, 7... Most significant bit of the first input signal, 8... ...Arithmetic logic operator, 9...Arithmetic logic operator 8 power, 11...
...4-bit input signal, 12...First decoder circuit, 13. Mountain...Second decoder circuit, 14
...Output of the first decoder circuit, U5...
. . . Output of second decoder circuit, 21. River . . 16-bit input signal, 22 . . . Decoder circuit, 23.
..., = 16-bit input signal output, 24...
...Decoder circuit output. Agent Patent Attorney Susumu Uchihara Figure 2 Figure 3 Figure 1 First output ooooooo θθ0000θθ1 QQQOQOQOOOOOOIO ooooooooooooooro. oooooθ000000 / 0000θoooooo
ooθoroooo. oooooooooootθθ000 0000000007000θθ0 ooooooooooooooo Oθθ000θ7000000θ0 oooooθroooooooθ 0θθθ01θOOθθooooo. 0000100θoooooooo. 000100000000θ0O0 01Oθooooooθoooooo. rooooooooooooooo. 2nd Q Tecoator output θθθθσσθθθθθ6θθθθ oooooooooooooooooor oooooooooooooott 00DOOOOOoθθO0θIII QQOOθ0000θθom1 oooooooooorr 0000θθ0000m Oθoooooo o t 0000θ000 ooooθ0O ooooθ oooor θθθIHT H+ 7 θθmTI J H7 QjmTT Nu IN 4th Fig. 16 Hit 0 person fl signal oooooooooooθOOθθl θθOOθ060θθθOθθθ0 00θθθθθ/θθ 0θ000θoooooθ1θ00 000θOθθ000010θ0θ θoooooθ0θθ1θOθθθ θθθOθooootθ000θθ θOθθOθootoooθθOθ 0θθ0θ001θθθθooo θθθθ00 10000 00000 0θooorθ0000000θOooootoooθθθoooooo orooooθ000000000 1oooθ00θθθ0ρθ0θ Tecoator output 0θθθOOθO0θOOθθOθ θ0θOθθoooθOθθθl θθθθθ06θθθθθθ11 0θ00θOOθθθθω117 θθθθ000θOθ0011 7 7 0θθθθθ0
00θθIHII θOOθθθ0θθOH7m Oθθ0000001 111111 0θOθ0000111717 II 0θ00000 1 / 7 1 11 11000θ
θmnrynn Oθ00117llllllll7 00011/IIIl7111fl 011111NIIIIIIH Chapter S ro

Claims (1)

【特許請求の範囲】[Claims] ２の補数で表現される第１の入力信号と、前記第１の入
力信号の丸め位置を指定する第２の入力信号と、前記第
２の入力信号に基づき、丸め位置のビットが“１”でそ
れ以外は“０”であるような第１のデコード出力信号、
及び丸め位置のビットより下位のビットが全て“１”で
それ以外は“０”であるような第２のデコード出力信号
の２種類の出力信号を生成するデコード手段と、前記デ
コード手段から出力された２つの信号を前記第１の入力
信号の最上位ビットが“０”ならば前記第１のデコード
出力信号を選択し、前記第１の入力信号の最上位ビット
が“１”ならば前記第２のデコード出力信号を選択する
選択手段と、前記第１の入力信号と前記選択手段からの
出力信号を入力とし、加算を行う算術論理演算器を有し
、任意の丸め位置に対して正負対称の０捨１入丸めが行
える事を特徴とする丸め演算回路。A first input signal expressed in two's complement, a second input signal specifying the rounding position of the first input signal, and a bit at the rounding position is "1" based on the second input signal. and a first decoded output signal which is otherwise “0”;
and a second decode output signal in which all bits lower than the bits at the rounding position are "1" and the rest are "0"; If the most significant bit of the first input signal is "0", the first decoded output signal is selected, and if the most significant bit of the first input signal is "1", the second decoded signal is selected. a selection means for selecting the second decoded output signal; and an arithmetic and logic unit that receives the first input signal and the output signal from the selection means and performs addition; A rounding arithmetic circuit that is capable of rounding to the nearest zero.
JP2199552A 1990-07-27 1990-07-27 Rounding arithmetic circuit Pending JPH0484318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2199552A JPH0484318A (en) 1990-07-27 1990-07-27 Rounding arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2199552A JPH0484318A (en) 1990-07-27 1990-07-27 Rounding arithmetic circuit

Publications (1)

Publication Number Publication Date
JPH0484318A true JPH0484318A (en) 1992-03-17

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ID=16409728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2199552A Pending JPH0484318A (en) 1990-07-27 1990-07-27 Rounding arithmetic circuit

Country Status (1)

Country Link
JP (1) JPH0484318A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0562513A2 (en) * 1992-03-23 1993-09-29 Nec Corporation Rounding operation circuit
KR100462447B1 (en) * 1995-12-29 2005-05-11 톰슨 콘슈머 일렉트로닉스, 인코포레이티드 Apparatus symmetrically reducing "n" least siginficant bits of an m-bit digital signal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0562513A2 (en) * 1992-03-23 1993-09-29 Nec Corporation Rounding operation circuit
EP0562513A3 (en) * 1992-03-23 1993-10-20 Nec Corp Rounding operation circuit
KR100462447B1 (en) * 1995-12-29 2005-05-11 톰슨 콘슈머 일렉트로닉스, 인코포레이티드 Apparatus symmetrically reducing "n" least siginficant bits of an m-bit digital signal

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