JPH0480667A - Ac vector detector - Google Patents

Ac vector detector

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Publication number
JPH0480667A
JPH0480667A JP19463190A JP19463190A JPH0480667A JP H0480667 A JPH0480667 A JP H0480667A JP 19463190 A JP19463190 A JP 19463190A JP 19463190 A JP19463190 A JP 19463190A JP H0480667 A JPH0480667 A JP H0480667A
Authority
JP
Japan
Prior art keywords
polarity
integration
integrators
integrating
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19463190A
Other languages
Japanese (ja)
Inventor
Hitoshi Kitayoshi
均 北吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP19463190A priority Critical patent/JPH0480667A/en
Publication of JPH0480667A publication Critical patent/JPH0480667A/en
Pending legal-status Critical Current

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  • Measurement Of Resistance Or Impedance (AREA)

Abstract

PURPOSE:To enable improvement in stability and accuracy of measurement by providing a polarity switching means which make polarity of a phase detection output signal to be applied to an integrator invert at each integrating action to allow the removal of a dielectric absorption electric charge. CONSTITUTION:Integration voltages of integrators 5A and 5B are reset each time switches SHS3 and S6 are turned ON and this resetting cycle corresponds to one integration cycle. An integrating operation is performed when the SHS2 and S5 are ON while the S1 and S4 are OFF. When the integrating operation ends with the S2 and S5 turned ON back, the SHS8 of an polarity switch 9 is operated. Interlocking the switching, output signals of phase detectors 4A and 4B are inverted to negative from positive and as a result, an integration voltage is inverted in polarity at each action. The voltage integrated is converted 6 into digital from analog and an arithmetic device 7 performs a computation to average the preceding and present measured values. Thus, this switching of the polarity at each integrating action removes a dielectric absorption electric charge in integration capacitors C1 and C2. This also allows the canceling and removal of leak errors or the like by the averaging computation with the arithmetic device 7.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は各種の回路のインピーダンス特性、伝達特性
等を測定することに用いることができる交流ベクトル検
波装置に関する。
DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an AC vector detection device that can be used to measure impedance characteristics, transfer characteristics, etc. of various circuits.

[従来の技術〕 第4図に従来の交流ベクトル検波装置を示す。[Conventional technology] FIG. 4 shows a conventional AC vector detection device.

図中1は基準信号発生部を示す。この基準信号発生部1
から例えば正弦波の基準信号v、、、=Sinωtが測
定対象2に与えられる。
In the figure, 1 indicates a reference signal generating section. This reference signal generator 1
For example, a sine wave reference signal v, . . . =Sinωt is applied to the measurement object 2 from

測定対象2の応答出力信号はバッファ増幅器3を通して
位相検波器4A、4Bに入力される0位相検波器4A、
4Bの基準信号入力端子には基準信号発生部1から互に
直交する位相差を持つ、例えば正弦波sinωtと余弦
波cosωを又は直交する位相差を持つ方形波を与える
The response output signal of the measurement object 2 is inputted to the phase detectors 4A and 4B through the buffer amplifier 3.
To the reference signal input terminal 4B, a sine wave sin ωt and a cosine wave cos ω having mutually orthogonal phase differences, for example, or a square wave having orthogonal phase differences are applied from the reference signal generator 1.

位相検波器4A、4Bの検波出力は積分器5A。The detection outputs of the phase detectors 4A and 4B are sent to the integrator 5A.

5Bで積分され実数ベクトル成分VR,と、虚数ベクト
ル成分V1.とに分離され、スイッチS。
5B, the real vector component VR, and the imaginary vector component V1. and switch S.

で選択されてAD変換器6でAD変換され、演夏表示器
7で演頁し、インピーダンス特性等が算出され表示され
る。尚8は積分器5A、5Bを構成するスイッチS、−
S、及びスイ、7チS、を切替制御する制御器を示す。
It is selected, AD-converted by the AD converter 6, displayed on the summer display 7, and impedance characteristics etc. are calculated and displayed. Note that 8 indicates switches S, -, which constitute the integrators 5A and 5B.
This figure shows a controller that switches and controls S, SW, and 7-S.

「発明が解決しようとする課題」 積分器5A、5Bにおいて、積分開始に先だってスイッ
チS2及びS、がオンに制御され、積分コンデンサC1
及びC2の電荷を放電させ初期化する。
"Problem to be Solved by the Invention" In the integrators 5A and 5B, switches S2 and S are controlled to be turned on prior to the start of integration, and the integrating capacitor C1
And the charge of C2 is discharged and initialized.

然し乍ら、積分コンデンサC1及びC2は理想コンデン
サでないから初期化しても初期化以前の電圧値によって
誘電体吸収電荷が残り、この誘電体吸収電荷によって測
定の安定度を悪化させたり、精度を悪くさせる。
However, since the integrating capacitors C1 and C2 are not ideal capacitors, even if they are initialized, a dielectric absorption charge remains due to the voltage value before initialization, and this dielectric absorption charge deteriorates the stability and accuracy of measurement.

またリーク電流誤差、クロストーク誤差等も受は易い。It is also susceptible to leakage current errors, crosstalk errors, etc.

因みに実数ベクトル成分VR,と虚数ベクトル成分Vl
、は VR,=A−cos a+61 V [、=A−sinθ+ε2 で表わされ、C1,C2が誘電体吸収電荷及びリーク電
流誤差、クロストーク誤差の総和である。
Incidentally, the real vector component VR and the imaginary vector component Vl
, is expressed as VR,=A-cos a+61 V[,=A-sin θ+ε2, where C1 and C2 are the sum of dielectric absorption charge, leakage current error, and crosstalk error.

「課題を解決するための手段」 この発明では積分器に与える位相検波出力信号の極性を
1積分動作毎に反転させる極性切替手段を設ける。この
発明の構成によれば積分器に与えられる位相検波出力信
号の極性が1積分動作毎に反転されるから、積分器に積
分させる積分電圧は1積分動作毎に極性が反転する。
"Means for Solving the Problems" In the present invention, a polarity switching means is provided for inverting the polarity of the phase detection output signal given to the integrator every integration operation. According to the configuration of the present invention, the polarity of the phase detection output signal applied to the integrator is inverted every integration operation, so the polarity of the integral voltage integrated by the integrator is inverted every integration operation.

従って平均すると積分コンデンサに生しる誘電体吸収電
荷は除去され、またリーク電流誤差及びクロストーク誤
差も演算上で除去される。
Therefore, on average, the dielectric absorption charge generated in the integrating capacitor is removed, and leakage current errors and crosstalk errors are also removed in calculations.

よってこの発明によれば測定の安定度を向上させること
ができ、また測定精度を高めることができる。
Therefore, according to the present invention, the stability of measurement can be improved, and the measurement accuracy can also be improved.

「実施例」 第1図にこの発明の一実施例を示す。第1図において、
1は基準信号発生部、2は測定対象、3はバッファ増幅
器、4A、4Bは位相検波器、5A、5Bは積分器、6
はAD変換器、7は演算表示器、8は制御器を示す点は
従来の説明と同しである。
"Embodiment" FIG. 1 shows an embodiment of the present invention. In Figure 1,
1 is a reference signal generator, 2 is a measurement object, 3 is a buffer amplifier, 4A, 4B are phase detectors, 5A, 5B are integrators, 6
This is the same as the conventional explanation in that numeral 7 indicates an AD converter, 7 indicates a calculation display, and 8 indicates a controller.

この発明においては積分器5A、5Bに入力する位相検
波出力信号の極性を1積分動作毎に反転させる極性切替
手段7を設けた構成を特徴とするものである。
The present invention is characterized by a configuration in which a polarity switching means 7 is provided for inverting the polarity of the phase detection output signal input to the integrators 5A and 5B every integration operation.

つまりこの例ではバッファ増幅器3として差動出力型の
バッファ増幅器を用い、このバッファ増幅器3の出力側
に極性切替手段9を設けた場合を示す、この例では極性
切替手段9をスイッチS。
That is, in this example, a differential output type buffer amplifier is used as the buffer amplifier 3, and a polarity switching means 9 is provided on the output side of the buffer amplifier 3. In this example, the polarity switching means 9 is connected to a switch S.

によって構成した場合を示す、スイッチS、を積分器I
A、1Bの1積分動作毎に切替ることにより位相検波器
4Aと4Bの出力電圧の極性を切替ることかできる。
The switch S is configured as an integrator I.
The polarity of the output voltages of the phase detectors 4A and 4B can be switched by switching each integral operation of A and 1B.

第2図に各スイッチS、〜S、の動作と、積分器5A、
5Bの動作を示す、積分器5Aと5Bに設けたスイッチ
S!とS、及びSlとS、、S。
FIG. 2 shows the operation of each switch S, ~S, and the integrator 5A,
Switch S provided in integrators 5A and 5B shows the operation of 5B! and S, and Sl and S,,S.

とS、は第2図A、B、Cに示すように同時にオン、オ
フ動作し、積分器5Aと5Bは同時に積分とリセット動
作を繰返す。
and S are simultaneously turned on and off as shown in FIG. 2A, B, and C, and the integrators 5A and 5B simultaneously repeat the integration and reset operations.

つまりスイッチS、とShがオンになる毎に積分器5A
と5Bの積分電圧はリセットされる。このリセットの周
期Tが積分器5Aと5Bの1動作周期となる。積分動作
はスイッチS2とS、がオン、スイッチS1と34がオ
フの状態で実行される。
In other words, every time switches S and Sh are turned on, the integrator 5A
The integrated voltage of and 5B is reset. This reset cycle T is one operating cycle of the integrators 5A and 5B. The integration operation is performed with switches S2 and S on and switches S1 and 34 off.

極性切替手段9を構成するスイッチS、は第2図Eに示
すように積分器5Aと5Bを構成するスイッチS、とS
、がオンの状態に戻され積分動作が終了したタイミング
で切替られる。
The switch S constituting the polarity switching means 9 is connected to the switches S and S constituting the integrators 5A and 5B as shown in FIG. 2E.
, is returned to the on state and is switched at the timing when the integral operation is completed.

位相検波器4Aと4Bに入力される信号vllは第2図
Fに示すように極性切替手段9の切替によってA−si
n(ωt−+θ)と−A−sin(ωt、+θ)に極性
が切替られる。
The signal vll input to the phase detectors 4A and 4B is changed to A-si by switching the polarity switching means 9 as shown in FIG.
The polarity is switched to n(ωt-+θ) and -A-sin(ωt, +θ).

位相検波器4Aと4Bの位相検波出力は極性切替器9の
切替動作に連動して正と負に反転し、この結集積分器5
Aと5Bの積分電圧は第2図GとHに示すように1動作
毎に極性が反転する。
The phase detection outputs of the phase detectors 4A and 4B are reversed to positive and negative in conjunction with the switching operation of the polarity switch 9, and
The polarity of the integrated voltages A and 5B is reversed for each operation, as shown in FIG. 2, G and H.

スイッチS、により積分器5Aと5Bに積分させた電圧
VR,とVl、をAD変換器6に取込みAD変換し、そ
のAD変換結果を演夏器7に送り込む。
The voltages VR and Vl integrated by the integrators 5A and 5B by the switch S are taken into the AD converter 6 and subjected to AD conversion, and the result of the AD conversion is sent to the compensator 7.

演算器7では前回の測定値VR□、V11と今回の測定
値VR,2,V 1.zを平均化演算し真の実数部ベク
トル成分VR,と虚数部ベクトル成分V1、を算出する
The calculator 7 calculates the previous measured value VR□, V11 and the current measured value VR,2, V1. z is averaged and the true real part vector component VR and imaginary part vector component V1 are calculated.

VR−=y2CVR*+−VR−*) v 1.−’A (V 1.+−v r、z)(変形実
施例) 第3図にこの発明の変形実施例を示す。この例では極性
切替手段9として、位相検波器4Aと4Bに与える基準
信号の極性を反転さセるように構成した場合を示す。
VR-=y2CVR*+-VR-*) v 1. -'A (V 1.+-v r,z) (Modified Embodiment) FIG. 3 shows a modified embodiment of the present invention. In this example, a case is shown in which the polarity switching means 9 is configured to invert the polarity of the reference signal applied to the phase detectors 4A and 4B.

このように構成しても上述と同様に動作することは容易
に理解できよう。
It is easy to understand that even with this configuration, the operation is similar to that described above.

尚、上述の実施例では極性切替手段9の切替周期を積分
器5A、5Bの1積分周期毎として説明したが、必ずし
も1周期毎でなくてもよく、2〜3周期毎に切替えても
よい。
In the above embodiment, the switching period of the polarity switching means 9 was explained as being every one integration period of the integrators 5A and 5B, but it does not necessarily have to be every one period, and may be changed every two to three periods. .

「発明の効果」 以上説明したように、この発明によれば積分器5Aと5
Bの積分電圧の極性を1積分動作毎に切替るように構成
したがら、積分コンデンサc1と02の積分電圧は直流
的に0レヘルとなる。
"Effects of the Invention" As explained above, according to the present invention, the integrators 5A and 5
Since the polarity of the integrated voltage of B is configured to be switched for each integral operation, the integrated voltages of the integrating capacitors c1 and 02 become 0 leher in DC terms.

このために積分コンデンサclとCtに誘電体吸収が起
きることを阻止され、誘電体9収による誤差が除去され
る。
This prevents dielectric absorption from occurring in the integrating capacitors cl and Ct, and eliminates errors due to dielectric absorption.

また積分器5Aと5Bを構成する演算増幅器の電流加箕
点に流れ込むリークit流によるリーク誤差及びクロス
トーク誤差は演算器7において平均化演算により打消さ
れ除去される。
Further, leakage errors and crosstalk errors due to the leakage current flowing into the current addition point of the operational amplifiers constituting the integrators 5A and 5B are canceled out and removed by the averaging operation in the arithmetic unit 7.

従って、この発明によれば測定の安定度が向上し、精度
の高い交流ベクトル検波装置を提供することができる。
Therefore, according to the present invention, it is possible to improve measurement stability and provide a highly accurate AC vector detection device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す接続図、第2図は第
1図の動作を説明するための波形図、第3図はこの発明
の変形実施例を示す接続図、第4図は従来の技術を説明
するための接続図である。 1:基準信号発生部、2:測定対象、3:バッファ増幅
器、4A、4B:位相検波器、5A、5B;積分器、6
:AD変換器、7:演算器、8:制御器、 9:極性切替手段。
FIG. 1 is a connection diagram showing an embodiment of this invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, FIG. 3 is a connection diagram showing a modified embodiment of this invention, and FIG. 4 is a connection diagram for explaining a conventional technique. 1: Reference signal generator, 2: Measurement object, 3: Buffer amplifier, 4A, 4B: Phase detector, 5A, 5B; Integrator, 6
: AD converter, 7: Arithmetic unit, 8: Controller, 9: Polarity switching means.

Claims (1)

【特許請求の範囲】[Claims] (1)A、被測定回路に正弦波信号を与える基準信号発
生部と、 B、被測定回路の応答出力信号を互に直交する位相差を
持つ基準信号で位相検波する二つの位相検波器と、 C、二つの位相検波器の検波出力を積分する二つの積分
器と、 D、この二つの積分器の積分電圧を除算し、該測定回路
のインピーダンスを算出する演算器と、 E、上記二つの位相検波器の出力信号の極性を上記積分
器の積分動作毎に反転させる極性切替手段と、 によって構成した交流ベクトル検波装置。
(1) A: a reference signal generator that provides a sine wave signal to the circuit under test; and B: two phase detectors that detect the phase of the response output signal of the circuit under test using reference signals having mutually orthogonal phase differences. , C. Two integrators that integrate the detection outputs of the two phase detectors; D. An arithmetic unit that divides the integrated voltage of these two integrators and calculates the impedance of the measurement circuit; E. an AC vector detection device comprising: polarity switching means for inverting the polarity of the output signal of the two phase detectors for each integration operation of the integrator;
JP19463190A 1990-07-23 1990-07-23 Ac vector detector Pending JPH0480667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19463190A JPH0480667A (en) 1990-07-23 1990-07-23 Ac vector detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19463190A JPH0480667A (en) 1990-07-23 1990-07-23 Ac vector detector

Publications (1)

Publication Number Publication Date
JPH0480667A true JPH0480667A (en) 1992-03-13

Family

ID=16327729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19463190A Pending JPH0480667A (en) 1990-07-23 1990-07-23 Ac vector detector

Country Status (1)

Country Link
JP (1) JPH0480667A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7260481B1 (en) 2006-03-17 2007-08-21 Tanita Corporation Vector detecting device and living-body complex impedance measuring apparatus having the vector detecting device
JP2012032365A (en) * 2010-01-26 2012-02-16 Hioki Ee Corp Measuring apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7260481B1 (en) 2006-03-17 2007-08-21 Tanita Corporation Vector detecting device and living-body complex impedance measuring apparatus having the vector detecting device
JP2007248446A (en) * 2006-03-17 2007-09-27 Tanita Corp Vector detection device and living body complex impedance measuring device having same
JP2012032365A (en) * 2010-01-26 2012-02-16 Hioki Ee Corp Measuring apparatus

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