JPH0478181B2 - - Google Patents
Info
- Publication number
- JPH0478181B2 JPH0478181B2 JP25797186A JP25797186A JPH0478181B2 JP H0478181 B2 JPH0478181 B2 JP H0478181B2 JP 25797186 A JP25797186 A JP 25797186A JP 25797186 A JP25797186 A JP 25797186A JP H0478181 B2 JPH0478181 B2 JP H0478181B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- wiring
- conductor
- forming
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 63
- 239000000919 ceramic Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 24
- 229920001721 polyimide Polymers 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 23
- 239000010409 thin film Substances 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000009719 polyimide resin Substances 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 9
- 238000001035 drying Methods 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000010304 firing Methods 0.000 claims description 2
- 238000004528 spin coating Methods 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims 1
- 239000004642 Polyimide Substances 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000009833 condensation Methods 0.000 description 2
- 230000005494 condensation Effects 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は配線基板およびその製造方法に係り、
特にハイブリツドIC用の多層配線基板およびそ
の製造方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a wiring board and a method for manufacturing the same,
In particular, the present invention relates to a multilayer wiring board for hybrid ICs and a method for manufacturing the same.
（従来の技術）
近年、電子機器の小型軽量化、多機能化、高速
化、高信頼化等の要求の高まりに伴ない、アルミ
ナ等のセラミツクの多層配線基板上にICチツプ
や抵抗、コンデンサのようなチツプ部品を多数搭
載し、全体を金属製キヤツプで気密に封止した構
造のハイブリツドICが多用されてきている。(Conventional technology) In recent years, with the increasing demand for electronic devices to be smaller and lighter, more multifunctional, faster, and more reliable, IC chips, resistors, and capacitors are being mounted on multilayer wiring boards made of ceramics such as alumina. Hybrid ICs, which are equipped with a large number of chip components and are hermetically sealed with a metal cap, are being widely used.
そしてこのハイブリツドICに用いられるセラ
ミツク多層配線基板は、通常グリーンシート法、
厚膜、あるいは厚膜薄膜混成法のいずれかの方法
により、製造されている。 Ceramic multilayer wiring boards used in this hybrid IC are usually manufactured using the green sheet method.
It is manufactured by either a thick film method or a thick film/thin film hybrid method.
しかしながらこのようなセラミツク多層配線基
板は、絶縁体層が比較的大きな誘電率（ε）を有
するセラミツク（ε＝８〜10）や結晶化ガラス
（ε＝９〜20）で構成されているため、配線の浮
遊容量をあまり低く抑えることができず、搭載さ
れた素子の高速動作化を阻んでいる。 However, in such a ceramic multilayer wiring board, the insulating layer is made of ceramic (ε=8 to 10) or crystallized glass (ε=9 to 20), which has a relatively large dielectric constant (ε). It is not possible to suppress the stray capacitance of the wiring to a very low level, which hinders the high-speed operation of the mounted elements.
そこでこのような問題に対処するために最近高
速素子搭載用の配線基板として銅−ポリイミド多
層配線基板が開発されつつある。この配線基板
は、第４図に示すように厚さが1μｍ〜10μｍ程度
の薄膜導体パターン１とポリイミド層２とをセラ
ミツク基板３上に積層した構造を有し、次のよう
にして製造されている。 In order to deal with such problems, copper-polyimide multilayer wiring boards have recently been developed as wiring boards for mounting high-speed devices. As shown in FIG. 4, this wiring board has a structure in which a thin film conductor pattern 1 with a thickness of approximately 1 μm to 10 μm and a polyimide layer 2 are laminated on a ceramic substrate 3, and is manufactured as follows. There is.
すなわち、蒸着或いはスパツタリングにより銅
を主導体とした２ないし３種の導体の層をセラミ
ツク基板３の全面に形成させて後フオトリソグラ
フイ等により不要部分をエツチングし薄膜導体パ
ターン１を形成する第１の工程と、ポリイミドを
スピンコート乾燥した後、フオトリソグラフイに
より上下の導体パターン１間を電気的に接続する
通孔４を形成する第２の工程とを、繰返すことに
より製造されている。 That is, the first step is to form a layer of two or three types of conductors with copper as the main conductor on the entire surface of the ceramic substrate 3 by vapor deposition or sputtering, and then to etch unnecessary parts by photolithography or the like to form the thin film conductor pattern 1. It is manufactured by repeating the steps 1 and 2, and a second step of forming through holes 4 for electrically connecting the upper and lower conductive patterns 1 by photolithography after drying the polyimide by spin coating.
そしてこのような薄膜法により製造された銅−
ポリイミド多層配線基板は、絶縁体層を構成する
ポリイミド樹脂の誘電率が極めて低く（ε＝３〜
４）、しかも他の金属に比べて電気抵抗の小さな
銅により導体パターン１が形成されているため、
搭載された素子を高速動作させることができる。 And copper produced by such a thin film method -
In polyimide multilayer wiring boards, the dielectric constant of the polyimide resin that constitutes the insulator layer is extremely low (ε=3 to
4) Moreover, since the conductor pattern 1 is made of copper, which has a lower electrical resistance than other metals,
The mounted elements can be operated at high speed.
（発明が解決しようとする問題点）
しかしながらこのような配線基板においては、
ポリイミド樹脂が吸湿性を有するため、この上に
ICチツプ等を搭載して金属製キヤツプ等で気密
に封止した場合、ポリイミド層２の厚さ方向から
湿気が搭載領域内に侵入してしまう。(Problems to be solved by the invention) However, in such a wiring board,
Since polyimide resin has hygroscopic properties,
When an IC chip or the like is mounted and hermetically sealed with a metal cap or the like, moisture will enter the mounting area from the direction of the thickness of the polyimide layer 2.
そして、この湿気がマイグレーシヨンによる多
層配線部の短絡事故、ICやワイヤの腐蝕事故、
或いは温度サイクル試験時の結露による短絡事故
を引き起こすという問題があつた。 This moisture can cause short circuits in multilayer wiring due to migration, corrosion of ICs and wires, etc.
Another problem was that dew condensation during temperature cycle tests caused short circuits.
本発明はこれらの問題を解決するためになされ
たもので、耐湿性が改善され気密に封止された領
域内への湿気の侵入がなく、しかも信頼性が高く
高速動作が可能なハイブリツドIC用などの多層
配線基板およびその製造方法を提供することを目
的とする。 The present invention was made to solve these problems, and is intended for use in hybrid ICs that have improved moisture resistance, prevents moisture from entering hermetically sealed areas, and are highly reliable and capable of high-speed operation. The purpose of the present invention is to provide a multilayer wiring board and a method for manufacturing the same.
［発明の構成］
（問題点を解決するための手段）
本発明の配線基板は、セラミツク基板と、この
セラミツク基板の所定面中央部に配設された低誘
電率絶縁材料を絶縁体層としてCu系導体パター
ンを多層的に有する多層配線部と、前記セラミツ
ク基板の所定面周辺部に前記多層配線部に対し離
間して形設された入出力パツドと、この入出力パ
ツドと一体をなし一端が多層配線部の端子にそれ
ぞれ電気的に接続された導電配線パターンと、こ
の導電配線パターンの少なくとも一部をそれぞれ
被覆しながらかつ前記多層配線部を囲繞するよう
前記セラミツク基板の所定面に環状に形設された
耐湿性材料からなる絶縁体層と、この絶縁体層上
に形設された環状導電体層と、前記多層配線部を
覆うように基部が前記環状導電体層に取着された
導電性キヤツプとを具備することを特徴としてい
る。[Structure of the Invention] (Means for Solving the Problems) The wiring board of the present invention includes a ceramic substrate and a low dielectric constant insulating material disposed at the center of a predetermined surface of the ceramic substrate as an insulator layer. a multilayer wiring section having system conductor patterns in multiple layers; an input/output pad formed on the periphery of a predetermined surface of the ceramic substrate at a distance from the multilayer wiring section; conductive wiring patterns each electrically connected to the terminals of the multilayer wiring section; and an annular shape formed on a predetermined surface of the ceramic substrate so as to cover at least a portion of each of the conductive wiring patterns and to surround the multilayer wiring section. an insulator layer made of a moisture-resistant material, an annular conductor layer formed on the insulator layer, and a conductor whose base is attached to the annular conductor layer so as to cover the multilayer wiring section. It is characterized by having a sexual cap.
また本発明の配線基板の製造方法は、セラミツ
ク基板の所定面周辺部に入出力パツドを厚膜法に
より形成する工程と、一端が前記入出力パツドに
接続されかつ前記セラミツク基板の所定面中央部
に向かう導体配線パターンを厚膜法により形成す
る工程と、前記導電配線パターンの少なくとも一
部をそれぞれ被覆しながらかつ前記セラミツク基
板の所定面中央部を囲繞するように環状に結晶化
ガラスからなる絶縁体層を形成する工程と、前記
絶縁体層上に環状導電体層を厚膜法により形成す
る工程と、前記セラミツク基板の所定面中央部に
ポリイミド樹脂を絶縁体層とし端子が前記入出力
パツドの他端に接続されるCu系導体パターンを
多層的に有する多層配線部を薄膜法により形成す
る工程と、前記多層配線部を覆うように導電性キ
ヤツプの基部を前記環状導電体層に取着する工程
とからなることを特徴としている。 Further, the method for manufacturing a wiring board of the present invention includes a step of forming an input/output pad on the periphery of a predetermined surface of the ceramic substrate by a thick film method, and a step of forming an input/output pad on the periphery of a predetermined surface of the ceramic substrate with one end connected to the input/output pad and a central portion of the predetermined surface of the ceramic substrate. a step of forming a conductive wiring pattern by a thick film method, and forming an annular insulator made of crystallized glass so as to cover at least a part of the conductive wiring pattern and surrounding a central part of a predetermined surface of the ceramic substrate. forming an annular conductive layer on the insulating layer by a thick film method; and forming a polyimide resin as an insulating layer in the center of a predetermined surface of the ceramic substrate, and forming a terminal on the input/output pad. A step of forming a multilayer wiring section having a multilayered Cu-based conductor pattern connected to the other end by a thin film method, and attaching a base of a conductive cap to the annular conductor layer so as to cover the multilayer wiring section. It is characterized by the process of
（作用）
本発明の配線基板においては、金属製キヤツプ
取着用のシールリングパターンとなる環状導電体
層と、入出力パツド、およびこれらの入出力パツ
ドと内部配線とを電気的に接続するための導電配
線パターンが厚膜法により形成されており、シー
ルリングパターンの内側のセラミツク基板上に薄
膜法により導体パターンとポリイミド樹脂からな
る絶縁体層とが交互に積層された銅−ポリイミド
多層配線部が設けられている。(Function) The wiring board of the present invention has an annular conductive layer that serves as a seal ring pattern for attaching a metal cap, an input/output pad, and a layer for electrically connecting these input/output pads and internal wiring. The conductive wiring pattern is formed by the thick film method, and the copper-polyimide multilayer wiring part is formed by alternately laminating the conductor pattern and the insulating layer made of polyimide resin by the thin film method on the ceramic substrate inside the seal ring pattern. It is provided.
従つて、セラミツクに比べて誘電率が極めて低
いポリイミド樹脂で絶縁体層が構成されているこ
とにより、高速動作が可能となる。 Therefore, high-speed operation is possible because the insulating layer is made of polyimide resin, which has a much lower dielectric constant than ceramic.
また、多層配線部が導電性キヤツプで気密に封
止されて外気に直接触れることがなく、しかもシ
ールリングパターンより外側の絶縁体層がセラミ
ツク及び結晶化ガラスで構成されており、これか
ら厚さ方向に湿気が侵入してくることがないの
で、短絡腐蝕事故等が発生することがなく、信頼
性の高いハイブリツドICが得られる。 In addition, the multilayer wiring section is hermetically sealed with a conductive cap so that it does not come into direct contact with the outside air, and the insulator layer outside the seal ring pattern is made of ceramic and crystallized glass, and from this point on in the thickness direction. Since moisture does not enter into the IC, short-circuit corrosion accidents do not occur, and a highly reliable hybrid IC can be obtained.
さらに、環状導電体層や入出力パツド等の導体
厚膜を、特にハンダぬれ性が良好でハンダとの拡
散速度の速い導体ペーストの印刷、乾燥、焼成に
より形成された場合には、これらの上に導電性キ
ヤツプや入出力リードあるいは入出力ピンをハン
ダ等により固着した場合の固着力が大きく、ハン
ダ溶着作業が簡単であるという利点がある。 Furthermore, if a thick conductor film such as an annular conductor layer or input/output pad is formed by printing, drying, and baking a conductor paste that has good solder wettability and a fast diffusion rate with solder, Another advantage is that when the conductive cap, input/output lead, or input/output pin is fixed with solder, the fixing force is large and the soldering work is easy.
（実施例）
以下、本発明の実施例を図面に基づいて説明す
る。(Example) Hereinafter, an example of the present invention will be described based on the drawings.
第１図および第２図は、それぞれ本発明の配線
基板の一実施例を示す斜視図および要部拡大断面
図である。 FIG. 1 and FIG. 2 are a perspective view and an enlarged sectional view of essential parts, respectively, showing an embodiment of the wiring board of the present invention.
これらの図において符号５はアルミナ等のセラ
ミツクからなる基板を示し、このセラミツク基板
５表面の周辺部には、複数の入出力導体パツド６
とこれらの入出力導体パツド６から内側に向かつ
てそれぞれ延出された複数本の比較的短尺の導体
パターン７とが、以下に示す厚膜法によりそれぞ
れ整列して形成されている。 In these figures, reference numeral 5 indicates a substrate made of ceramic such as alumina, and a plurality of input/output conductor pads 6 are provided at the peripheral portion of the surface of the ceramic substrate 5.
and a plurality of relatively short conductor patterns 7 extending inward from these input/output conductor pads 6 are formed in alignment by the thick film method described below.
すなわちこれらの厚膜導体は、Cuペースト、
Ag−Ptペースト、Au−Ptペースト、Ag−Pdペ
ーストのような、ハンダぬれ性が良くかつハンダ
との拡散速度が比較的速い導体ペーストを、５〜
20μｍの厚さにスクリーン印刷し続いて乾燥、焼
成することによつて形成されている。 In other words, these thick film conductors are made of Cu paste,
Conductive pastes such as Ag-Pt paste, Au-Pt paste, and Ag-Pd paste, which have good solder wettability and a relatively fast diffusion rate with solder, are used for 5 to 50 minutes.
It is formed by screen printing to a thickness of 20 μm, followed by drying and baking.
またこうして形成された入出力導体パツド６列
の内側には、短尺の厚膜導体パターン７の両端部
をそれぞれ露出させ中央部のみを被覆するような
幅のリング状の絶縁体層８が、結晶化ガラスペー
ストを印刷、乾燥、焼成することによつて形成さ
れている。 Also, inside the six rows of input/output conductor pads formed in this way, a ring-shaped insulating layer 8 with a width that exposes both ends of the short thick film conductor pattern 7 and covers only the central part is provided. It is formed by printing, drying, and firing a chemically modified glass paste.
さらにこのリング状の絶縁体層８の上にはこれ
と相似形でこれよりいくらか幅の狭いリング状の
導体パターン９が、前述の厚膜導体ペーストを同
様にして印刷、乾燥、焼成することにより形成さ
れている。 Further, on this ring-shaped insulating layer 8, a ring-shaped conductor pattern 9 having a similar shape but slightly narrower than this is formed by printing, drying, and baking the above-mentioned thick film conductor paste in the same manner. It is formed.
またさらにこのようなリング状の厚膜導体パタ
ーン９の内側のセラミツク基板５表面には、銅を
主導体とした２ないし３種の導体からなる厚さが
1μ〜10μ程度の薄膜導体パターン１０と同程度の
厚さのポリイミド層１１とを、以下に示すような
薄膜法により交互に積層してなる銅−ポリイミド
多層配線部１２が設けられている。 Further, on the surface of the ceramic substrate 5 inside such a ring-shaped thick film conductor pattern 9, there is a thickness consisting of two or three types of conductors with copper as the main conductor.
A copper-polyimide multilayer wiring section 12 is provided in which a thin film conductor pattern 10 of about 1 to 10 microns and a polyimide layer 11 of about the same thickness are alternately laminated by a thin film method as described below.
すなわちこの多層配線部１２は、まずリング状
の導体パターン９の内側のセラミツク基板５上に
銅を主導体とした２ないし３種の導体、たとえば
Cr／Cu、Ti／Cu、Cr／Cu／Cr、Ti／Cu／Cr、
Cr／Cu／Au、Ti／Cu／Au等の導体を、蒸着或
いはスパツタリングすることにより薄膜を形成し
た後、フオトリソグラフイにより不要の部分をエ
ツチングすることにより第１層目の薄膜導体パタ
ーン１０を形成する。そしてこの第１層目の薄膜
導体パターン１０においては、これらの端部を短
尺の厚膜導体パターン７の全内側端部上に重ね合
わせて形成し、短尺の厚膜導体パターン７を介し
て入出力導体パツド６と多層配線部とが電気的に
接続されるように構成する。 In other words, this multilayer wiring section 12 is constructed by first disposing two or three types of conductors, for example copper as the main conductor, on the ceramic substrate 5 inside the ring-shaped conductor pattern 9.
Cr/Cu, Ti/Cu, Cr/Cu/Cr, Ti/Cu/Cr,
After forming a thin film by vapor depositing or sputtering a conductor such as Cr/Cu/Au, Ti/Cu/Au, etc., the first layer thin film conductor pattern 10 is formed by etching unnecessary parts using photolithography. Form. In the first layer thin film conductor pattern 10, these ends are formed so as to overlap the entire inner end of the short thick film conductor pattern 7, and the conductor is inserted through the short thick film conductor pattern 7. The output conductor pad 6 and the multilayer wiring section are configured to be electrically connected.
このように形成された薄膜導体パターン１０上
に、有機材料であるポリイミド樹脂をスピンコー
トし乾燥硬化させてポリイミド層１１を形成した
後、フオトリソグラフイによりエツチングを行つ
て導体パターン１０間を電気的に接続するための
通孔１３を形成する。 A polyimide resin, which is an organic material, is spin-coated on the thin film conductor pattern 10 formed in this way, dried and hardened to form a polyimide layer 11, and then etched by photolithography to electrically connect the conductor patterns 10. A through hole 13 is formed for connection to.
このような工程を繰返し薄膜導体パターン１０
とポリイミド層１１とを所定の数だけ交互に積層
し、さらに最上層の薄膜導体部に、ICチツプの
ような能動素子や抵抗、コンデンサのような受動
素子を搭載するための複数のダイパツド１４と、
ボンデイングワイヤを介して、搭載された能動素
子と多層配線部１２とを電気的に接続するための
複数のアウターリードボンデイングパツド
（OLB）１５とを形成することにより銅−ポリイ
ミド多層配線部１２が完成する。 These steps are repeated to form the thin film conductor pattern 10.
A predetermined number of polyimide layers 11 and 11 are alternately laminated, and a plurality of die pads 14 for mounting active elements such as IC chips and passive elements such as resistors and capacitors are further formed on the thin film conductor portion of the uppermost layer. ,
The copper-polyimide multilayer wiring section 12 is formed by forming a plurality of outer lead bonding pads (OLB) 15 for electrically connecting the mounted active elements and the multilayer wiring section 12 via bonding wires. Complete.
このように構成される実施例の配線基板上に
は、通常次のようにして素子が搭載され、ハイブ
リツドICが製作される。 On the wiring board of the embodiment configured as described above, elements are usually mounted in the following manner to produce a hybrid IC.
すなわち、第３図に示すように、多層配線部１
２のダイパツド１４上には、ICチツプ１６や抵
抗等（図示を省略。）がそれぞれ導電性エポキシ
１７のような接着剤で接着され、これらのICチ
ツプ１６とOLB１５との間は、Au線やAl線のよ
うなボンデイングワイヤ１８により電気的に接続
される。そしてリング状の厚膜導体パターン９の
上には、コバールやFe／Ni42アロイのようなセ
ラミツクと熱膨脹係数がほぼ等しい金属からなる
キヤツプ１９がSn／Pb63／37合金のような共晶
ハンダ２０により固着され、ICチツプ１６等が
搭載された領域はヘリウムや窒素のような不活性
ガス２１が封入された状態で気密に封止される。 That is, as shown in FIG.
On the die pad 14 of No. 2, an IC chip 16, a resistor, etc. (not shown) are bonded with adhesive such as conductive epoxy 17, and between these IC chips 16 and OLB 15, Au wire or Electrical connection is made by a bonding wire 18 such as an Al wire. On top of the ring-shaped thick film conductor pattern 9, a cap 19 made of a metal having a coefficient of thermal expansion approximately equal to that of ceramic such as Kovar or Fe/Ni42 alloy is attached using eutectic solder 20 such as Sn/Pb63/37 alloy. The area where the IC chip 16 and the like are mounted is hermetically sealed with an inert gas 21 such as helium or nitrogen filled therein.
さらに入出力導体パツド６上には、共晶ハンダ
等を用いてクリツプリード等の入出力リードや入
出力ピン（図示を省略。）が固着される。 Furthermore, input/output leads such as clip leads and input/output pins (not shown) are fixed onto the input/output conductor pad 6 using eutectic solder or the like.
従つて、実施例の配線基板を用いこのようにし
て構成されるハイブリツドICにおいては、ICチ
ツプ１６等が搭載される領域の絶縁体層が、セラ
ミツクや結晶化ガラスと比べて非常に低い誘電率
を有するポリイミド樹脂で構成されているので、
配線の浮遊容量を小さくすることができ、動作の
高速化が進められる。 Therefore, in the hybrid IC constructed in this way using the wiring board of the embodiment, the insulator layer in the area where the IC chip 16 etc. are mounted has a dielectric constant that is very low compared to ceramic or crystallized glass. Since it is composed of polyimide resin with
The stray capacitance of the wiring can be reduced, leading to faster operation.
またこのようなICチツプ１６等が搭載された
領域が金属製キヤツプ１９で気密に封止されてお
り、かつ金属製キヤツプ１９の外側に露出した周
辺部の絶縁体層は、耐湿性の高いセラミツク及び
結晶化ガラスで構成されているので、金属製キヤ
ツプ１９内部の搭載領域への湿気の侵入がなく、
マイグレーシヨン、ワイヤ腐蝕、結露事故等が全
く発生することがない。 Furthermore, the area where the IC chip 16 and the like are mounted is hermetically sealed with a metal cap 19, and the insulator layer in the peripheral area exposed to the outside of the metal cap 19 is made of highly moisture-resistant ceramic material. and crystallized glass, there is no moisture intrusion into the mounting area inside the metal cap 19.
No migration, wire corrosion, dew condensation, etc. will occur.
さらに、リング状の厚膜導体パターン９と入出
力導体パツド６とが、いずれもSn−Pb系のハン
ダとのぬれ性が良くかつハンダとの拡散速度の速
い導体の厚膜で構成されているので、これらの上
に金属製キヤツプ１９あるいは入出力リード等を
ハンダ２０により強固に固着することができる。 Further, the ring-shaped thick film conductor pattern 9 and the input/output conductor pad 6 are both made of a thick film of a conductor that has good wettability with Sn-Pb solder and a fast diffusion rate with the solder. Therefore, metal caps 19, input/output leads, etc. can be firmly fixed onto these with solder 20.
［発明の効果］
以上説明から明らかなように、本発明の配線基
板およびその製造方法によれば、気密に封止され
た素子の搭載領域内への湿気の侵入がなく、短絡
腐蝕事故等が発生せず、しかも信頼性が高く素子
の高速動作が可能なハイブリツドICを提供する
ことができる。[Effects of the Invention] As is clear from the above explanation, according to the wiring board and the manufacturing method thereof of the present invention, there is no intrusion of moisture into the hermetically sealed mounting area of the element, and accidents such as short circuit corrosion can be avoided. Therefore, it is possible to provide a hybrid IC that does not generate any problems, has high reliability, and is capable of high-speed operation of the device.
第１図および第２図はそれぞれ本発明の配線基
板の一実施例を示す斜視図および要部拡大断面
図、第３図は実施例の配線基板を用いて製作した
ハイブリツドICの要部拡大断面図、第４図は従
来の銅−ポリイミド多層配線基板の断面図であ
る。
５……セラミツク基板、６……入出力導体パツ
ド、７……短尺の厚膜導体パターン、８……リン
グ状の絶縁体層、９……リング状の厚膜導体パタ
ーン、１０……薄膜導体パターン、１１……ポリ
イミド層、１２……多層配線部、１３……通孔、
１４……ダイパツド、１５……OLB、１６……
ICチツプ、１９……金属製キヤツプ、２０……
ハンダ。
1 and 2 are a perspective view and an enlarged cross-sectional view of the main parts of an embodiment of the wiring board of the present invention, respectively, and FIG. 3 is an enlarged cross-section of the main parts of a hybrid IC manufactured using the wiring board of the embodiment. 4 are cross-sectional views of a conventional copper-polyimide multilayer wiring board. 5... Ceramic substrate, 6... Input/output conductor pad, 7... Short thick film conductor pattern, 8... Ring-shaped insulator layer, 9... Ring-shaped thick film conductor pattern, 10... Thin film conductor pattern, 11... polyimide layer, 12... multilayer wiring section, 13... through hole,
14...Daipatsudo, 15...OLB, 16...
IC chip, 19...Metal cap, 20...
Solder.
Claims (1)
た低誘電率絶縁材料を絶縁体層としてCu系導体
パターンを多層的に有する多層配線部と、 前記セラミツク基板の所定面周辺部に前記多層
配線素子に対し離間して形設された入出力パツド
と、 この入出力パツドと一体をなし前記多層配線部
の一端が多層配線部の端子に電気的に接続された
導電配線パターンと、 この導電配線パターンの少なくとも一部をそれ
ぞれ被覆しながらかつ前記多層配線素子を囲繞す
るよう前記セラミツク基板の所定面に環状に形設
された耐湿性材料からなる絶縁体層と、 この絶縁体層上に形設された環状導電体層と、 前記多層配線素子を覆うように基部が前記環状
導電体層に取着された導電性キヤツプと、 を具備することを特徴とする配線基板。 ２ セラミツク基板が、アルミナからなる基板で
ある特許請求の範囲第１項記載の配線基板。 ３ Cu系導体パターンが、Cr／Cu、Ti／Cu、
Cr／Cu／Cr、Ti／Cu／Ti、Cr／Cu／Au、或い
はTi／Cu／Auである特許請求の範囲第１項記載
の配線基板。 ４ 多層配線部を構成するCu系導体パターンの
最下層のCu系導体パターンの端部が、導電配線
パターンの他端に重ね合わせられて電気的に接続
されている特許請求の範囲第１項記載の配線基
板。 ５ 低誘電率絶縁材料が、ポリイミド樹脂である
特許請求の範囲第１項記載の配線基板。 ６ 耐湿性材料が、結晶化ガラスである特許請求
の範囲第１項記載の配線基板。 ７ 導電性キヤツプが、金属製キヤツプである特
許請求の範囲第１項記載の配線基板。 ８ 環状導電体層が、導電性キヤツプを取着する
ためのシーリングパターンである特許請求の範囲
第１項記載の配線基板。 ９ セラミツク基板の所定面周辺部に入出力パツ
ドと一端がセラミツク基板の所定面中央部に向か
う導体配線パターンとを厚膜法により形成する工
程と、 前記導電配線パターンの少なくとも一部をそれ
ぞれ被覆しながらかつ前記セラミツク基板の所定
面中央部を囲繞するように環状に結晶化ガラスか
らなる絶縁体層を形成する工程と、 前記絶縁体層上に環状導電体層を厚膜法により
形成する工程と、 前記セラミツク基板の所定面中央部にポリイミ
ド樹脂を絶縁体層とし端子が前記導体配線パター
ンの他端に接続されるCu系導体パターンを多層
的に有する多層配線部を薄膜法により形成する工
程と、 前記多層配線部を覆うように導電性キヤツプの
基部を前記環状導電体層に取着する工程と、 からなることを特徴とする配線基板の製造方法。 １０ 入出力パツド、導体配線パターンおよび環
状導電体層を形成する工程は、それぞれハンダぬ
れ性が良くかつハンダとの拡散速度の速い厚膜導
体ペーストを印刷、乾燥、焼成してなるものであ
る特許請求の範囲第９項記載の配線基板の製造方
法。 １１ 絶縁体層を形成する工程は、厚膜結晶化ガ
ラスペーストを印刷、乾燥、焼成してなるもので
ある特許請求の範囲第９項記載の配線基板の製造
方法。 １２ Cu系導体パターンを形成する工程は、
Cr／Cu、Ti／Cu、Cr／Cu／Cr、Ti／Cu／Ti、
Cr／Cu／Au、或いはTi／Cu／Auからなる薄膜
を蒸着或いはスパツタリングし、フオトリソグラ
フイにより不要成分をエツチングしてなるもので
ある特許請求の範囲第９項記載の配線基板の製造
方法。 １３ ポリイミド樹脂の絶縁体層を形成する工程
は、スピンコートによりポリイミド樹脂の薄膜を
形成し、フオトリソグラフイによりエツチングし
てなるものである特許請求の範囲第９項記載の配
線基板の製造方法。[Scope of Claims] 1. A ceramic substrate; a multilayer wiring section having Cu-based conductor patterns in multiple layers using a low dielectric constant insulating material as an insulating layer disposed at the center of a predetermined surface of the ceramic substrate; an input/output pad formed on the periphery of a predetermined surface of the board at a distance from the multilayer wiring element; and an input/output pad that is integral with the input/output pad, and one end of the multilayer wiring section is electrically connected to a terminal of the multilayer wiring section. an insulating layer made of a moisture-resistant material formed in a ring shape on a predetermined surface of the ceramic substrate so as to cover at least a portion of the conductive wiring pattern and to surround the multilayer wiring element; an annular conductor layer formed on the insulator layer; and a conductive cap having a base attached to the annular conductor layer so as to cover the multilayer wiring element. wiring board. 2. The wiring board according to claim 1, wherein the ceramic substrate is a substrate made of alumina. 3 Cu-based conductor patterns include Cr/Cu, Ti/Cu,
The wiring board according to claim 1, which is Cr/Cu/Cr, Ti/Cu/Ti, Cr/Cu/Au, or Ti/Cu/Au. 4. Claim 1, wherein the end of the lowest layer of the Cu-based conductor pattern constituting the multilayer wiring section is superimposed on and electrically connected to the other end of the conductive wiring pattern. wiring board. 5. The wiring board according to claim 1, wherein the low dielectric constant insulating material is a polyimide resin. 6. The wiring board according to claim 1, wherein the moisture-resistant material is crystallized glass. 7. The wiring board according to claim 1, wherein the conductive cap is a metal cap. 8. The wiring board according to claim 1, wherein the annular conductive layer is a sealing pattern for attaching a conductive cap. 9. Forming an input/output pad on the periphery of a predetermined surface of the ceramic substrate and a conductive wiring pattern with one end facing toward the center of the predetermined surface of the ceramic substrate by a thick film method, and covering at least a portion of the conductive wiring pattern, respectively. a step of forming an annular insulator layer made of crystallized glass so as to surround a central portion of a predetermined surface of the ceramic substrate; and a step of forming an annular conductor layer on the insulator layer by a thick film method. , a step of forming a multilayer wiring part using a thin film method in the center of a predetermined surface of the ceramic substrate, the multilayer wiring part having a polyimide resin as an insulating layer and a multilayer Cu-based conductor pattern whose terminal is connected to the other end of the conductor wiring pattern; A method for manufacturing a wiring board, comprising the steps of: attaching a base portion of a conductive cap to the annular conductor layer so as to cover the multilayer wiring portion. 10 The process of forming input/output pads, conductor wiring patterns, and annular conductor layers is a patent that involves printing, drying, and baking thick film conductor pastes that have good solder wettability and a fast diffusion rate with solder. A method for manufacturing a wiring board according to claim 9. 11. The method of manufacturing a wiring board according to claim 9, wherein the step of forming the insulator layer is performed by printing, drying, and firing a thick film crystallized glass paste. 12 The process of forming a Cu-based conductor pattern is as follows:
Cr/Cu, Ti/Cu, Cr/Cu/Cr, Ti/Cu/Ti,
10. The method of manufacturing a wiring board according to claim 9, wherein a thin film of Cr/Cu/Au or Ti/Cu/Au is deposited or sputtered, and unnecessary components are etched by photolithography. 13. The method of manufacturing a wiring board according to claim 9, wherein the step of forming the insulating layer of polyimide resin is performed by forming a thin film of polyimide resin by spin coating and etching by photolithography.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25797186A JPS63110755A (en) | 1986-10-29 | 1986-10-29 | Wiring substrate and manufacture thereof |
| EP87309593A EP0266210B1 (en) | 1986-10-29 | 1987-10-29 | Electronic apparatus comprising a ceramic substrate |
| DE8787309593T DE3784213T2 (en) | 1986-10-29 | 1987-10-29 | ELECTRONIC APPARATUS WITH A CERAMIC SUBSTRATE. |
| US07/817,996 US5153709A (en) | 1986-10-29 | 1992-01-09 | Electronic apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25797186A JPS63110755A (en) | 1986-10-29 | 1986-10-29 | Wiring substrate and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63110755A JPS63110755A (en) | 1988-05-16 |
| JPH0478181B2 true JPH0478181B2 (en) | 1992-12-10 |
Family
ID=17313757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25797186A Granted JPS63110755A (en) | 1986-10-29 | 1986-10-29 | Wiring substrate and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63110755A (en) |
-
1986
- 1986-10-29 JP JP25797186A patent/JPS63110755A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63110755A (en) | 1988-05-16 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |