JPH0474865B2 - - Google Patents
Info
- Publication number
- JPH0474865B2 JPH0474865B2 JP61054424A JP5442486A JPH0474865B2 JP H0474865 B2 JPH0474865 B2 JP H0474865B2 JP 61054424 A JP61054424 A JP 61054424A JP 5442486 A JP5442486 A JP 5442486A JP H0474865 B2 JPH0474865 B2 JP H0474865B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- etching
- photoresist
- sides
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 52
- 238000005530 etching Methods 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 14
- 230000001681 protective effect Effects 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000011888 foil Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 11
- 239000007921 spray Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 230000007261 regionalization Effects 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体素子などの電子部品素子の電
極と外部基板との電気的接続を得るために使用す
る基板への電気的接続用突起の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming electrical connection protrusions on a substrate used to obtain electrical connection between an electrode of an electronic component element such as a semiconductor element and an external substrate. Regarding the manufacturing method.
従来、たとえばテープキヤリア基板のインナー
リードへの電気的接続用突起の製造方法として
は、特開昭59−17981の様に、第2図に示す如く、
(a) 導体層2の表面に保護レジスト71を塗布す
る工程と
(b) 導体層2の裏面にフオトレジスト3塗布、露
光、現像、ハーフエツチングからなる突起6を
形成する工程と、
(c) 導体層2の表・裏面の保護レジスト71とフ
オトレジスト3を剥離する工程と
(d) 導体層2の表面にフオトレジスト31塗布、
露光、現像からなるパターニングする工程と
(e) 導体層2の裏面に保護レジスト72を塗布す
る工程と
(f) 導体層2の表面をエツチングしてインナーリ
ード8を含む回路パターンを形成する工程と
(g) 導体層2の表・裏面のフオトレジスト31と
保護レジスト72を剥離する工程により、イン
ナーリード8の裏面に突起6を製造していた。
Conventionally, as shown in FIG. 2, as shown in Japanese Patent Application Laid-Open No. 59-17981, as a method for manufacturing a protrusion for electrical connection to the inner lead of a tape carrier board, for example, (a) a protective resist is coated on the surface of the conductor layer 2. (b) forming protrusions 6 on the back surface of the conductor layer 2 by applying photoresist 3, exposing, developing, and half-etching; (c) coating the protective resist 71 on the front and back surfaces of the conductor layer 2; and (d) coating the photoresist 31 on the surface of the conductor layer 2.
A patterning step consisting of exposure and development; (e) a step of applying a protective resist 72 to the back surface of the conductor layer 2; and (f) a step of etching the surface of the conductor layer 2 to form a circuit pattern including the inner leads 8. (g) The protrusion 6 was manufactured on the back surface of the inner lead 8 by a step of peeling off the photoresist 31 and the protective resist 72 on the front and back surfaces of the conductor layer 2.
しかし、前述の従来技術では、導体層2の表・
裏面の露光を別々に行なうため、露光の際の基板
の位置決め誤差により、インナーリード8の所定
の位置に突起6を形成することが容易でない。殊
にテープキヤリア基板のように露光を自動的に連
続して行なう場合には初期的に表裏パターンの位
置合せをすることはできても、それ以降の一つ一
つの基板について位置合せをすることは不可能で
あり、露光機の基板位置決め精度や、基準穴とな
るスプロケツトホール5の変形等によつては、突
起の欠落や半導体素子電極との位置ずれによる接
合不良の原因となる。更に従来技術では、導体層
2をハーフエツチングし、強度的に弱くなつた状
態でフオトレジスト塗布、露光、現像等の工程を
通すため導体層が変形しやすく、その結果フオト
レジストのクラツクによる断線等で良好なパター
ン形成が安定してできないという問題がある。
However, in the above-mentioned conventional technology, the surface of the conductor layer 2
Since the back side is exposed separately, it is not easy to form the protrusion 6 at a predetermined position on the inner lead 8 due to a positioning error of the substrate during exposure. Especially when exposure is performed automatically and continuously, such as with tape carrier substrates, although it is possible to align the front and back patterns initially, it is difficult to align each substrate after that. This is not possible, and depending on the substrate positioning accuracy of the exposure machine, deformation of the sprocket hole 5 serving as a reference hole, etc., it may cause bonding failure due to missing protrusions or misalignment with the semiconductor element electrode. Furthermore, in the conventional technology, the conductor layer 2 is half-etched and subjected to steps such as photoresist coating, exposure, and development in a weakened state, so the conductor layer is easily deformed, resulting in wire breakage due to photoresist cracks, etc. However, there is a problem in that good pattern formation cannot be stably performed.
そこで本発明はこのような問題点を解決するも
ので、その目的はリードと突起との位置ずれをな
くし、また工程を短縮することによつて導体層へ
のダメージを軽減し、良好なパターン形成を安定
的に可能とする基板導体層への突起製造方法を提
供することにある。 The present invention is intended to solve these problems, and its purpose is to eliminate misalignment between leads and protrusions, reduce damage to the conductor layer by shortening the process, and improve pattern formation. An object of the present invention is to provide a method for manufacturing protrusions on a substrate conductor layer that stably enables the production of protrusions on a substrate conductor layer.
本発明の基板導体層への突起製造方法は、電子
部品の入る開孔部が形成された樹脂材からなる絶
縁層と前記開孔部を覆うように前記絶縁層上に被
着された金属箔からなる導体層とより構成される
基板導体層を有し、
前記導体層の両面にフオトレジストを塗布する
第1の工程と、前記導体層の両面のフオトレジス
トを同時露光、現像してパターニングする第2の
工程と、前記導体層を両面からエツチングして前
記導体層の一部を残すようにハーフエツチングす
る第3の工程と、ハーフエツチングされた前記導
体層の裏面に保護レジストを塗布する第4の工程
と、ハーフエツチングされた前記導体層を表面か
らエツチングする第5の工程と、前記フオトレジ
ストと前記保護レジストを剥離する第6の工程と
を有し、
前記開孔部に位置する前記導体層に突起が形成
されることを特徴とする。
The method of manufacturing protrusions on a substrate conductor layer according to the present invention includes: an insulating layer made of a resin material in which an opening into which an electronic component is inserted; and a metal foil adhered on the insulating layer so as to cover the opening. a substrate conductor layer consisting of a conductor layer and a conductor layer, a first step of applying a photoresist on both sides of the conductor layer, and simultaneous exposure and development of the photoresist on both sides of the conductor layer for patterning. a second step, a third step of etching the conductor layer from both sides and half-etching so as to leave a portion of the conductor layer; and a third step of applying a protective resist to the back side of the half-etched conductor layer. a fifth step of etching the half-etched conductor layer from the surface; and a sixth step of peeling off the photoresist and the protective resist, A feature is that protrusions are formed on the conductor layer.
以下、本発明について、実施例に基づき詳細に
説明する。
Hereinafter, the present invention will be described in detail based on examples.
第1図は本発明の一実施例であり、テープキヤ
リア基板のインナーリードに電気的接続用突起を
形成する工程順を示す図である。まずa図は絶縁
層1に張り付けられた導体層2の両面にフオトレ
ジスト3を塗布する工程である。ここで絶縁層1
は厚さ25μm〜125μmのポリイミドやガラエポ等
のフレキシブルテープで、半導体素子等の電子部
品素子の入るデバイスホール4と、位置決めや搬
送に用いるスプロケツトホール5およびその他回
路に必要な穴抜けがされている。導体層2は通常
厚さ35μm〜70μmの銅箔で、その裏面は絶縁層
1との密着性をあげるため表面粗度10μm程度の
凹凸を有するよう処理されている。この凹凸は、
後工程で形成される突起表面に残留し、半導体素
子のAl電極との接合においてAl酸化膜を突き破
り接合強度を増加する効果を有しているため、初
期的な表面粗度を保持することが重要である。従
つて導体層2の裏面のフオトレジスト厚みは、後
述のハーフエツチングの際に凸部がエツチングさ
れないよう、かつ厚すぎて不均一とならないよう
な厚さにすることが必要で、1.5μm〜4μmが適正
である。一方表面のフオトレジスト厚みは通常
1μm〜3μmで、その塗布方法としては表裏とも
ロールコーターやスプレーを用いる。 FIG. 1 is an embodiment of the present invention, and is a diagram showing the sequence of steps for forming electrical connection protrusions on inner leads of a tape carrier substrate. First, Fig. a shows a step of applying photoresist 3 to both sides of a conductor layer 2 pasted on an insulating layer 1. Here, insulating layer 1
is a flexible tape made of polyimide or glass epoxy with a thickness of 25 μm to 125 μm, and has device holes 4 for electronic components such as semiconductor devices, sprocket holes 5 used for positioning and transportation, and other holes necessary for circuits. There is. The conductor layer 2 is usually a copper foil with a thickness of 35 μm to 70 μm, and its back surface is treated to have irregularities with a surface roughness of about 10 μm to improve adhesion to the insulating layer 1. This unevenness is
It remains on the surface of the protrusions formed in the subsequent process, and has the effect of breaking through the Al oxide film and increasing the bonding strength when bonding with the Al electrode of the semiconductor element, making it possible to maintain the initial surface roughness. is important. Therefore, the thickness of the photoresist on the back surface of the conductor layer 2 must be set to a thickness of 1.5 μm to 4 μm so that the convex portions are not etched during half etching, which will be described later, and so that it is not too thick and uneven. is appropriate. On the other hand, the thickness of the photoresist on the surface is normal.
The thickness is 1 μm to 3 μm, and a roll coater or spray is used for both the front and back sides.
次にb図のように、導体層2の表面には第3図
のようなフオトマスクを用いてインナーリードを
含む回路パターンを、裏面には第4図のようなフ
オトマスクを用いて突起パターンを、互いに所定
の位置に来るように調整された両面露光装置によ
り同時露光して焼きつけ、次いで専用の現像液を
用いてスプレーもしくはデイツピングにより、両
面同時に現像する。ここで第3図のフオトマスク
は、インナーリードを含む回路パターンが後工程
で電気メツキが可能なように全て導通するよう設
計されている。また突起パターンを焼きつけるフ
オトマスクとしては、第4図のようにインナーリ
ードに対応して個別に突起パターンを設けたもの
のほかに、第5図のように一部もしくは全ての突
起をつなげたものを用いることも可能である。さ
らに現像において同時に両面を適正現像状態とす
るためその調節を露光量にて行ない、両面のフオ
トレジスト厚みが等しい場合は表面粗度が大きく
現像されにくい裏面は表面に比較して1.5〜2.5倍
の露光量とするのが良い。 Next, as shown in Figure b, a circuit pattern including inner leads is formed on the front surface of the conductor layer 2 using a photomask as shown in Figure 3, and a protrusion pattern is formed on the back side using a photomask as shown in Figure 4. Both sides are exposed and printed at the same time using a double-sided exposure device that is adjusted to be in a predetermined position with respect to each other, and then both sides are simultaneously developed by spraying or dipping using a special developer. Here, the photomask shown in FIG. 3 is designed so that the circuit pattern including the inner leads are all electrically conductive so that electroplating can be performed in a subsequent process. In addition, as a photomask for printing the protrusion pattern, in addition to a photomask with individual protrusion patterns corresponding to the inner leads as shown in Fig. 4, a photomask with some or all protrusions connected as shown in Fig. 5 is used. It is also possible. Furthermore, in order to bring both sides into a proper developing state at the same time, the exposure amount is adjusted.If the photoresist thickness on both sides is the same, the back side, which has a large surface roughness and is difficult to develop, has a roughness of 1.5 to 2.5 times that of the front side. It is better to set it to the amount of exposure.
次にc図のように、導体層2の両面を塩化第2
鉄などのエツチング液のスプレーによりハーフエ
ツチングする。ここで導体層2の裏面の突起6の
高さは用いる導体層の厚みによつても異なるが、
通常35μm銅箔の場合は半導体素子のエツジシヨ
ートの防止及びインナーリード強度の確保の為
5μm〜20μmとする。さらにハーフエツチング部
の角に応力が集中して切断しやすくなるのを防ぐ
為、第6図のようにハーフエツチ部の角に大きな
アールがつくようスプレー圧を低くしてサイドエ
ツチを大きくする。通常、比重30Be′〜60Be′、
液温25℃〜40℃の塩化第2鉄液でスプレー圧0.5
Kgf/cm2以下でハーフエツチングを行なつている
が、突起6の高さが用いる導体層2の厚みの1/2
未満であれば、デイツピングによるハーフエツチ
も可能である。尚インナリード強度の確保の為に
は裏面への突起パターン焼きつけ用のフオトマス
クを工夫することにより、第7図のようにハーフ
エツチ量を連続的に変えることも第8図のように
ハーフエツチング部を極力短かくすることも可能
である。一方導体層2の表面のハーフエツチング
は、裏面のハーフエツチングの際のエツチング液
の回り込みによる不均一エツチングを防止する為
に、裏面同様エツチング液をスプレーする。この
ときのハーフエツチング量は両面からエツチング
される部分が貫通しない程度にとどまるようスプ
レー圧等により調節する。 Next, as shown in figure c, both sides of the conductor layer 2 are coated with dichloride.
Half-etch by spraying an etching solution such as iron. Here, the height of the protrusion 6 on the back surface of the conductor layer 2 varies depending on the thickness of the conductor layer used.
Usually, in the case of 35μm copper foil, it is used to prevent edge-cutting of semiconductor elements and to ensure inner lead strength.
It is set to 5 μm to 20 μm. Furthermore, in order to prevent stress from concentrating on the corners of the half-etched part and making it easier to cut, the spray pressure is lowered and the side etching is increased so that a large radius is formed at the corner of the half-etched part, as shown in Figure 6. Usually specific gravity 30Be′~60Be′,
Spray pressure 0.5 with ferric chloride liquid at liquid temperature 25℃~40℃
Although half etching is performed at less than Kgf/ cm2 , the height of the protrusion 6 is 1/2 of the thickness of the conductor layer 2 used.
If it is less than that, half etching by dipping is also possible. In order to ensure the strength of the inner lead, by devising a photomask for printing the protrusion pattern on the back side, it is possible to continuously change the amount of half etching as shown in Figure 7, or to change the amount of half etching as shown in Figure 8. It is also possible to make it as short as possible. On the other hand, when half-etching the front surface of the conductor layer 2, an etching solution is sprayed on the back surface in order to prevent uneven etching due to the etching solution flowing around when half-etching the back surface. The amount of half etching at this time is adjusted by spray pressure or the like so that the portions etched from both sides do not penetrate through.
次にd図のように、導体層2の裏面にa図で用
いたフオトレジストと同じ剥離液で剥離可能なエ
ツチングレジストやフオトレジスト等の保護レジ
スト7をロールコーターやスプレー等により塗布
する。 Next, as shown in Figure d, a protective resist 7 such as an etching resist or a photoresist that can be removed with the same stripping solution as the photoresist used in Figure A is applied to the back surface of the conductor layer 2 using a roll coater, spray, or the like.
次にe図のように、導体層2の表側よりエツチ
ング液スプレーにより、c図の工程でエツチング
されずに残つていた不要な導体層をエツチングし
て、インナーリード8を含む回路パターンを形成
する。 Next, as shown in figure e, the unnecessary conductor layer that was not etched in the process of figure c is etched by spraying an etching liquid from the front side of the conductor layer 2 to form a circuit pattern including the inner leads 8. do.
次にf図のようにフオトレジスト3と保護レジ
スト7を専用剥離液を用いて剥離することにより
電気的接続用突起6のついたインナーリード8を
有するテープキヤリア基板が完成する。通常この
後は図示しないメツキの工程によりニツケルメツ
キを0μm〜3μm、その上に金メツキを0.5μm〜2μ
mつけ、半導体素子の電極との間で位置出しをし
て熱圧着することにより電気的接続ができる。第
9図は本発明によるテープキヤリア基板10と半
導体素子11との実装構造を示す図であり、12
は樹脂封止剤剤である。 Next, as shown in Fig. f, the photoresist 3 and the protective resist 7 are peeled off using a special stripping liquid, thereby completing a tape carrier substrate having inner leads 8 with electrical connection protrusions 6. Usually, after this, a plating process (not shown) is performed to apply nickel plating to 0 μm to 3 μm, and then gold plating to 0.5 μm to 2 μm.
Electrical connection can be made by attaching the electrode to the semiconductor element, positioning it with the electrode of the semiconductor element, and bonding it by thermocompression. FIG. 9 is a diagram showing a mounting structure of the tape carrier substrate 10 and the semiconductor element 11 according to the present invention.
is a resin sealant.
以上の説明はテープキヤリア基板を例にしたが
テープキヤリア基板に限らず、電子部品素子を接
合するためのインナーリードを有するあらゆるプ
リント基板に応用することが可能である。 Although the above explanation took the tape carrier board as an example, it is not limited to the tape carrier board, but can be applied to any printed circuit board having inner leads for bonding electronic component elements.
以上述べたように本発明によれば、導体層の両
面のフオトレジストを同時露光、現像してパター
ニングする第2の工程を有する構成としたので、
例えば、初期的に両面のパターンの位置合わせを
しておけば、その相対的な位置ズレが防止できる
ことから、露光機への基板導体層の位置決め精度
や、基板導体層自体の位置決め精度に影響される
ことなく、常に導体層の所定の位置に突起を形成
することが可能となり、その結果、半導体素子の
電極と突起との位置合わせが容易となり、両者の
安定的な接続が可能となる。
As described above, according to the present invention, the structure includes the second step of simultaneously exposing, developing and patterning the photoresists on both sides of the conductor layer.
For example, if the patterns on both sides are aligned initially, it is possible to prevent relative misalignment. It becomes possible to always form the protrusion at a predetermined position on the conductor layer without causing any damage, and as a result, alignment between the electrode of the semiconductor element and the protrusion becomes easy, and a stable connection between the two becomes possible.
また、パターニングされた基板導体層は両面か
らハーフエツチングした後、その裏面に保護レジ
ストが塗布され、再度表面よりエツチングされ
て、つまり2段階のエツチングにより導体層に突
起が形成されるように第2乃至第3工程を有する
構成としたので、ハーフエツチングにより形成さ
れた突起はその状態で保護レジストにより保護さ
れると共に、両面からのハーフエツチングによ
り、薄くされた導体層の一部のみが再度エツチン
グされることから、例えば、一方向の面のみから
順次エツチングしてパターン形成および突起形成
する従来技術と比較すれば、加工工程が短縮され
ると共に、導体層の変形もなく、またそのためフ
オトレジストにクラツクの入ることもないため、
良好かつ安定的なパターン形成が可能となる。 In addition, after the patterned substrate conductor layer is half-etched from both sides, a protective resist is applied to the back side, and it is etched again from the front side. Since the structure includes the third step, the protrusion formed by half etching is protected by the protective resist in that state, and only a part of the thinned conductor layer is etched again by half etching from both sides. For example, compared to conventional techniques in which patterns are formed and protrusions are formed by sequentially etching from only one surface, the processing steps are shortened, there is no deformation of the conductor layer, and there is no crack in the photoresist. Because there is no possibility of entering
Good and stable pattern formation becomes possible.
また工程の短縮により、製造コストの低減が可
能となる。 Furthermore, by shortening the process, manufacturing costs can be reduced.
第1図a〜fは本発明の実施例であるテープキ
ヤリア基板への電気的接続用突起の製造方法を示
す工程図、第2図a〜(g)は従来のテープキヤリア
基板への電気的接続用突起の製造方法を示す工程
図、第3図・第4図・第5図は本発明の実施例で
用いるフオトマスクの平面図、第6図・第7図・
第8図は本発明の実施例におけるインナーリード
形状を示す断面図、第9図は本発明の実施例にお
けるテープキヤリア基板を用いた半導体素子との
実装構造を示す断面図である。
1…絶縁層、2…導体層、3・31…フオトレ
ジスト、4…デイバイスホール、5…スプロケツ
トホール、6…突起、7・71・72…保護レジ
スト、8…インナーリード、10…テープキヤリ
ア基板、11…半導体素子、12…樹脂封止剤。
Figures 1a to 1f are process diagrams showing a method for manufacturing electrical connection protrusions to a tape carrier board according to an embodiment of the present invention, and Figures 2a to 2g are process diagrams showing a method for manufacturing electrical connection protrusions to a tape carrier board according to an embodiment of the present invention. 3, 4, and 5 are plan views of photomasks used in the embodiments of the present invention, and FIGS. 6, 7, and
FIG. 8 is a cross-sectional view showing the inner lead shape in an embodiment of the present invention, and FIG. 9 is a cross-sectional view showing a mounting structure of a semiconductor element using a tape carrier substrate in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Insulating layer, 2... Conductor layer, 3, 31... Photoresist, 4... Device hole, 5... Sprocket hole, 6... Protrusion, 7, 71, 72... Protective resist, 8... Inner lead, 10... Tape carrier Substrate, 11...Semiconductor element, 12...Resin sealant.
Claims (1)
らなる絶縁層と前記開孔部を覆うように前記絶縁
層上に被着された金属箔からなる導体層とより構
成される基板導体層を有し、 前記導体層の両面にフオトレジストを塗布する
第1の工程と、前記導体層の両面のフオトレジス
トを同時露光、現像してパターニングする第2の
工程と、前記導体層を両面からエツチングして前
記導体層の一部を残すようにハーフエツチングす
る第3の工程と、ハーフエツチングされた前記導
体層の裏面に保護レジストを塗布する第4の工程
と、ハーフエツチングされた前記導体層を表面か
らエツチングする第5の工程と、前記フオトレジ
ストと前記保護レジストを剥離する第6の工程と
を有し、 前記開孔部に位置する前記導体層に突起が形成
されることを特徴とする基板導体層への突起製造
方法。[Scope of Claims] 1. An insulating layer made of a resin material in which an opening into which an electronic component is inserted is formed, and a conductor layer made of a metal foil deposited on the insulating layer so as to cover the opening. a first step of applying a photoresist on both sides of the conductor layer; a second step of simultaneously exposing and developing the photoresist on both sides of the conductor layer to pattern it; a third step of etching the conductor layer from both sides and half-etching the conductor layer so as to leave a portion of the conductor layer; a fourth step of applying a protective resist to the back surface of the half-etched conductor layer; A fifth step of etching the etched conductor layer from the surface, and a sixth step of peeling off the photoresist and the protective resist, and a protrusion is formed on the conductor layer located in the opening. A method for manufacturing protrusions on a substrate conductor layer, characterized in that:
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5442486A JPS62211930A (en) | 1986-03-12 | 1986-03-12 | Method of producing projection of substrate conductor layer |
US07/017,419 US4786545A (en) | 1986-02-28 | 1987-02-24 | Circuit substrate and method for forming bumps on the circuit substrate |
GB8704425A GB2187331B (en) | 1986-02-28 | 1987-02-25 | Method of forming an integrated circuit assembly or part thereof |
GB8901825A GB2211351B (en) | 1986-02-28 | 1989-01-27 | Method of forming an integrated circuit assembly or part thereof |
SG1392A SG1392G (en) | 1986-02-28 | 1992-01-08 | Method of forming an integrated circuit assembly or part thereof |
SG1492A SG1492G (en) | 1986-02-28 | 1992-01-08 | Method of forming an integrated circuit assembly or part thereof |
HK36093A HK36093A (en) | 1986-02-28 | 1993-04-15 | Method of forming an integrated circuit assembly or part thereof |
HK35993A HK35993A (en) | 1986-02-28 | 1993-04-15 | Method of forming an integrated circuit assembly or part thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5442486A JPS62211930A (en) | 1986-03-12 | 1986-03-12 | Method of producing projection of substrate conductor layer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62211930A JPS62211930A (en) | 1987-09-17 |
JPH0474865B2 true JPH0474865B2 (en) | 1992-11-27 |
Family
ID=12970328
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5442486A Granted JPS62211930A (en) | 1986-02-28 | 1986-03-12 | Method of producing projection of substrate conductor layer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62211930A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55138864A (en) * | 1979-04-16 | 1980-10-30 | Sharp Corp | Method of fabricating semiconductor assembling substrate |
-
1986
- 1986-03-12 JP JP5442486A patent/JPS62211930A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55138864A (en) * | 1979-04-16 | 1980-10-30 | Sharp Corp | Method of fabricating semiconductor assembling substrate |
Also Published As
Publication number | Publication date |
---|---|
JPS62211930A (en) | 1987-09-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |