JPH04721A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04721A JPH04721A JP34280489A JP34280489A JPH04721A JP H04721 A JPH04721 A JP H04721A JP 34280489 A JP34280489 A JP 34280489A JP 34280489 A JP34280489 A JP 34280489A JP H04721 A JPH04721 A JP H04721A
- Authority
- JP
- Japan
- Prior art keywords
- phosphorus
- semiconductor substrate
- film
- damage
- excimer laser
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 37
- 239000011574 phosphorus Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- 239000013078 crystal Substances 0.000 claims abstract description 12
- 239000002344 surface layer Substances 0.000 claims abstract description 3
- 230000007547 defect Effects 0.000 claims description 8
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 230000035755 proliferation Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- 239000012159 carrier gas Substances 0.000 abstract description 3
- 239000002245 particle Substances 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 abstract 2
- 229910019213 POCl3 Inorganic materials 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000004576 sand Substances 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005488 sandblasting Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005247 gettering Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 241000252067 Megalops atlanticus Species 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半導体回路
素子が形成される表面及びその近傍層に存在し、半導体
回路素子特性を劣化させる原因となる汚染不純物を半導
体回路素子形成領域外の半導体基板裏面の歪場へ捕獲し
ようとするエクストリンシック ゲッタリング（Ｅ Ｇ
）能力の、半導体回路素子形成過程における補強の方法
に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, in particular, the present invention relates to a method for manufacturing a semiconductor device. Extrinsic gettering (E G
) relates to a method for reinforcing the ability in the process of forming a semiconductor circuit element.
従来、この種のＥＧ技術は半導体基板裏面に歪場を導入
することで行われているが、歪場は半導体回路素子形成
前もしくは形成過程中で結晶格子を損傷させることで導
入される。これには半導体基板裏面に機械的に損傷を与
える方法、イオン注入やドーパントの過剰拡散によって
結晶格子を歪ませる方法などが取られている。Conventionally, this type of EG technology has been carried out by introducing a strain field to the back surface of a semiconductor substrate, and the strain field is introduced by damaging a crystal lattice before or during the formation of a semiconductor circuit element. This can be achieved by mechanically damaging the backside of the semiconductor substrate, or by distorting the crystal lattice through ion implantation or over-diffusion of dopants.
通常機械的に損傷を与える方法は半導体回路素子形成途
中では行われないが、近年新しい裏面損傷技術として提
案されたエキシマレーザ ゲッタリング法（特願昭６ｌ
−１５４３７２）では半導体回路素子形成過程において
も裏面損傷が与えられることが特徴的である。また、ド
ーパントの過剰拡散では、Ｓｉ原子より原子径の大きい
ことなどから、半導体回路素子形成過程において基板裏
面にリンを拡散させる方法（応用物理 第４８巻第２号
１９７９年）がよく用いられている。Normally, methods that cause mechanical damage are not used during the formation of semiconductor circuit elements, but in recent years the excimer laser gettering method has been proposed as a new backside damage technology.
-154372) is characterized in that backside damage is caused even during the process of forming semiconductor circuit elements. In addition, for overdiffusion of dopants, the method of diffusing phosphorus to the back surface of the substrate in the process of forming semiconductor circuit elements (Applied Physics Vol. 48, No. 2, 1979) is often used because the atomic diameter is larger than that of Si atoms. There is.
従来の機械的な損傷与えるＥＧ法では結晶欠陥が半導体
回路素子形成過程で、熱処理によって緩和されＥＧ能力
が減退するという欠点がある。The conventional EG method that causes mechanical damage has the disadvantage that crystal defects are alleviated by heat treatment during the process of forming semiconductor circuit elements, resulting in a decrease in EG performance.
従って、回路素子形成途中で何らかの方法によりＥＧ能
力を補強してやらなければならない。半導体航路素子形
成途中でＥＧ能力を補強するには、基板裏面にＳｉ原子
より原子径の大きいドーパントを過剰に拡散させ結晶格
子を歪ませる処理を行うと合理的である。一般的にはド
ーパントにリンを用いることが多く、以後この処理に関
しては代表として裏面リン拡散について述べる。近年、
半導体装置の製造プロセスは低温化の傾向にあるが、そ
れに伴いリン拡散温度も低下してきている。低温化によ
り基板内部に拡散するリンの量、また拡散深さが小さく
なり、強固な歪場が得にくくなるという問題が生じる。Therefore, the EG ability must be reinforced by some method during the formation of the circuit element. In order to strengthen the EG ability during the formation of a semiconductor channel element, it is reasonable to carry out a process to distort the crystal lattice by excessively diffusing a dopant having an atomic diameter larger than that of Si atoms on the back surface of the substrate. Generally, phosphorus is often used as a dopant, and hereafter, backside phosphorus diffusion will be described as a representative example of this process. recent years,
As the manufacturing process of semiconductor devices tends to be lower in temperature, the phosphorus diffusion temperature is also lowering accordingly. As the temperature decreases, the amount of phosphorus that diffuses into the substrate and the diffusion depth decrease, causing a problem that it becomes difficult to obtain a strong strain field.
低温化による裏面リン拡散のＥＧ能力の低減を阻止し、
強固な歪場を得るための対策が必要である。Prevents reduction in EG ability due to back surface phosphorus diffusion due to low temperature,
Measures are needed to obtain a strong strain field.
本発明の半導体装置の製造方法は、半導体回路素子形成
過程において半導体基板裏面にエキシマレーザ照射を行
ない損傷を与えた後、裏面リン拡散を行うという工程を
有している。基板表面に損傷があると、損傷にそってリ
ン拡散が増速されて多量のリンが基板表面近傍に侵入す
るという効果がある。従って、本発明を適用すると基板
表面に損傷が無い、もしくは熱処理によって緩和されて
いる場合よりも、ＥＧ能力が強化できる。また、低温処
理でも強固な歪場が得られ十分なＥＧ能力が得られる。The method for manufacturing a semiconductor device of the present invention includes the step of irradiating the back surface of a semiconductor substrate with an excimer laser to damage it in the process of forming a semiconductor circuit element, and then performing back surface phosphorus diffusion. When there is damage to the substrate surface, phosphorus diffusion is accelerated along the damage, and a large amount of phosphorus enters the vicinity of the substrate surface. Therefore, when the present invention is applied, the EG ability can be enhanced more than when the substrate surface has no damage or is softened by heat treatment. In addition, a strong strain field can be obtained even during low-temperature processing, and sufficient EG ability can be obtained.
エキシマレーザ照射と裏面リン拡散の間には、レーザ損
傷を緩和させないため、高温長時間の熱処理は避けるべ
きである。During excimer laser irradiation and backside phosphorus diffusion, high-temperature and long-term heat treatment should be avoided in order to prevent laser damage from being alleviated.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明を適用したＭＯＳキャパシタ作製工程を
示す。FIG. 1 shows a process for manufacturing a MOS capacitor to which the present invention is applied.
第１図の工程（ａ）に示す、裏面にシリカ（ＳｉＯｚ）
の粒子を吹きつけるサンドブラスト法で損傷３を与えた
Ｐ型Ｓｉ半導体基板１と損傷を与えていないＰ型Ｓｉ半
導体基板２のそれぞれの基板上に、第１図工程（ｂ）に
示すように素子分離膜４．ゲート酸化膜５を形成しさら
にＣＶＤ法によりポリＳｉ膜６を成長させた。次に工程
（ｃ）に示すように、それぞれの基板はウェットエツチ
ングで裏面のポリシリコン２酸化膜等を除去し、一部の
基板には裏面にＫｒＦをレーザ源とするエキシマレーザ
（波長２４９ｎｍ）７を照射し、レーザ損傷８を導入し
た。この後、すべての基板に対し第１図工程（ｄ）のよ
うに８５０℃で％Ｎ２をキャリアーガスとしＰＯＣρ３
によって３０分間リン拡散を行った。半導体基板裏面に
は表面層内にリンが拡散して結晶格子を歪ませて歪場９
を形成する。最後に第１図工程（ｅ）に示す様にポリシ
リコンゲート電極１０．保護膜１１１層間絶縁膜１２．
ＡＩ２配線１３を形成しＭＯＳキャパシタを完成させた
。Silica (SiOz) is applied to the back side as shown in step (a) in Figure 1.
A device is placed on each of the P-type Si semiconductor substrate 1 which has been damaged by a sandblasting method in which particles of Separation membrane 4. A gate oxide film 5 was formed, and then a poly-Si film 6 was grown by CVD. Next, as shown in step (c), the polysilicon dioxide film, etc. on the back surface of each substrate is removed by wet etching, and some substrates are etched with an excimer laser (wavelength 249 nm) using KrF as a laser source. 7 was irradiated to introduce laser damage 8. After that, as shown in step (d) in Figure 1, all the substrates were heated to 850°C with %N2 as a carrier gas and POCρ3
Phosphorus diffusion was performed for 30 minutes. On the back side of the semiconductor substrate, phosphorus diffuses into the surface layer and distorts the crystal lattice, creating a strain field 9.
form. Finally, as shown in step (e) of FIG. 1, the polysilicon gate electrode 10. Protective film 111 Interlayer insulating film 12.
AI2 wiring 13 was formed to complete the MOS capacitor.
完成したＭＯＳキャパシタは次の４種類のＥＧ処理が施
されている。The completed MOS capacitor has been subjected to the following four types of EG processing.
■ サンドブラスト損傷十エキシマレーザ損傷十裏面リ
ン拡散
■ サンドブラスト損傷十裏面リン拡散■ エキキマレ
ーザ損傷＋裏面リン拡散■ 裏面リン拡散。■ Sandblasting damage 10 Excimer laser damage 10 Back side phosphorus diffusion ■ Sandblasting damage 10 Back side phosphorus diffusion ■ Excimer laser damage + back side phosphorus diffusion ■ Back side phosphorus diffusion.
それぞれのＭＯＳキャパシタについてマイノリティキャ
リアのライフタイムを測定した。結果を第２図に示す。The lifetime of minority carriers was measured for each MOS capacitor. The results are shown in Figure 2.
ライフタイムは上記■〉■〉■〉■の順に大きく、本発
明を適用し、裏面リン拡散直前に裏面損傷を与えること
によってＥＧ能力を強化し、ＭＯＳキャパシタ特性を向
上させることができる。The lifetime increases in the order of ■>■>■>■ above, and by applying the present invention and damaging the backside immediately before backside phosphorus diffusion, the EG ability can be strengthened and the MOS capacitor characteristics can be improved.
第３図は本発明の半導体装置の製造方法をＤＲＡＭ作製
工程に適用する一実施例を示す概略図である。FIG. 3 is a schematic diagram showing an embodiment in which the semiconductor device manufacturing method of the present invention is applied to a DRAM manufacturing process.
第３図工程（ａ）に示す様に比抵抗１５Ω・口のＰ型（
１００）のＳｉ半導体基板１４上に、素子分離膜１５ｎ
＋領域１６容量膜１７を形成し、この上にストレージゲ
ートとなるポリＳｉ １８をＣＶＤにより成長させた。As shown in Figure 3, step (a), the resistivity is 15Ω and the opening P type (
100) on the Si semiconductor substrate 14, an element isolation film 15n
A capacitive film 17 in the + region 16 was formed, and poly-Si 18, which would become a storage gate, was grown thereon by CVD.
ここで、第３図工程（ｂ）のようにＳｉ半導体基板１４
の裏面はウェットエツチングによって基板面を露出させ
てＸｅＣｌ１を光源とする波長３０８ ｎｍのエキシマ
レーザ１９を照射エネルギー密度５ Ｊ ／ａＡ、 ｐ
ａｌｓｅで照射し一面にレーザ損傷２０を形成した。次
に第３図工程（ｃ）に見られるようにそれぞれ１０００
℃。Here, as shown in step (b) of FIG. 3, the Si semiconductor substrate 14
The back surface of the substrate was wet-etched to expose the substrate surface and irradiated with an excimer laser 19 with a wavelength of 308 nm using XeCl1 as a light source at an energy density of 5 J/aA, p.
irradiation with alse to form laser damage 20 on the entire surface. Next, as shown in step (c) of Figure 3, 1000 each
℃.
８００℃でＮ２をキャリアーガスとしＰＯ（１，を用い
て３０分間リン拡散を行なうと、半導体基板裏面に拡散
されたリンは結晶格子を歪ませ、歪場２１を形成する。When phosphorus is diffused at 800° C. for 30 minutes using PO(1, with N2 as a carrier gas), the phosphorus diffused into the back surface of the semiconductor substrate distorts the crystal lattice and forms a strain field 21.
この後、第３図工程（ｄ）に示すようにストレージゲー
ト２２．絶縁膜２３．ゲート酸化膜２４．ポリシリコン
ゲート電極２５．絶縁膜２６．ｎ“ソース領域２７．ｎ
＋ドレイン領域２８を形成する。さらに第３図工程（ｅ
）の様に絶縁層間膜２９を形成し、Ａｌ２３０を配線す
ると、１トランジスタ、１キヤパシタのメモリセルが構
成される。After this, as shown in step (d) of FIG. 3, the storage gate 22. Insulating film 23. Gate oxide film 24. Polysilicon gate electrode 25. Insulating film 26. n" source region 27.n
+Drain region 28 is formed. Furthermore, the process in Figure 3 (e
) When an insulating interlayer film 29 is formed and Al 230 is wired, a memory cell with one transistor and one capacitor is constructed.
半導体基板裏面に発生した結晶欠陥をジルトルエッチを
行った後、観察したところ、８００℃のリン拡散を行っ
た基板は本発明の適用例では〜ｌ×１０５個／ａＡ、裏
面に損傷なく裏面リン拡散を行った場合は約２Ｘ１０’
個／ｄ、回路素子形成前にサンドブラスト法で損傷を与
えただけで裏面リン拡散を行った場合は４Ｘ１０’個／
−と、本発明を適用すると従来の裏面リン拡散法を用い
た場合よりも５〜２．５倍の結晶欠陥が発生した。また
１０００℃のリン拡散の基板は、サンドブラスト法で損
傷を与え裏面リン拡散を行った従来の裏面リン拡散法で
は〜１×ｌＯｓ個／ｄの結晶欠陥が観察された。従来法
ではリン拡散温度が低下すると発生欠陥数が低減したが
、本発明を適用するとリン拡散温度が８００℃に低下し
ても、１０００℃の場合と同程度の欠陥数が観察された
。つまり、リン拡散温度の低下によりＥＧ能力が低減し
ていない。また本発明をＤＲＡＭ製造工程に適用したと
ころ、良品率が１０〜１５％上昇した。When we observed the crystal defects generated on the back surface of the semiconductor substrate after performing zirtle etching, it was found that the substrate subjected to phosphorus diffusion at 800°C was ~l×105 defects/aA in the application example of the present invention, and the back surface phosphorus was diffused without damage to the back surface. Approximately 2X10'
pieces/d, 4×10' pieces/d when backside phosphorus diffusion is performed with only damage caused by sandblasting before circuit element formation.
-, when the present invention was applied, 5 to 2.5 times more crystal defects were generated than when the conventional back surface phosphorus diffusion method was used. Further, in the case of a substrate subjected to phosphorus diffusion at 1000° C., crystal defects of ~1×1Os/d were observed in the conventional backside phosphorus diffusion method in which damage was done by sandblasting and backside phosphorus diffusion was performed. In the conventional method, the number of generated defects decreased as the phosphorus diffusion temperature decreased, but when the present invention was applied, even when the phosphorus diffusion temperature decreased to 800°C, the same number of defects as in the case of 1000°C was observed. In other words, the EG ability is not reduced due to the decrease in phosphorus diffusion temperature. Furthermore, when the present invention was applied to a DRAM manufacturing process, the non-defective product rate increased by 10 to 15%.
以上説明したように本発明は、半導体回路素子形成過程
において半導体基板裏面にエキシマレーザを照射し損傷
を与えた後リン拡散をすることによって、強固な歪場を
得、より安定した強力なＥＧ能力を働かせ半導体回路素
子特性を向上させ、さらに半導体回路素子製品の歩留り
を向上できるという効果がある。As explained above, in the process of forming a semiconductor circuit element, the present invention irradiates the back surface of a semiconductor substrate with an excimer laser to damage it and then diffuses phosphorus, thereby obtaining a strong strain field and achieving more stable and strong EG performance. This has the effect of improving the characteristics of semiconductor circuit elements and further improving the yield of semiconductor circuit element products.
【図面の簡単な説明】
第１図は本発明をＭＯＳキャパシタ作製工程に適用した
場合の工程フｐ−を示す断面図、第２図は本発明を適用
して作製したＭＯＳキャパシタを用いて測定したマイノ
リティキャリアのライフタイムを示すグラフ、′第３図
は本発明をＤＲＡＭ作製工程に適用する一実施例を示す
概略図である。
１・・・・・・Ｐ型Ｓｉ半導体基板、２・・・・・・Ｐ
型Ｓｉ半導体基板、３・・・・・・損傷、４・・・・・
・素子分離膜、５・・・・・・ゲート酸化膜、６・・・
・・・ポリＳｉ膜、７・・・・・・エキシマレーザ、８
・・・・・・レーザ損傷、９・・・・・・歪場、１０・
・・・・・ポリシリコンゲート電極、１工・・・・・・
保護膜、１２・・・・・・層間絶縁膜、１３・・・・・
・Ａρ配線、１４・・・・・・Ｐ型Ｓｉ半導体基板、１
５・・・・・・素子分離膜、１６・・・・・・ｎ＋領領
域１７・・・・・・容量膜、１８・・・・・ポ！ｊｓｉ
、１９・・・・・・エキシマレーザ、２０・・・・・・
レーザ損傷、２１・・・・・・歪場、２２・・・・・・
ストレージゲート、２３・・・・・・絶縁膜、２４・・
・・・・ゲート酸化膜、２５・・・・・・ポリシリコン
ゲート電極、２６・・・・・・絶縁膜、２７−− ｎ＋
ソース領域、２８ ＝−−−−ｎ＋ドレイン領域、２９
・・・・・・絶縁層間膜、３０・・・・・・Ａｆｆｌ配
線。
代理人 弁理士 内 原 晋
Ｈ
正の対象
明の詳細な説明の欄
平成
３年
８月２２日
７、補正の内容
明細書簡２頁１行目「８６図面の簡単な説明」とあるの
を「３、発明の詳細な説明」と訂正する。
１、事件の表示
平成
１年特
第３４２８０４号
２、発明の名称
半導体装置の製造方法[Brief Description of the Drawings] Figure 1 is a cross-sectional view showing the process step when the present invention is applied to the MOS capacitor manufacturing process, and Figure 2 is a measurement using the MOS capacitor manufactured by applying the present invention. FIG. 3 is a schematic diagram showing an embodiment in which the present invention is applied to a DRAM manufacturing process. 1...P-type Si semiconductor substrate, 2...P
Type Si semiconductor substrate, 3...Damage, 4...
・Element isolation film, 5...Gate oxide film, 6...
... Poly Si film, 7 ... Excimer laser, 8
...Laser damage, 9...Strain field, 10.
...Polysilicon gate electrode, 1 piece...
Protective film, 12...Interlayer insulating film, 13...
・Aρ wiring, 14... P-type Si semiconductor substrate, 1
5...Element isolation film, 16...N+ region 17...Capacitance film, 18...Po! jsi
, 19... excimer laser, 20...
Laser damage, 21... Strain field, 22...
Storage gate, 23...Insulating film, 24...
... Gate oxide film, 25 ... Polysilicon gate electrode, 26 ... Insulating film, 27-- n+
Source region, 28 =---n+drain region, 29
...Insulating interlayer film, 30...Affl wiring. Representative Patent Attorney Susumu Uchihara Column for Detailed Explanation of the Subject Matter August 22, 1991 7, page 2, line 1 of the amendment letter, ``Brief explanation of drawing 86'' was replaced with ``Brief explanation of drawing 86'' 3. Detailed description of the invention". 1. Indication of the case 1999 Special No. 342804 2. Name of the invention Method for manufacturing semiconductor devices
Claims (2)
上に半導体回路素子を製造する過程において、前記鏡面
と反対側の半導体基板表面にエキシマレーザを照射して
損傷を与える工程と、この後、該損傷面にリンを拡散さ
せる工程とを有する半導体装置の製造方法(1) In the process of manufacturing semiconductor circuit elements on the mirror-polished surface of a semiconductor substrate made of Si single crystal, a step of irradiating the surface of the semiconductor substrate opposite to the mirror surface with an excimer laser to damage it; , a step of diffusing phosphorus into the damaged surface.
は積層欠陥、あるいは、その両者を誘起するエネルギー
密度条件で行われかつ、前記リン拡散の条件が、レーザ
損傷面表面層にリンの過剰拡散によるＳｉ結晶格子欠陥
の増殖が認められる条件であることを特徴とする請求項
１記載の半導体装置の製造方法(2) The excimer laser irradiation is performed under energy density conditions that induce dislocations, stacking faults, or both on the irradiated surface, and the phosphorus diffusion conditions are such that phosphorus is excessively diffused into the surface layer of the laser-damaged surface. The method for manufacturing a semiconductor device according to claim 1, wherein the conditions are such that proliferation of Si crystal lattice defects is observed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34280489A JPH04721A (en) | 1989-12-29 | 1989-12-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34280489A JPH04721A (en) | 1989-12-29 | 1989-12-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04721A true JPH04721A (en) | 1992-01-06 |
Family
ID=18356627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34280489A Pending JPH04721A (en) | 1989-12-29 | 1989-12-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04721A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009260012A (en) * | 2008-04-16 | 2009-11-05 | Hitachi Industrial Equipment Systems Co Ltd | Static induction electrical apparatus |
| CN102719894A (en) * | 2012-05-22 | 2012-10-10 | 江苏顺风光电科技有限公司 | Phosphorus diffusion technology of solar cell silicon wafer |
-
1989
- 1989-12-29 JP JP34280489A patent/JPH04721A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009260012A (en) * | 2008-04-16 | 2009-11-05 | Hitachi Industrial Equipment Systems Co Ltd | Static induction electrical apparatus |
| CN102719894A (en) * | 2012-05-22 | 2012-10-10 | 江苏顺风光电科技有限公司 | Phosphorus diffusion technology of solar cell silicon wafer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6031231A (en) | Manufacture of semiconductor substrate | |
| JP2998330B2 (en) | SIMOX substrate and method of manufacturing the same | |
| JPH04163920A (en) | Manufacture of si substrate | |
| JPS6031232A (en) | Manufacture of semiconductor substrate | |
| JPH04721A (en) | Manufacture of semiconductor device | |
| JPH05235005A (en) | Semiconductor substrate and manufacture thereof | |
| JPS6120337A (en) | Manufacture of semiconductor device | |
| JPH0411736A (en) | Semiconductor device and manufacture thereof | |
| JPH05152304A (en) | Manufacture of semiconductor substrate | |
| JP3001513B2 (en) | Manufacturing method of semiconductor wafer | |
| JPH04171827A (en) | Manufacture of semiconductor device | |
| JPH0661234A (en) | Production of semiconductor device | |
| KR100545990B1 (en) | How to remove metal impurities in silicon wafer | |
| JPH0247836A (en) | Manufacture of semiconductor device | |
| JP3407345B2 (en) | Oxygen concentration measurement method for silicon substrate | |
| JPH04293241A (en) | Manufacture of semiconductor substrate | |
| JPS60176241A (en) | Manufacture of semiconductor substrate | |
| JPH0616498B2 (en) | Method for manufacturing epitaxial wafer | |
| JPH1187258A (en) | Manufacture of semiconductor device | |
| JPS6386565A (en) | Manufacture of semiconductor device | |
| JPS5974638A (en) | Manufacture of semiconductor wafer | |
| JP2669722B2 (en) | Method for manufacturing semiconductor device | |
| JPS61114537A (en) | Silicon semiconductor substrate | |
| JPH04155930A (en) | Production of semiconductor device | |
| JPH02310929A (en) | Manufacture of semiconductor device |