JPH0247836A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0247836A JPH0247836A JP20048788A JP20048788A JPH0247836A JP H0247836 A JPH0247836 A JP H0247836A JP 20048788 A JP20048788 A JP 20048788A JP 20048788 A JP20048788 A JP 20048788A JP H0247836 A JPH0247836 A JP H0247836A
- Authority
- JP
- Japan
- Prior art keywords
- silicon semiconductor
- oxygen
- semiconductor substrate
- heat
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 40
- 239000010703 silicon Substances 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 23
- 150000002926 oxygen Chemical class 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 38
- 239000001301 oxygen Substances 0.000 abstract description 38
- 229910052760 oxygen Inorganic materials 0.000 abstract description 38
- 238000005247 gettering Methods 0.000 abstract description 27
- 239000002244 precipitate Substances 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 8
- 239000013078 crystal Substances 0.000 abstract description 5
- 230000002045 lasting effect Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 230000002950 deficient Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon Chemical class 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000005923 long-lasting effect Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にゲッタリン
グ源となる欠陥層が形成されたシリコン半導体基板の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a silicon semiconductor substrate on which a defect layer serving as a gettering source is formed.
シリコン半導体基板中に形成した結晶欠陥層によって有
害不純物などをゲッタリングする技術には、欠陥層の形
成方法により大きく分けてイントリンシック・ゲッタリ
ング技術とエクストリンシック・ゲッタリング技術とが
ある。欠陥層の具体的な形成方法としては従来、イント
リンシック・ゲッタリング技術においてはチョクラルス
キー法で引き上げたシリコン単結晶中にもともと過飽和
に含まれる溶存酸素を熱処理によってか析出させ、シリ
コン半導体基板の内部に欠陥層を形成する技術が代表的
である。Techniques for gettering harmful impurities using a crystal defect layer formed in a silicon semiconductor substrate are broadly divided into intrinsic gettering techniques and extrinsic gettering techniques, depending on the method of forming the defect layer. Conventionally, the specific method for forming a defective layer is to use heat treatment to precipitate dissolved oxygen, which is originally supersaturated in a silicon single crystal pulled by the Czochralski method, to form a silicon semiconductor substrate. A typical technique is to form a defective layer inside.
一方エクトスリンシック・ゲッタリング技術は半導体基
板の裏面側に格子歪を導入するもので、たとえばシリコ
ン半導体基板の裏面に機械的損傷を与えたり、あるいは
シリコン半導体基板の裏面にリンなどの不純物を拡散し
、格子不整合転位網を発生させたり、あるいはアルゴン
などのイオン注入によって格子に損傷を与えたり、ある
いはまた、シリコン半導体基板の裏面にシリコン窒化膜
を成長させ、高温で熱処理することによってシリコン半
導体基板とシリコン窒化膜との界面に歪場を形成するな
どの方法がある。さらにまたシリコン半導体基板の裏面
に多結晶半導体膜を成長させ、この多結晶半導体膜の結
晶粒界をゲッタリング源とする方法もエクストリンシッ
ク・ゲッタリング技術に含まれる。On the other hand, ectothrinthic gettering technology introduces lattice strain on the backside of a semiconductor substrate, for example by mechanically damaging the backside of a silicon semiconductor substrate or by diffusing impurities such as phosphorus into the backside of a silicon semiconductor substrate. The silicon semiconductor can be grown by generating a lattice-mismatched dislocation network, or by damaging the lattice by implanting ions such as argon, or by growing a silicon nitride film on the backside of the silicon semiconductor substrate and heat-treating it at high temperatures. There are methods such as forming a strain field at the interface between the substrate and the silicon nitride film. Furthermore, extrinsic gettering technology also includes a method in which a polycrystalline semiconductor film is grown on the back surface of a silicon semiconductor substrate and the crystal grain boundaries of this polycrystalline semiconductor film are used as a gettering source.
しかしながら上述した従来のゲッタリング技術は、たと
えばまずイントリンシック・ゲッタリング技術において
は、酸素析出の機構が極めて多様かつ複雑な要因を含ん
でいるため、酸素析出の完全な制御は非常に困難で、欠
陥層の形成が十分でなかったり、逆に無欠陥であるべき
デバイス活性領域に欠陥が発生したりして、半導体装置
の製造歩留りを低下させるという問題点を持つ。さらに
また、酸素析出が多い場合、格子間酸素濃度が低下する
ことと、酸素析出物の形成に伴い転位が発生することに
よって、シリコン半導体基板の機械的強度は著しく低下
し、半導体装置製造工程中にシリコン半導体基板にスリ
ップが生じ、半導体装置の製造歩留りを低下させるとい
う問題点がある。However, in the conventional gettering technology described above, for example, in the intrinsic gettering technology, the mechanism of oxygen precipitation includes extremely diverse and complex factors, so it is extremely difficult to completely control oxygen precipitation. There is a problem in that the formation of a defective layer is insufficient or, conversely, defects occur in a device active region that should be defect-free, reducing the manufacturing yield of semiconductor devices. Furthermore, when there is a large amount of oxygen precipitated, the interstitial oxygen concentration decreases and dislocations occur due to the formation of oxygen precipitates, resulting in a significant decrease in the mechanical strength of the silicon semiconductor substrate. Another problem is that slip occurs in the silicon semiconductor substrate, reducing the manufacturing yield of semiconductor devices.
一方エクストリンシック・ゲッタリング技術においては
、シリコン半導体基板の変形や汚染を伴うことが多く、
また欠陥層の幅が小さいため、般的にイントリンシック
・ゲッタリング技術よりは効果が小さく、さらにシリコ
ン半導体基板の裏面に機械的損傷を与えたり、不純物拡
散により格子不整合転位網を発生させたり、イオン注入
により格子に損傷を与えるなどして形成した欠陥層は熱
処理によって容易にア丘−ル・アウトされてしま・い、
またシリコン半導体基板の裏面にシリコン窒化膜や多結
晶半導体膜を成長させる方法では、エツチングや酸化な
どのプロセスを経ることによって消費されてしまい、い
ずれも半導体装置製造工程中でゲッタリング効果が長続
きしないという問題点があった。On the other hand, extrinsic gettering technology often involves deformation and contamination of the silicon semiconductor substrate.
In addition, because the width of the defect layer is small, it is generally less effective than intrinsic gettering technology, and it also causes mechanical damage to the backside of the silicon semiconductor substrate and generates a lattice-mismatched dislocation network due to impurity diffusion. The defective layer formed by damaging the lattice through ion implantation is easily removed by heat treatment.
Furthermore, in the method of growing a silicon nitride film or a polycrystalline semiconductor film on the back side of a silicon semiconductor substrate, the gettering effect does not last long during the semiconductor device manufacturing process because the film is consumed through processes such as etching and oxidation. There was a problem.
本発明の半導体装置の製造方法は、シリコン半導体基板
の一方の表面に過飽和に酸素を含んだ多結晶シリコン半
導体膜を形成する工程と、該シリコン半導体基板を１０
５０℃より高い温度で３０分間以上熱処理する工程と、
該シリコン半導体基板を１０００℃より低い温度で２時
間以上熱処理する工程と、半導体基板の他方の表面に半
導体素子を形成する工程とを有している。The method for manufacturing a semiconductor device of the present invention includes the steps of forming a polycrystalline silicon semiconductor film containing supersaturated oxygen on one surface of a silicon semiconductor substrate, and
a step of heat treatment at a temperature higher than 50°C for 30 minutes or more;
The method includes a step of heat-treating the silicon semiconductor substrate at a temperature lower than 1000° C. for 2 hours or more, and a step of forming a semiconductor element on the other surface of the semiconductor substrate.
次に本発明の一実施例について図面を参照して順に説明
する。Next, one embodiment of the present invention will be described in order with reference to the drawings.
まず第１図に示すように１．４Ｘ１０”ｃｍ−”の格子
間酸素を含んだ、直径１２５ｍｍ、厚さ６００ｕｍ。First, as shown in FIG. 1, it is 125 mm in diameter and 600 um in thickness, and contains 1.4 x 10 cm of interstitial oxygen.
面方位（１００）のシリコン半導体基板ｌの一方の表面
にシラン（ＳｉＨ＋）を用いた通常の化学気相成長法（
ＣＶＤ法）によって厚さ１０μｍの多結晶シリコン半導
体膜２を形成し、次いで多結晶シリコン半導体膜２ヘエ
ネルギー７０ＫｅＶ。A conventional chemical vapor deposition method (100) using silane (SiH
A polycrystalline silicon semiconductor film 2 with a thickness of 10 μm is formed by CVD method, and then an energy of 70 KeV is applied to the polycrystalline silicon semiconductor film 2.
ドーズ量ｌＸ１０１３ｃｍ”で酸素３をイオン注入する
。なお第１図においては格子間酸素は省略しである。Oxygen 3 is ion-implanted at a dose of 1×10 13 cm. In FIG. 1, interstitial oxygen is omitted.
次いで第２図に示すようにシリコン半導体基板１を、５
％の酸素を含む窒素雰囲気中で１２００℃、２時間の熱
処理を施し、これによってシリコン半導体基板１の内部
にほぼ一様に分布している格子間酸素４のシリコン半導
体基板１の表面からの外部拡散５を起こさせるが、この
際、多結晶シリコン半導体膜２中の酸素３は格子間へ放
出されており、多結晶シリコン半導体膜２中の格子間酸
素濃度が高いため、こちらの表面側からは酸素の外部拡
散５は起きない。したがってシリコン半導体基板１中の
格子間酸素４は多結晶シリコン半導体膜２の形成されて
いない方の表面付近だけが濃度が低くなる。Next, as shown in FIG. 2, the silicon semiconductor substrate 1 is
Heat treatment is performed at 1200° C. for 2 hours in a nitrogen atmosphere containing % oxygen, and as a result, interstitial oxygen 4, which is almost uniformly distributed inside the silicon semiconductor substrate 1, is removed from the surface of the silicon semiconductor substrate 1. Diffusion 5 is caused, but at this time, oxygen 3 in the polycrystalline silicon semiconductor film 2 is released into the interstitial space, and since the interstitial oxygen concentration in the polycrystalline silicon semiconductor film 2 is high, the oxygen 3 in the polycrystalline silicon semiconductor film 2 is released from this surface side. In this case, external diffusion 5 of oxygen does not occur. Therefore, the concentration of interstitial oxygen 4 in silicon semiconductor substrate 1 is low only near the surface where polycrystalline silicon semiconductor film 2 is not formed.
続いてシリコン半導体基板１を６５０℃、４時間の熱処
理を施し、第３図に示すようにシリコン半導体基板ｌ内
部の格子間酸素濃度の高い領域に酸素析出核６を成長さ
せる。次にこのシリコン半導体基板１を乾燥酸素雰囲気
中で１０００℃、１６時間の熱処理を施すと、第４図に
示すように酸素析出核６が形成されている領域に酸素析
出物７が成長し、これがイントリンシック・ゲッタリン
グ源として作用する。Subsequently, the silicon semiconductor substrate 1 is subjected to a heat treatment at 650° C. for 4 hours, and as shown in FIG. 3, oxygen precipitate nuclei 6 are grown in a region with a high interstitial oxygen concentration inside the silicon semiconductor substrate 1. Next, when this silicon semiconductor substrate 1 is subjected to heat treatment at 1000° C. for 16 hours in a dry oxygen atmosphere, oxygen precipitates 7 grow in the region where oxygen precipitate nuclei 6 are formed, as shown in FIG. This acts as an intrinsic gettering source.
また多結晶シリコン半導体膜２の結晶粒界はエクストリ
ンシック・ゲッタリング源として作用する。なおこの多
結晶シリコン半導体膜２は酸化工程を繰り返すことによ
って消費されるが、すへてか消費された後は、この表面
に高密度に依存していた酸素析出物７の成長に起因して
、第５図に示すように積層欠陥８が高密度に発生し、こ
れが強力なエクストリンシック・ゲッタリング源として
作用する。Further, the crystal grain boundaries of the polycrystalline silicon semiconductor film 2 act as an extrinsic gettering source. Note that this polycrystalline silicon semiconductor film 2 is consumed by repeating the oxidation process, but after it is completely consumed, due to the growth of oxygen precipitates 7 that are highly concentrated on this surface. , as shown in FIG. 5, stacking faults 8 occur in high density and act as a strong extrinsic gettering source.
以上のように作成したシリコン半導体基板は、従来のゲ
ッタリング技術を用いたものと異なり、酸化処理などに
よってゲッタリング源であった多結晶シリコン半導体膜
がすべて消費されてしまった後でも、表面まで露出した
内部欠陥に起因し成長する積層欠陥に基づくゲッタリン
グ作用が働く。The silicon semiconductor substrate created as described above differs from those using conventional gettering technology in that even after the polycrystalline silicon semiconductor film that was the gettering source has been completely consumed by oxidation treatment, A gettering effect occurs based on stacking faults that grow due to exposed internal defects.
このゲッタリング源は無尽蔵といってよく、半導体装置
製造工程中に７エール・アウトされたり消費されつくし
てしまうことはない。This gettering source can be said to be inexhaustible, and will not be exhausted or consumed during the semiconductor device manufacturing process.
また本発明の半導体装置の製造方法は有害不純物などに
よる汚染の心配もない。さらに本発明はイントリンシッ
ク・ゲッタリング技術とエクストリンシック技術との相
乗効果による極めて強力なゲッタリング作用が得られる
ため、無欠陥であるべき領域近くまで過剰の内部欠陥の
形成させるような危険をおかす必要はない。Furthermore, the method of manufacturing a semiconductor device of the present invention eliminates the risk of contamination by harmful impurities. Furthermore, since the present invention provides an extremely strong gettering effect due to the synergistic effect of the intrinsic gettering technology and the extrinsic technology, there is a risk that excessive internal defects will be formed near areas that should be defect-free. There's no need.
これらのことから、本発明の半導体装置の製造方法は、
信頼性の高い半導体装置を高歩留まり製造するのに極め
て有効であるといえる。From these facts, the method for manufacturing a semiconductor device of the present invention is as follows:
It can be said that this method is extremely effective in manufacturing highly reliable semiconductor devices at a high yield.
なお、半導体素子は、シリコン半導体基板１の多結晶シ
リコン半導体膜２が形成されていない主面側に形成され
る。Note that the semiconductor element is formed on the main surface side of the silicon semiconductor substrate 1 where the polycrystalline silicon semiconductor film 2 is not formed.
第６図、第７図は本発明の他の実施例を説明するための
縦断面図である。すなわち、本発明の一実施例において
は、シリコン半導体基板ｌの表面上に多結晶シリコン半
導体膜２を成長させる際、シランガスから気相成長させ
る通常の方法によっていたが、本実施例としては、５パ
ーセントのＮ２０ガスを含むシランガスを用いてシリコ
ン半導体基板９の表面上に多結晶シリコン半導体膜１０
を成長させる。この多結晶シリコン半導体膜１０には多
量の酸素１１が含まれており、シリコン半導体基板９を
１２００℃、乾燥酸素中で熱処理することにより、これ
らの酸素１１は格子間に放出され、多結晶シリコン半導
体膜ｌＯ中の格子間酸素濃度が高くなるとともに第７図
のようにシリコン半導体基板９中の格子間酸素１２は多
結晶シリコン半導体膜１０が形成されていない側の表面
からのみ外部拡散１３を起こす。FIGS. 6 and 7 are longitudinal cross-sectional views for explaining other embodiments of the present invention. That is, in one embodiment of the present invention, when growing the polycrystalline silicon semiconductor film 2 on the surface of the silicon semiconductor substrate l, the usual method of vapor phase growth from silane gas was used. A polycrystalline silicon semiconductor film 10 is formed on the surface of a silicon semiconductor substrate 9 using silane gas containing 10% N20 gas.
grow. This polycrystalline silicon semiconductor film 10 contains a large amount of oxygen 11, and by heat-treating the silicon semiconductor substrate 9 at 1200° C. in dry oxygen, these oxygens 11 are released between the lattices and the polycrystalline silicon As the interstitial oxygen concentration in the semiconductor film 10 increases, as shown in FIG. wake up
この実施例によれば、直接、酸素を含んだ多結晶シリコ
ン半導体膜を成長するため、イオン注入工程を省略でき
、コスト・時間を大幅に削減できるという利点がある。According to this embodiment, since the polycrystalline silicon semiconductor film containing oxygen is directly grown, the ion implantation process can be omitted, which has the advantage of significantly reducing cost and time.
以上説明したように本発明はシリコン半導体基板の一方
の表面に過飽和に酸素を含んだ多結晶シリコン半導体膜
を形成する工程と、該シリコン半導体基板を１０５０℃
より高い温度で３０分間以上熱処理する工程と、該シリ
コン半導体基板を１０００℃より低い温度で２時間以上
熱処理する工程とを有しており、これによってシリコン
半導体基板に、イントリンシック・ゲッタリング作用に
加えて、効果が強力で長持ちする、クリーンなエクスト
リンシック・ゲッタリング作用を与えることができる効
果がある。As explained above, the present invention includes the steps of forming a polycrystalline silicon semiconductor film containing supersaturated oxygen on one surface of a silicon semiconductor substrate, and heating the silicon semiconductor substrate at 1050°C.
The method includes a step of heat-treating the silicon semiconductor substrate at a higher temperature for 30 minutes or more, and a step of heat-treating the silicon semiconductor substrate at a temperature lower than 1000° C. for 2 hours or more, thereby causing the silicon semiconductor substrate to undergo an intrinsic gettering effect. In addition, it has the effect of providing a clean extrinsic gettering effect that is strong and long-lasting.
第１図〜第５図は本発明の一実施例の主な工程を示す縦
断面図、第６図、第７図は本発明の他の実施例の主な工
程を示す縦断面図である。
■・・・・・・シリコン半導体基板、２・・・・・・多
結晶シリコン半導体膜、３・・・・・・酸素、４・・・
・・・格子間酸素、５・・・・・・外部拡散、６・・・
・・・酸素析出核、７・・・・・・酸素析出物、８・・
・・・・積層欠陥、９・・・・・・シリコン半導体基板
、１０・・・・・・多結晶シリコン半導体膜、１１・・
・・・・酸素、１２・・・・・・格子酸素、１３・・・
・・・外部拡散。
代理人 弁理士 内 原 晋
翁
回
筋
旧
図
筋
図
第
り
巳
第
図
筋
回FIGS. 1 to 5 are longitudinal sectional views showing the main steps of one embodiment of the present invention, and FIGS. 6 and 7 are longitudinal sectional views showing the main steps of another embodiment of the invention. . ■...Silicon semiconductor substrate, 2...Polycrystalline silicon semiconductor film, 3...Oxygen, 4...
...Interstitial oxygen, 5...External diffusion, 6...
...Oxygen precipitate nucleus, 7...Oxygen precipitate, 8...
...Stacking fault, 9...Silicon semiconductor substrate, 10...Polycrystalline silicon semiconductor film, 11...
...Oxygen, 12... Lattice oxygen, 13...
...External diffusion. Agent Patent Attorney Shino Uchihara
Claims (1)
だ多結晶シリコン半導体膜を形成する工程と、該シリコ
ン半導体基板を１０５０℃より高い温度で３０分間以上
熱処理する工程と、該シリコン半導体基板を１０００℃
より低い温度で２時間以上熱処理する工程と、前記シリ
コン半導体基板の他方の表面に半導体素子形成する工程
とを有する半導体装置の製造方法。a step of forming a polycrystalline silicon semiconductor film containing supersaturated oxygen on one surface of a silicon semiconductor substrate; a step of heat-treating the silicon semiconductor substrate at a temperature higher than 1050° C. for 30 minutes or more; ℃
A method for manufacturing a semiconductor device, comprising the steps of performing heat treatment at a lower temperature for 2 hours or more, and forming a semiconductor element on the other surface of the silicon semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20048788A JPH0247836A (en) | 1988-08-10 | 1988-08-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20048788A JPH0247836A (en) | 1988-08-10 | 1988-08-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0247836A true JPH0247836A (en) | 1990-02-16 |
Family
ID=16425133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20048788A Pending JPH0247836A (en) | 1988-08-10 | 1988-08-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0247836A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529324A (en) * | 1991-07-22 | 1993-02-05 | Mitsubishi Materials Corp | Manufacture of silicon wafer |
| EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| US5894037A (en) * | 1995-11-22 | 1999-04-13 | Nec Corporation | Silicon semiconductor substrate and method of fabricating the same |
| JP2005311126A (en) * | 2004-04-22 | 2005-11-04 | Shin Etsu Handotai Co Ltd | P-type silicon single-crystal wafer and its manufacturing method |
-
1988
- 1988-08-10 JP JP20048788A patent/JPH0247836A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529324A (en) * | 1991-07-22 | 1993-02-05 | Mitsubishi Materials Corp | Manufacture of silicon wafer |
| EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| EP0635879A3 (en) * | 1993-07-22 | 1996-10-23 | Toshiba Kk | Semiconductor silicon wafer and process for producing it. |
| US5738942A (en) * | 1993-07-22 | 1998-04-14 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
| US5894037A (en) * | 1995-11-22 | 1999-04-13 | Nec Corporation | Silicon semiconductor substrate and method of fabricating the same |
| JP2005311126A (en) * | 2004-04-22 | 2005-11-04 | Shin Etsu Handotai Co Ltd | P-type silicon single-crystal wafer and its manufacturing method |
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