JPH0469435B2 - - Google Patents
Info
- Publication number
- JPH0469435B2 JPH0469435B2 JP59206554A JP20655484A JPH0469435B2 JP H0469435 B2 JPH0469435 B2 JP H0469435B2 JP 59206554 A JP59206554 A JP 59206554A JP 20655484 A JP20655484 A JP 20655484A JP H0469435 B2 JPH0469435 B2 JP H0469435B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- mis
- diffused
- semiconductor device
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002184 metal Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 230000005669 field effect Effects 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0865—Disposition
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にシリコンゲー
ト電極層とAl等の金属配線層が複層された金属
ゲート電極を有する絶縁ゲート型電界効果トラン
ジスタを含む半導体装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an insulated gate field effect transistor having a metal gate electrode in which a silicon gate electrode layer and a metal wiring layer such as Al are multilayered. The present invention relates to a semiconductor device including the present invention.
従来の二重拡散型MIS FETは高周波、高出力
用の絶縁ゲート型電界効果トランジスタ（以下
MIS TRと記す）として使用されその構造は第２
図ａ，ｂに示すとおりである。第２図ａは上面
図、第２図ｂはＡ−A′部断面図である。第２図
ａ，ｂにおいて、１は半導体基板でMIS TRのド
レイン領域となる。２はベース領域でチヤネル形
成領域である。又３及び３′はソース領域、４は
多結晶シリコンゲート電極、５は絶縁膜、６はソ
ース電極、７は金属ゲート電極層でこの部分では
金属ゲート電極は第１層のシリコンゲート電極層
とAl等の金属配線層の積層構造となつている。
８はチヤネル形成部、９はゲート絶縁膜である。
以上のようにソース電極６と半導体基板１の間に
並列に形成された複数個の二重拡散型MOS
FETにより構成される。MIS TRのスイツチン
グ・スピードは、そのMIS TRを構成する半導体
装置の主表面に選択的に積層形成される材料とパ
タンによつて決まる入力容量（Ciss）とゲート抵
抗（RG）によつて決定され、スピードを上げる
ためには、入力容量とゲート抵抗を小さくしなけ
ればならない。
The conventional double-diffused MIS FET is an insulated gate field effect transistor (hereinafter referred to as
MIS T R ) and its structure is the second
As shown in Figures a and b. FIG. 2a is a top view, and FIG. 2b is a sectional view taken along line A-A'. In FIGS. 2a and 2b, 1 is a semiconductor substrate which becomes the drain region of the MISTR . 2 is a base region and a channel forming region. Further, 3 and 3' are source regions, 4 is a polycrystalline silicon gate electrode, 5 is an insulating film, 6 is a source electrode, and 7 is a metal gate electrode layer, and in this part, the metal gate electrode is the first silicon gate electrode layer. It has a laminated structure of metal wiring layers such as Al.
8 is a channel forming portion, and 9 is a gate insulating film.
As described above, a plurality of double diffused MOSs are formed in parallel between the source electrode 6 and the semiconductor substrate 1.
Consists of FET. The switching speed of MIS TR is determined by the input capacitance (Ciss) and gate resistance (R G ), which are determined by the materials and patterns selectively laminated on the main surface of the semiconductor device that makes up the MIS TR . To increase speed, input capacitance and gate resistance must be reduced.
ゲート電極として多結晶シリコンに不純物拡散
した電極層を用いる構造のMIS TRにおいては、
一般に多結晶シリコンの電極抵抗率が高いために
ゲート抵抗が大きくなり、スイツチングスピード
が遅くなる。そのため多結晶のシリコンをゲート
電極層として使用する場合はそのゲート抵抗を下
げるためAl等の電気抵抗率の小さい金属配線層
を選択的に積層する方法がとられる。Al等の金
属層と多結晶シリコンの層抵抗は金属の方が３桁
程度小さいため、MIS TRにゲート信号を入力し
スイツチングをさせる場合、初期のスイツチング
電流は多結晶シリコンゲート電極上に選択的に積
層配線された金属配線層の付近から流れ始める。
ゲート信号が高速になる程この傾向が強くなる。
従来は第２図ａ，ｂに例を示すように、ゲート電
極の金属配線層７に隣接した部分にもソース領域
３′を形成していたため製造工程中に生じる８の
部分のチヤネル形成部のチヤネル長のバラツキ
で、チヤネル長の短くなつた部分に電流が集中し
やすく、高速スイツチングが必要な高周波で使用
すると、スイツチングの初期の段階でこのチヤネ
ルの短い部分に電流集中が生じ半導体装置が破壊
することがあつた。
In MIS TR , which uses an electrode layer in which impurities are diffused into polycrystalline silicon as a gate electrode,
Generally, polycrystalline silicon has a high electrode resistivity, which increases gate resistance and slows down switching speed. Therefore, when polycrystalline silicon is used as a gate electrode layer, a method is used in which a metal wiring layer with low electrical resistivity, such as Al, is selectively laminated in order to lower the gate resistance. The layer resistance of a metal layer such as Al and polycrystalline silicon is about three orders of magnitude lower, so when inputting a gate signal to MIS TR to perform switching, the initial switching current is selected on the polycrystalline silicon gate electrode. It begins to flow near the metal wiring layer where the wiring is laminated.
This tendency becomes stronger as the gate signal becomes faster.
Conventionally, as shown in FIGS. 2a and 2b, the source region 3' was also formed in the part adjacent to the metal wiring layer 7 of the gate electrode, so that the channel forming part at part 8, which occurs during the manufacturing process, was Due to variations in channel length, current tends to concentrate in the shortened portion of the channel, and when used at high frequencies that require high-speed switching, current concentration occurs in the short portion of the channel in the early stages of switching, resulting in damage to the semiconductor device. I had something to do.
本発明はこれらの問題点を除去改良する構造を
提供することを目的とする。 The object of the present invention is to provide a structure that eliminates and improves these problems.
本発明の半導体装置は、基板上に同一形状の二
重拡散領域を配列してなり、シリコンゲート電極
を有する複数個の縦型二重拡散型MIS−FETが
並列接続して構成され、前記縦型二重拡散型MIS
−FETの一部がシリコンゲート電極層とAl等の
金属配線層の積層された金属ゲート電極を備えて
なる半導体装置において、前記積層された金属ゲ
ート電極に隣接した縦型二重拡散型MIS−FET
のソース領域が削除されていることを特徴として
構成される。
The semiconductor device of the present invention is formed by arranging double-diffused regions of the same shape on a substrate, and is configured by connecting in parallel a plurality of vertical double-diffused MIS-FETs each having a silicon gate electrode. type double diffusion type MIS
- In a semiconductor device in which a part of the FET includes a metal gate electrode in which a silicon gate electrode layer and a metal wiring layer such as Al are stacked, a vertical double diffusion type MIS adjacent to the stacked metal gate electrode - FET
The source area is deleted.
次に、本発明について、図面を参照して説明す
る。
Next, the present invention will be explained with reference to the drawings.
第１図ａ，ｂは本発明の一実施例の上面図及び
そのＢ−B′部の断面図である。第１図ａ，ｂに
おいて従来例の第２図ａ，ｂと同一部分は同一番
号を付してある。第１図ａ，ｂからわかるよう
に、シリコンゲート電極４上に選択積層配線され
た金属電極層７に隣接した部分のソース領域（第
２図ａ，ｂの３′相当部分）を削除した構造とな
つている。このような削除した構造にすることに
より従来構造で発生したチヤネル長のバラツキ
で、チヤネル長の短くなつた部分に電流が集中し
やすく、高速スイツチングが必要な高周波で使用
すると、スイツチングの初期の段階でこのチヤネ
ルの短い部分に電流が集中し半導体装置を破壊し
たが、この部分を削除することにより高周波で安
定動作が可能となつた。 FIGS. 1a and 1b are a top view of an embodiment of the present invention and a sectional view taken along line B-B' thereof. In FIGS. 1a and 1b, the same parts as in FIGS. 2a and 2b of the conventional example are given the same numbers. As can be seen from FIGS. 1a and b, the structure is such that the source region adjacent to the metal electrode layer 7 selectively laminated on the silicon gate electrode 4 (corresponding to 3' in FIGS. 2a and b) is removed. It is becoming. Due to the channel length variations that occur in the conventional structure, current tends to concentrate in the shortened portion of the channel, and when used at high frequencies where high-speed switching is required, the initial stage of switching Current was concentrated in a short part of this channel, destroying the semiconductor device, but by removing this part, stable operation at high frequencies became possible.
以上説明したとおり、本発明によれば、従来構
造に比較して電流集中現象が起こりにくくなり、
高周波で安定動作が可能な絶縁ゲート型電界効果
トランジスタが得られる。
As explained above, according to the present invention, the current concentration phenomenon is less likely to occur compared to the conventional structure,
An insulated gate field effect transistor capable of stable operation at high frequencies can be obtained.
第１図ａ，ｂは本発明の一実施例の上面図及び
そのＢ−B′部断面図、第２図ａ，ｂは従来の二
重拡散型MOS FETの上面図及びそのＡ−A′断
面図である。
１……半導体基板、２……ベース領域、３，
３′……ソース領域、４……多結晶シリコンゲー
ト電極、５……絶縁膜、６……ソース電極、７…
…金属ゲート電極層、８……チヤネル形成部、９
……ゲート絶縁膜。
Figures 1a and b are a top view of an embodiment of the present invention and a sectional view taken along the line B-B', and Figures 2a and b are top views of a conventional double-diffused MOS FET and a cross-sectional view taken along the line A-A'. FIG. 1...Semiconductor substrate, 2...Base region, 3,
3'... Source region, 4... Polycrystalline silicon gate electrode, 5... Insulating film, 6... Source electrode, 7...
...Metal gate electrode layer, 8...Channel forming part, 9
...Gate insulating film.
Claims (1)
なり、シリコンゲート電極を有する複数個の縦型
二重拡散型MIS−FETが並列接続して構成され、
前記縦型二重拡散型MIS−FETの一部がシリコ
ンゲート電極層とAl等の金属配線層の積層され
た金属ゲート電極を備えてなる半導体装置におい
て、前記積層された金属ゲート電極に隣接した縦
型二重拡散型MIS−FETのソース領域が削除さ
れていることを特徴とする半導体装置。1 Consisting of double diffused regions of the same shape arranged on a substrate, and a plurality of vertical double diffused MIS-FETs each having a silicon gate electrode connected in parallel,
In a semiconductor device in which a part of the vertical double-diffused MIS-FET includes a metal gate electrode in which a silicon gate electrode layer and a metal wiring layer such as Al are laminated, a portion adjacent to the laminated metal gate electrode A semiconductor device characterized in that a source region of a vertical double-diffused MIS-FET is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59206554A JPS6184865A (en) | 1984-10-02 | 1984-10-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59206554A JPS6184865A (en) | 1984-10-02 | 1984-10-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6184865A JPS6184865A (en) | 1986-04-30 |
| JPH0469435B2 true JPH0469435B2 (en) | 1992-11-06 |
Family
ID=16525310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59206554A Granted JPS6184865A (en) | 1984-10-02 | 1984-10-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6184865A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2785271B2 (en) * | 1988-04-28 | 1998-08-13 | 富士電機株式会社 | Semiconductor device |
| JPH0828503B2 (en) * | 1988-05-18 | 1996-03-21 | 富士電機株式会社 | MOS semiconductor device |
| JPH02312280A (en) * | 1989-05-26 | 1990-12-27 | Mitsubishi Electric Corp | Insulated gate bipolar transistor |
| JPH0783125B2 (en) * | 1989-06-12 | 1995-09-06 | 株式会社日立製作所 | Semiconductor device |
| JP2817536B2 (en) * | 1991-09-27 | 1998-10-30 | 日本電気株式会社 | Semiconductor device |
| US5430314A (en) * | 1992-04-23 | 1995-07-04 | Siliconix Incorporated | Power device with buffered gate shield region |
| US5544038A (en) * | 1992-09-21 | 1996-08-06 | General Electric Company | Synchronous rectifier package for high-efficiency operation |
| US6037631A (en) * | 1998-09-18 | 2000-03-14 | Siemens Aktiengesellschaft | Semiconductor component with a high-voltage endurance edge structure |
-
1984
- 1984-10-02 JP JP59206554A patent/JPS6184865A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6184865A (en) | 1986-04-30 |
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