JPH0463451A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0463451A JPH0463451A JP17587990A JP17587990A JPH0463451A JP H0463451 A JPH0463451 A JP H0463451A JP 17587990 A JP17587990 A JP 17587990A JP 17587990 A JP17587990 A JP 17587990A JP H0463451 A JPH0463451 A JP H0463451A
- Authority
- JP
- Japan
- Prior art keywords
- support tape
- thin wire
- fine line
- tape
- line leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 claims description 4
- 239000004033 plastic Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 abstract description 20
- 229920005989 resin Polymers 0.000 abstract description 20
- 238000007789 sealing Methods 0.000 abstract description 18
- 230000008602 contraction Effects 0.000 abstract description 4
- 239000000088 plastic resin Substances 0.000 abstract description 2
- 230000002522 swelling effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
半導体のチップのボンディングされた細線リドをサポー
トテープて支持するＴＡＢ方式（ＴａｐｅＡｕｔｏｍａ
ｔｅｄ Ｂｏｎｄｉｎｇ 以下ＴＡＢ方式と呼ぶ）を
用いた半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The TAB method (Tape Automa
The present invention relates to a semiconductor device using ted bonding (hereinafter referred to as TAB method).
ＩＣチップはチップ本体のみては機能しないため、ＩＣ
チップのパッケージングを行い、プリント基板等との接
続を行う。その際、ＩＣチップとリードフレームを細線
リードでボンディングすると細線リードとベースの間に
空隙かでき、この空隙のために封圧樹脂注入の際、細線
リードか振動することがある。この空隙を埋め、細線リ
ードを支持するためにサポートテープが必要になる。さ
らに、細線リードや、サポートテープ、ベース等は各材
質の違いかある。従って、材質が異なっても耐性に優れ
たパッケージングか求められている。IC chips do not function with just the chip body, so
Packages the chip and connects it to printed circuit boards, etc. At this time, when the IC chip and the lead frame are bonded using thin wire leads, a gap is created between the thin wire lead and the base, and this gap may cause the thin wire lead to vibrate when the sealing resin is injected. Support tape is required to fill this void and support the thin wire leads. Furthermore, the thin wire leads, support tape, base, etc. are made of different materials. Therefore, there is a need for packaging that is highly resistant even when made of different materials.
プラスチック封止型ＩＣ素子でＴＡＢ方式を使用した半
導体装置ではＩＣチップとリードフレーム間の細線リー
ドの振動や歪みから保護するために細線リードを支持す
るサポートテープが必要である。In a semiconductor device using a TAB method with a plastic-sealed IC element, a support tape is required to support the thin wire leads between the IC chip and the lead frame in order to protect the thin wire leads from vibration and distortion.
第３図は従来のプラスチック封止型ＩＣの一例を示す。FIG. 3 shows an example of a conventional plastic-sealed IC.
３０は細線リードであり、３１は細線リド３０を支持す
るためのサポートテープてあり、３２はＩＣチップ、３
３はリードフレームである。30 is a thin wire lead, 31 is a support tape for supporting the thin wire lead 30, 32 is an IC chip, 3
3 is a lead frame.
封止はＩＣチップ３２に悪影響を及ぼす塵埃、薬品、湿
気や、機械的な破壊から保護するためになされる。The sealing is performed to protect the IC chip 32 from dust, chemicals, moisture, and mechanical damage that may adversely affect the IC chip 32.
ＩＣチップ３２は細線リード３０てリードフレーム３３
にボンディングされており、サポートテープ３１は細線
リード３０とリードフレーム３３の間にてきる空隙で細
線リード３０を支持するために設けられている。The IC chip 32 is attached to a lead frame 33 using a thin wire lead 30.
The support tape 31 is provided to support the thin wire lead 30 in the gap between the thin wire lead 30 and the lead frame 33.
また、第４図は従来のＴＡＢ方式プラスチック封止型Ｉ
Ｃの一例の断面図を示す。第３図と同一構成部分には同
一符号を付し、その説明を省略する。４０は封止樹脂て
細線リード３０やサポートテープ３１を封止する。樹脂
封止は樹脂をトランスファーモールドにより注入し、Ｉ
Ｃチップ３２表面に密着し、完全に被覆する。Also, Figure 4 shows the conventional TAB type plastic sealed type I.
A sectional view of an example of C is shown. Components that are the same as those in FIG. 3 are given the same reference numerals, and their explanations will be omitted. 40 seals the thin wire leads 30 and support tape 31 with a sealing resin. For resin sealing, resin is injected using a transfer mold.
It comes into close contact with the surface of the C chip 32 and completely covers it.
細線リード３０を支持するサポートテープ３１の材質は
吸湿性のあるカプトン（ポリイミド膜）であるので、封
止すると封止用の樹脂との接着性か悪く、細線リード
３０が振動して位置ずれや切断を生じることがある。ま
た、サポートテープ３１と細線リード３０とは膨張率が
異なるために細線リード３０がテープの膨張や収縮のた
めに切断されることもあるという問題かある。The material of the support tape 31 that supports the thin wire lead 30 is hygroscopic Kapton (polyimide film), so when it is sealed, it has poor adhesion with the sealing resin, and the thin wire lead
30 may vibrate, causing misalignment or cutting. Further, since the support tape 31 and the thin wire lead 30 have different expansion rates, there is a problem that the thin wire lead 30 may be cut due to expansion or contraction of the tape.
さらに封止する樹脂はＩＣチップ３２や細線リド３０と
の接着性が弱いために、プリント基板等に装着する段階
でパッケージに実装ストレスを与えると、ひび割れを起
こす。Furthermore, since the sealing resin has weak adhesion to the IC chip 32 and the thin wire lid 30, cracks will occur if mounting stress is applied to the package at the stage of mounting it on a printed circuit board or the like.
また、第４図中、ａはサポートテープ３１のエツジ部分
と封止樹脂４０との間にてきるひび割れを示す。これは
サポートテープ３１に外力が集中するためや温度変化に
よるもので、その場合ａのようなエツジ部分にひびが入
りやすい等の問題かあった。Further, in FIG. 4, a indicates a crack that occurs between the edge portion of the support tape 31 and the sealing resin 40. This is due to the concentration of external force on the support tape 31 or due to temperature changes, and in this case, there were problems such as cracks easily appearing at the edge portions as shown in a.
本発明は上記の点に鑑みなされたもので封止用樹脂との
接着性を良くし、リードフレーム３３での耐実装ストレ
スを向上させ、細線リード３０の振動による切断等、及
びゃパッケージのひび割れを防ぎ、信頼性のある半導体
装置を提供することを目的とする。The present invention has been made in view of the above points, and improves the adhesiveness with the sealing resin, improves the resistance to mounting stress on the lead frame 33, and prevents the thin wire leads 30 from being cut due to vibration, and cracking of the package. The purpose is to provide a reliable semiconductor device.
上記課題は細線リードを支持するサポートテープに複数
個のスルーホールを設け、また、サポートテープの所定
箇所に面取りを施すように構成することにより解決され
る。The above problem is solved by providing a plurality of through holes in the support tape that supports the thin wire leads, and by chamfering the support tape at predetermined locations.
サポートテープにスルーホールを設けることにより樹脂
がスルーホールに注入され、スルーホールが樹脂で固め
られ、接着性が強くなる。また、応力が集中し易いサポ
ートテープのエツジ部分の面取りを施すことによりエツ
ジ部分に集中する応力を分散する。By providing through holes in the support tape, resin is injected into the through holes, solidifying the through holes with the resin and increasing adhesiveness. Furthermore, by chamfering the edge portions of the support tape where stress tends to concentrate, stress concentrated at the edge portions is dispersed.
第１図は本発明の第１実施例の平面図を示す。 FIG. 1 shows a plan view of a first embodiment of the invention.
同図中、第３図と同一部分には同一符号を付し、その説
明を省略する。１０はサポートテープ、１１はスルーホ
ールである。In the figure, the same parts as in FIG. 3 are given the same reference numerals, and their explanations will be omitted. 10 is a support tape, and 11 is a through hole.
サポートテープ１０は細線リード３０を支持し、細線リ
ード３０はＩＣチップ３２とリードフレム３３をポンデ
ィングしている。The support tape 10 supports a thin wire lead 30, and the thin wire lead 30 bonds an IC chip 32 and a lead frame 33.
テープ状のリードフレーム３３にはＩＯチ・ｙプ３２、
サポートテープ１０か設けられている。細線リード３０
はＩＣチップの電極とボンディングされ、ＩＣチップの
電極はパッド上に形成されている。The tape-shaped lead frame 33 has an IO chip 32,
Support tape 10 is provided. Thin wire lead 30
is bonded to the electrode of the IC chip, and the electrode of the IC chip is formed on the pad.
サポートテープ１０のスルーホール１１はサポートテー
プ１０の全面に任意の配列で複数個設ける。また、これ
によりプラススチック樹脂かサポトテーブＩＯの上下の
どちらからでも注入することかでき、サポートテープｌ
Ｏを挟んて上下に封止樹脂かあるので、封止樹脂に周囲
を固められて細線リード３０と共に固定される。A plurality of through holes 11 of the support tape 10 are provided in an arbitrary arrangement over the entire surface of the support tape 10. Additionally, this allows the plastic resin to be injected from either the top or bottom of the support tape IO.
Since there is sealing resin above and below with O in between, the periphery is hardened by the sealing resin and fixed together with the thin wire lead 30.
スルーホール１１の大きさは例えば５０〜６０ミクロン
の大きさであっても封止樹脂か注入されるには十分であ
り、また、スルーホール１１の数は細線リード３０を支
持することかできる強度の範囲で全体的に多く設けた方
が封止樹脂との接着力か強くなる。Even if the size of the through holes 11 is, for example, 50 to 60 microns, it is sufficient for injecting the sealing resin, and the number of through holes 11 is determined to be strong enough to support the thin wire leads 30. The adhesive force with the sealing resin will be stronger if more is provided overall within the range of .
第２図は本発明の第２実施例の断面図を示す。FIG. 2 shows a cross-sectional view of a second embodiment of the invention.
第１図、第３図と同一部分には同一符号を付し、その説
明を省略する。２０はサポートテープ１０のエツジであ
る。サポートテープ１０を断面から見ると上下４カ所の
エツジかあり、そのうち細線リード３０を支持していな
いほうの下部の２つのエツジ２０の部分に対し、ケミカ
ルエツチングまたはプレスにより面取りを施す。Components that are the same as those in FIGS. 1 and 3 are designated by the same reference numerals, and their explanations will be omitted. 20 is the edge of the support tape 10. When the support tape 10 is viewed from a cross section, there are four edges at the top and bottom, of which the two lower edges 20 that do not support the thin wire leads 30 are chamfered by chemical etching or pressing.
これにより封止樹脂２１を注入したときサポートテープ
のエツジ２０との接着面か円弧状であるので、いままで
サポートテープ１０のエツジ２０に集中していた応力が
分散される。As a result, when the sealing resin 21 is injected, the bonding surface with the edge 20 of the support tape is arcuate, so that the stress that has been concentrated on the edge 20 of the support tape 10 is dispersed.
従って、本発明の実施例でのリードフレーム３３におい
て、耐実装ストレスのパッケージクラック性では許容吸
湿時間が２倍以上となる。Therefore, in the lead frame 33 according to the embodiment of the present invention, the permissible moisture absorption time is more than twice as long as the package crack resistance of the mounting stress resistance.
以上のように本発明によればサポートテープにスルーホ
ールを設けることにより封止樹脂かサポートテープのス
ルーホールに注入される。これによりアンカー効果が生
じ、サポートテープの周囲か固められ、接着性か向上し
、細線リートの振動や、膨張、収縮による細線リードの
断線が防止できる。As described above, according to the present invention, by providing a through hole in the support tape, the sealing resin is injected into the through hole of the support tape. This creates an anchor effect, hardens the area around the support tape, improves adhesion, and prevents vibration of the fine wire lead and breakage of the fine wire lead due to expansion and contraction.
また、サポートテープのエツジの面取りを行うことによ
りエツジに集中する力か拡散し、ＩＣチップの中部に応
力か集中してもその衝撃か和らげられる。また、実装の
時に膨張・収縮によるひび割れ等が起こり難くなり信頼
性の向上か図れるという特長がある。Furthermore, by chamfering the edges of the support tape, the force concentrated on the edges is diffused, and even if stress is concentrated in the middle of the IC chip, the impact can be softened. Another advantage is that cracks due to expansion and contraction are less likely to occur during mounting, thereby improving reliability.
第４図は従来のプラスチック封止型ＩＣの断面図である
。FIG. 4 is a sectional view of a conventional plastic-sealed IC.
図において、 ＩＯはサポートテープ、 １１はスルーホール、 ３０は細線リード、 ３２はＩＣチップ、 ３３はリードフレーム、 ２０はエツジ、 ４０は封止樹脂、 ４１はパッド を示す。In the figure, IO is support tape, 11 is a through hole, 30 is a thin wire lead, 32 is an IC chip, 33 is a lead frame, 20 is Etsuji, 40 is a sealing resin; 41 is a pad shows.
第１図は本発明の第１実施例の平面図、第２図は本発明
の第２実施例の断面図、第３図は従来のプラスチック封
止型ＩＣの平面図、
本発明の第１実施例の平面図
第
図
本発明の第２実施例の断面図
第
図
従来のプラスチック封止型ＩＣの平面同第
図
従来のプラスチック封止型ＩＣの断面同第
図FIG. 1 is a plan view of a first embodiment of the present invention, FIG. 2 is a sectional view of a second embodiment of the present invention, and FIG. 3 is a plan view of a conventional plastic-sealed IC. A plan view of the embodiment A cross-sectional view of a second embodiment of the present invention A plan view of a conventional plastic-sealed IC A cross-sectional view of a conventional plastic-sealed IC
Claims (2)
テープキャリア方式を使用し、サポートテープ（１０）
で前記ＩＣに設けられた電極と外部とを接続する複数本
の細線リード（１２）を支持する半導体装置において、 前記サポートテープ（１０）に複数個のスルーホール（
１１）を設けることを特徴とする半導体装置。(1) A tape carrier method is used in a package where the IC is sealed with plastic, and support tape (10) is used.
In a semiconductor device that supports a plurality of thin wire leads (12) connecting electrodes provided on the IC and the outside, the support tape (10) has a plurality of through holes (
11) A semiconductor device comprising:
を施すことを特徴とする請求項１記載の半導体装置。(2) The semiconductor device according to claim 1, wherein a predetermined portion of the support tape (10) is chamfered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17587990A JP2815984B2 (en) | 1990-07-03 | 1990-07-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17587990A JP2815984B2 (en) | 1990-07-03 | 1990-07-03 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0463451A true JPH0463451A (en) | 1992-02-28 |
| JP2815984B2 JP2815984B2 (en) | 1998-10-27 |
Family
ID=16003810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17587990A Expired - Fee Related JP2815984B2 (en) | 1990-07-03 | 1990-07-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2815984B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0627766A1 (en) * | 1993-06-04 | 1994-12-07 | Seiko Epson Corporation | Semiconductor device and manufacturing method thereof |
| US5970320A (en) * | 1993-06-04 | 1999-10-19 | Seiko Epson Corporation | Process of resin sealing a semiconductor device and lead frame |
-
1990
- 1990-07-03 JP JP17587990A patent/JP2815984B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0627766A1 (en) * | 1993-06-04 | 1994-12-07 | Seiko Epson Corporation | Semiconductor device and manufacturing method thereof |
| US5554885A (en) * | 1993-06-04 | 1996-09-10 | Seiko Epson Corporation | Semiconductor device including means for dispersing and absorbing tensile forces acting on film tape |
| US5970320A (en) * | 1993-06-04 | 1999-10-19 | Seiko Epson Corporation | Process of resin sealing a semiconductor device and lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2815984B2 (en) | 1998-10-27 |
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