JPH04590B2 - - Google Patents

Info

Publication number
JPH04590B2
JPH04590B2 JP59258520A JP25852084A JPH04590B2 JP H04590 B2 JPH04590 B2 JP H04590B2 JP 59258520 A JP59258520 A JP 59258520A JP 25852084 A JP25852084 A JP 25852084A JP H04590 B2 JPH04590 B2 JP H04590B2
Authority
JP
Japan
Prior art keywords
film
conductivity type
region
forming
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59258520A
Other languages
Japanese (ja)
Other versions
JPS61136266A (en
Inventor
Takao Ito
Yasuhiro Katsumata
Kyoshi Takaoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP59258520A priority Critical patent/JPS61136266A/en
Priority to DE8585109543T priority patent/DE3580206D1/en
Priority to EP19850109543 priority patent/EP0170250B1/en
Publication of JPS61136266A publication Critical patent/JPS61136266A/en
Publication of JPH04590B2 publication Critical patent/JPH04590B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はバイポーラ型半導体装置の製造方法に
関し、特に、セルフアライン方式により外部ベー
ス／エミツタ間の距離を縮小してベース抵抗を下
げ、高速動作を可能としたバイポーラ型半導体装
置を製造する方法の改良に係る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a bipolar semiconductor device, and in particular, to a method for manufacturing a bipolar semiconductor device, in particular, a self-align method is used to reduce the distance between an external base and an emitter to lower base resistance and achieve high-speed operation. This invention relates to an improvement in a method for manufacturing a bipolar semiconductor device.

〔発明の技術的背景〕[Technical background of the invention]

バイポーラ型半導体装置の高速動作特性および
高周波特性を改善するために従来行なわれている
方法は、イオン注入法による浅い接合の形成、溝
切り構造等による基板／コレクタ間の寄生容量の
低減、自己整合法等の微細加工技術によるベー
ス／コレクタ間、ベース／エミツタ間の寄生容量
を低減することである。 Conventionally used methods to improve the high-speed operating characteristics and high-frequency characteristics of bipolar semiconductor devices include forming shallow junctions using ion implantation, reducing parasitic capacitance between the substrate and collector using grooved structures, and self-alignment. The goal is to reduce the parasitic capacitance between the base and the collector and between the base and the emitter using microfabrication techniques such as the method.

例えば、特公昭57−41826号公報には、多結晶
シリコン層からなるベース取出し電極を採用する
ことによりベース／コレクタ間の容量を低減する
技術が開示されている。 For example, Japanese Patent Publication No. 57-41826 discloses a technique for reducing the base-collector capacitance by employing a base lead-out electrode made of a polycrystalline silicon layer.

また、特開昭57−53979号公報には、多結晶シ
リコン層からなるベース取出し電極を拡散源とし
て外部ベース領域を形成した後、このベース取出
し電極側壁に形成したサブミクロン膜厚の酸化膜
を利用して活性ベース領域とエミツタ領域とを自
己整合で形成することにより、ベース抵抗を低減
する技術が開示されている。これと同様な技術
は、特公昭56−4457号公報、特開昭57−186360号
公報、特開昭57−186359号公報、特開昭57−
188872号公報にも開示されている。 Furthermore, Japanese Patent Laid-Open No. 57-53979 discloses that after an external base region is formed using a base lead-out electrode made of a polycrystalline silicon layer as a diffusion source, an oxide film with a submicron thickness is formed on the side walls of the base lead-out electrode. A technique has been disclosed for reducing base resistance by forming an active base region and an emitter region in self-alignment. Techniques similar to this are disclosed in Japanese Patent Publication No. 56-4457, Japanese Patent Application Laid-open No. 186360-1982, Japanese Patent Application Laid-Open No. 186359-1982,
It is also disclosed in Publication No. 188872.

更に、特公昭55−26630号公報、特公昭55−
27469号公報、特公昭57−32511号公報には、多結
晶シリコン層からなるベース取出し電極の形成に
際し、酸化膜等の段差を利用した自己整合技術を
導入してベース／コレクタ間容量を低減する技術
が開示されている。 Furthermore, Special Publication No. 55-26630, Special Publication No. 55-26630,
Publication No. 27469 and Japanese Patent Publication No. 57-32511 introduce a self-alignment technique that utilizes steps such as oxide films to reduce the base-collector capacitance when forming a base lead-out electrode made of a polycrystalline silicon layer. The technology has been disclosed.

上記の公知技術の他、本発明の関連技術として
は出願人が特願昭59−160518号として先に出願し
たものが挙げられる。この先願発明は、多結晶シ
リコン膜および金属シリサイド膜の積層膜からな
るベース取出し電極を用いることによりベース抵
抗を更に低減し、高速動作および高周波特性を一
段と向上することを可能としたものである。 In addition to the above-mentioned known technology, related technology to the present invention includes the technology previously filed by the applicant as Japanese Patent Application No. 160518/1983. This prior invention makes it possible to further reduce base resistance and further improve high-speed operation and high-frequency characteristics by using a base lead-out electrode made of a laminated film of a polycrystalline silicon film and a metal silicide film.

〔背景技術の問題点〕[Problems with background technology]

前掲の公知技術においても寄生容量の低減につ
いては略満足できる程度に達成されていると考え
られる。しかし、多結晶シリコンの層抵抗は単結
晶シリコンに同量の不純物を添加した場合に比較
して約３〜５倍の高い値になるため、多結晶シリ
コン層をベース取出し電極に用いた公知技術では
全体的なベース抵抗rbb′が高くならざるを得ず、
高速動作特性について満足できる結果が得られな
い。そこで、ベース取出し電極用の多結晶シリコ
ン層の膜厚を4000〜6000Åと厚くしてベース取出
し電極の抵抗を下げるようにしているが、それで
も50〜500Ω／□程度の値しか得られていない。 It is considered that the above-mentioned known technology also achieves a substantially satisfactory reduction in parasitic capacitance. However, since the layer resistance of polycrystalline silicon is about 3 to 5 times higher than that of single crystal silicon with the same amount of impurities added, the known technology using a polycrystalline silicon layer as the base lead-out electrode Then, the overall base resistance rbb′ must be high,
Satisfactory results regarding high-speed operation characteristics cannot be obtained. Therefore, attempts have been made to increase the thickness of the polycrystalline silicon layer for the base lead-out electrode to 4,000 to 6,000 Å to lower the resistance of the base lead-out electrode, but even so, a value of only about 50 to 500 Ω/□ is obtained.

また、前掲の公知技術は製造プロセス上の観点
から第１０図〜第１２図に示すような問題があつ
た。即ち、これらの公知技術においては、第１０
図に示すように選択的にフイールド酸化膜２２が
形成されているＮ型エピタキシヤルシリコン層２
１の上にベース取出し電極用の多結晶シリコン層
（ボロン添加）２３を堆積した後、イオンミリン
グ等の方法を用いて該多結晶シリコン層２３に活
性ベース領域形成用の拡散窓２４を開孔し、エピ
タキシヤル層２１表面を露出する工程が含まれて
いる。この場合、多結晶シリコン層２３およびエ
ピタキシヤルシリコン層２１が同一物質でエツチ
ングされる速度が略同じであることから、エツチ
ング終了の判定がめて困難である。そのため、多
結晶シリコン層２３の膜厚のバラツキを考慮して
オーバーエツチングすることが一般的に行なわれ
る結果、第１１図に示したように、エピタキシヤ
ル層２１の表面が多結晶シリコン層２３の膜厚
（4000〜6000Å）の20〜50％、即ち、0.1〜0.3μm
程度削られてしまう事態が発生することになる。
その結果、多結晶シリコン層２３を拡散源として
P+型の外部ベース領域２５を形成した後、開孔
部２４からボロンのイオン注入等によりＰ型活性
ベース領域２６を形成したときに、第１２図に示
したように両領域２５，２６が短絡せずに分離し
てしまい、正常なトランジスタ動作が得られなく
なるという問題を生じていた。なお、第１２図に
おいて、２７は層間絶縁膜としてCVD−SiO2膜、
２８はCVD−SiO2膜２７に開孔した拡散窓から
燐をドープして形成されたN+型エミツタ領域、
２９はエミツタ電極である。 Further, the above-mentioned known technology has problems as shown in FIGS. 10 to 12 from the viewpoint of the manufacturing process. That is, in these known techniques, the 10th
As shown in the figure, an N-type epitaxial silicon layer 2 on which a field oxide film 22 is selectively formed.
After depositing a polycrystalline silicon layer (boron-added) 23 for a base extraction electrode on top of the polycrystalline silicon layer 23, a diffusion window 24 for forming an active base region is opened in the polycrystalline silicon layer 23 using a method such as ion milling. However, a step of exposing the surface of the epitaxial layer 21 is included. In this case, since the polycrystalline silicon layer 23 and the epitaxial silicon layer 21 are etched with the same material at substantially the same speed, it is very difficult to determine whether etching has ended. Therefore, over-etching is generally performed taking into consideration the variation in the thickness of the polycrystalline silicon layer 23, and as a result, the surface of the epitaxial layer 21 is slightly larger than that of the polycrystalline silicon layer 23, as shown in FIG. 20-50% of film thickness (4000-6000Å), i.e. 0.1-0.3μm
A situation will occur where the amount will be reduced to a certain extent.
As a result, the polycrystalline silicon layer 23 is used as a diffusion source.
After forming the P + type external base region 25, when forming the P type active base region 26 by implanting boron ions through the opening 24, both regions 25 and 26 are formed as shown in FIG. A problem has arisen in that the transistors are separated without being short-circuited, making it impossible to obtain normal transistor operation. In addition, in FIG. 12, 27 is a CVD-SiO 2 film as an interlayer insulating film,
28 is an N + type emitter region formed by doping phosphorus through a diffusion window opened in the CVD-SiO 2 film 27;
29 is an emitter electrode.

なお、上記第１０図〜第１２図で説明した問題
を防止する方法として、例えば特公昭55−26630
号公報には、イオンミリングで前記開孔部２４を
形成する際に多結晶シリコン層２３を極く薄く残
し（例えば1000Å程度）、然る後にケミカルエツ
チングによりエピタキシヤル層表面を露出させ、
或いは多結晶シリコン層を熱酸化して除去する繰
り返すことによりエピタキシヤル層表面を露出さ
せる方法が記載されている。しかし、この方法で
は工程が複雑化せざるを得ず、またケミカルエツ
チングや熱酸化では等方的に多結晶シリコン層が
除去されるから開孔部２４の大きさにバラツキを
生じるという問題を有している。 In addition, as a method for preventing the problems explained in FIGS. 10 to 12 above, for example,
The publication discloses that when forming the openings 24 by ion milling, the polycrystalline silicon layer 23 is left extremely thin (for example, about 1000 Å), and then the surface of the epitaxial layer is exposed by chemical etching.
Alternatively, a method is described in which the surface of an epitaxial layer is exposed by repeatedly thermally oxidizing and removing a polycrystalline silicon layer. However, this method inevitably complicates the process, and chemical etching and thermal oxidation remove the polycrystalline silicon layer isotropically, resulting in variations in the size of the openings 24. are doing.

他方、出願人の先願に係る特願昭59−160518号
の方法ではベース取出し電極を構成する多結晶シ
リコン層の上に金属シリサイド膜を積層したか
ら、高速動作特性のためベース抵抗rbb′を低減す
る課題は略達成することができた。しかし、この
場合にも開孔部２４の形成に際してエピタキシヤ
ル層表面を0.1〜0.2μmエツチングしてしまうこと
になり、第１０図〜第１２図で説明した問題につ
いては既述の公知例と同様の問題を有している。 On the other hand, in the method of Japanese Patent Application No. 160518/1989, which is related to the applicant's earlier application, a metal silicide film is laminated on the polycrystalline silicon layer constituting the base lead-out electrode, so the base resistance rbb′ is reduced for high-speed operation characteristics. We were able to achieve most of the reduction issues. However, in this case as well, the surface of the epitaxial layer is etched by 0.1 to 0.2 μm when forming the opening 24, and the problems explained in FIGS. 10 to 12 are the same as in the previously mentioned known example. I have this problem.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、全
体的なベース抵抗rbb′を低減して高速動作特性お
よび高周波特性に優れたバイポーラ型半導体装置
を製造することができ、且つ外部ベース領域と活
性ベース領域とが短絡しなくなる事態を回避でき
る安定した製造方法を提供しようとするものであ
る。 The present invention has been made in view of the above circumstances, and it is possible to manufacture a bipolar semiconductor device that reduces the overall base resistance rbb' and has excellent high-speed operation characteristics and high-frequency characteristics, and that The purpose is to provide a stable manufacturing method that can avoid short circuits with the base region.

〔発明の概要〕[Summary of the invention]

本発明によるバイポーラ型半導体装置の製造方
法は、第一導電型半導体層の一部上に非単結晶シ
リコン膜および金属シリサイド膜の積層膜パター
ンを形成する工程と、この積層膜パターンに第二
導電型不純物をドープする工程と、前記積層膜パ
ターンの一部分において、金属シリサイドに対し
て選択性を有するエツチング法により前記金属シ
リサイド膜のみをエツチング除去し、当該部分に
おいて前記非単結晶シリコン膜を露出させる工程
と、この非単結晶シリコン膜の露出部分を酸化す
ることにより取出し電極を形成する工程と、熱処
理により前記取出し電極から前記第一導電型半導
体層内に前記不純物を拡散させて第二導電型高濃
度不純物領域を形成する工程と、前記非単結晶シ
リコン膜の酸化領域から前記第一導電型半導体層
に選択的に第二導電型不純物をドープすることに
より、前記第二導電型高濃度不純物領域に接した
第二導電型低濃度不純物領域を形成する工程と、
前記取出し電極を覆う絶縁膜を堆積した後、該絶
縁膜に対して異方性エツチングを施すことにより
前記取出し電極の側壁に絶縁膜を残存させる工程
と、前記第二導電型低濃度不純物領域内に第一導
電型高濃度不純物領域を形成する工程とを具備し
たことを特徴とするものである。 A method for manufacturing a bipolar semiconductor device according to the present invention includes the steps of forming a laminated film pattern of a non-single crystal silicon film and a metal silicide film on a part of a first conductivity type semiconductor layer, and a second conductive film pattern on this laminated film pattern. doping with type impurities, and etching away only the metal silicide film in a part of the laminated film pattern using an etching method that is selective to metal silicide, exposing the non-single crystal silicon film in the part. a step of forming an extraction electrode by oxidizing the exposed portion of the non-single crystal silicon film; and a step of diffusing the impurity from the extraction electrode into the first conductivity type semiconductor layer by heat treatment to form a second conductivity type semiconductor layer. The second conductivity type high concentration impurity is formed by forming a high concentration impurity region and selectively doping the second conductivity type impurity from the oxidized region of the non-single crystal silicon film into the first conductivity type semiconductor layer. forming a second conductivity type low concentration impurity region in contact with the region;
After depositing an insulating film covering the lead-out electrode, the insulating film is anisotropically etched to leave the insulating film on the side wall of the lead-out electrode, and in the second conductivity type low concentration impurity region The method is characterized by comprising a step of forming a first conductivity type high concentration impurity region.

上記本発明の方法は出願人による前述の先願発
明を改良したもので、先願発明による効果をその
まま具備している。即ち、非単結晶シリコン膜お
よび金属シリサイド膜の積層構造からなるベース
取出し電極としたことから、ベース抵抗rbb′を低
減して高速動作特性を改善できる。また、異方性
エツチングで取出し電極の側壁に形成したサブミ
クロン膜厚の絶縁膜を利用し、第二導電型高濃度
不純物領域（外部ベース領域）、第二導電型低濃
度不純物領域（活性ベース領域）および第一導電
型高濃度不純物領域（エミツタ領域）を自己整合
で形成できる。従つて、素子を微細化が可能とな
り、活性ベース領域の層抵抗を低減して高速動作
特性を更に向上できる。 The method of the present invention is an improvement on the aforementioned earlier invention by the applicant, and has the effects of the earlier invention as they are. That is, since the base lead-out electrode has a laminated structure of a non-single-crystal silicon film and a metal silicide film, the base resistance rbb' can be reduced and high-speed operation characteristics can be improved. In addition, by using an insulating film with a submicron thickness formed on the side wall of the extraction electrode by anisotropic etching, a second conductivity type high concentration impurity region (external base region), a second conductivity type low concentration impurity region (active base region) and a second conductivity type low concentration impurity region (active base region) and the first conductivity type high concentration impurity region (emitter region) can be formed by self-alignment. Therefore, it is possible to miniaturize the device, reduce the layer resistance of the active base region, and further improve high-speed operation characteristics.

上記の効果に加え、本発明では前記積層膜パタ
ーンから取出し電極を形成する際のエツチングに
おいて、前記金属シリサイド膜のみを除去して前
記非単結晶シリコン層は残存させ、事後この残存
非単結晶シリコン層部分を酸化することとして
る。従つて、先行開示技術のように半導体層（エ
ピタキシヤル層）の表面までオーバーエツチング
する事態を回避でき、外部ベース領域と活性ベー
ス領域とが短絡しなくなるといつた問題の発生の
防止することができる。 In addition to the above effects, in the present invention, only the metal silicide film is removed and the non-single crystal silicon layer is left in etching when forming the lead-out electrode from the laminated film pattern. The layer portion is oxidized. Therefore, it is possible to avoid the situation where the surface of the semiconductor layer (epitaxial layer) is over-etched as in the prior art, and it is possible to prevent the occurrence of problems such as short-circuiting between the external base region and the active base region. can.

〔発明の実施例〕[Embodiments of the invention]

以下、第１図〜第８図を参照して本発明の一実
施例を説明する。 Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 to 8.

(1) 先ず、Ｐ型シリコン基板１の一部に選択的に
N+型埋込領域２を形成した後、全面にＮ型エ
ピタキシヤルシリコン層３を成長させ、続いて
選択酸化法により膜厚6000〜10000Åのフイー
ルド酸化膜４を形成する。次いで、フイールド
酸化膜４に囲まれたエピタキシヤル層３の一部
にＮ型不純物をドープすることにより、N+コ
レクタコンタクト領域５を形成する。続いて、
LPCVD法により全面に膜厚約500Åの不純物
無添加多結晶シリコン膜６を堆積し、更にスパ
ツタ法により全面に膜厚約3000ÅのMoSi2膜７
を堆積する（第１図々示）。(1) First, selectively coat a part of the P-type silicon substrate 1.
After forming the N + type buried region 2, an N type epitaxial silicon layer 3 is grown on the entire surface, and then a field oxide film 4 having a thickness of 6000 to 10000 Å is formed by selective oxidation. Next, a part of the epitaxial layer 3 surrounded by the field oxide film 4 is doped with N type impurities to form an N + collector contact region 5. continue,
An impurity-free polycrystalline silicon film 6 with a thickness of approximately 500 Å is deposited on the entire surface by the LPCVD method, and a MoSi 2 film 7 with a thickness of approximately 3000 Å is deposited on the entire surface by the sputtering method.
(as shown in the first figure).

(2) 次に、ケミカルドライエツチング（CDE）
或いは反応性イオンエツチング（RIE）により
MoSi2膜７および多結晶シリコン膜６を順次パ
ターンニングして積層膜パターンを形成した
後、該積層膜パターンに対し、加速エネルギー
40〜50keV、ドーズ量1015〜1016／cm2の条件で
選択的にボロンをイオン注入する。続いて、全
面に膜厚3000〜4000ÅのCVD−SiO2膜８を堆
積する（第２図々示）。(2) Next, chemical dry etching (CDE)
Or by reactive ion etching (RIE)
After sequentially patterning the MoSi 2 film 7 and the polycrystalline silicon film 6 to form a laminated film pattern, acceleration energy is applied to the laminated film pattern.
Boron ions are selectively implanted under the conditions of 40 to 50 keV and a dose of 10 15 to 10 16 /cm 2 . Subsequently, a CVD-SiO 2 film 8 having a thickness of 3000 to 4000 Å is deposited on the entire surface (as shown in the second figure).

(3) 次に、活性ベース領域予定部上に開孔部を有
するフオトレジスタパターン９を形成した後、
これをマスクとし、CF4を反応ガスとしたRIE
によりCVD−SiO2膜８をエツチングして開孔
部を形成する。MoSi2膜７が露出した時点で反
応ガスをCl2／O2の混合ガスに切替えてRIEを
続行し、MoSi2膜７のみを除去して多結晶シリ
コン膜６を露出させる（第３図々示）。(3) Next, after forming a photoresistor pattern 9 having an opening on the planned active base region,
RIE using this as a mask and CF 4 as a reaction gas
The CVD-SiO 2 film 8 is etched to form an opening. When the MoSi 2 film 7 is exposed, the reaction gas is switched to a mixed gas of Cl 2 /O 2 and RIE is continued to remove only the MoSi 2 film 7 and expose the polycrystalline silicon film 6 (see Figure 3). (shown).

なお、Cl2／O2を反応ガスとしたRIEによる
MoSi2と多結晶シリコンのエツチング速度は第
９図に示す通りである。図示のように、この
RIEは多結晶シリコンに比較しでMoSi2に対す
る充分な選択性を有しているから、第３図の状
態でエツチングを停止し、多結晶シリコン膜６
を残存させることは容易に行なうことができ
る。 In addition, RIE using Cl 2 /O 2 as a reaction gas
The etching rates of MoSi 2 and polycrystalline silicon are shown in FIG. As shown, this
Since RIE has sufficient selectivity for MoSi 2 compared to polycrystalline silicon, etching is stopped in the state shown in Figure 3, and the polycrystalline silicon film 6 is etched.
It is easy to leave the .

(4) 次に、レジストパターン９を除去した後、熱
酸化を行ない、多結晶シリコン膜６の露出部分
を酸化膜１１に転化することにより、ベース取
出し電極１０を形成する。続いて、1000〜1100
℃で熱処理を行なうことによりMoSi2膜７およ
び多結晶シリコン膜６にドープされたボロンを
拡散させ、P+型外部ベース領域１２を形成す
る。更に、加速エネルギー40keV、ドーズ量
1014／cm2の条件で、前記RIEで形成した開孔部
から選択的にボロンをイオン注入することによ
りP-型活性ベース領域１３を形成する（第４
図々示）。(4) Next, after removing the resist pattern 9, thermal oxidation is performed to convert the exposed portion of the polycrystalline silicon film 6 into an oxide film 11, thereby forming the base lead-out electrode 10. Then 1000-1100
By performing heat treatment at .degree. C., the boron doped into the MoSi 2 film 7 and the polycrystalline silicon film 6 is diffused to form a P + type external base region 12. Furthermore, acceleration energy 40keV, dose amount
A P - type active base region 13 is formed by selectively implanting boron ions through the opening formed by RIE under the condition of 10 14 /cm 2 (fourth step).
(Illustrated).

こうして、P+型外部ベース領域１２および
P-型活性ベース領域１３が自己整合で形成さ
れ、しかもエピタキシヤル層３の表面は従来の
ようにエツチングされていないから、両領域１
２，１３は確実に短絡接続して形成されること
になる。 In this way, the P + type external base region 12 and
Since the P - type active base region 13 is formed in a self-aligned manner and the surface of the epitaxial layer 3 is not etched as in the conventional case, both regions 1
2 and 13 are surely formed in a short-circuit connection.

(5) 次に、全面に膜厚3000〜5000ÅのCVD−
SiO2膜１４を堆積した後、900〜1000℃で熱処
理を行ない、CVD−SiO2膜１４のアニールと
活性ベース領域１３のアニールを行なう（第５
図々示）。(5) Next, apply CVD with a film thickness of 3000 to 5000 Å on the entire surface.
After depositing the SiO 2 film 14, heat treatment is performed at 900 to 1000°C to anneal the CVD-SiO 2 film 14 and the active base region 13 (fifth
(Illustrated).

(6) 次に、CF4を用いたRIEによりCVD−SiO2膜
１４および熱酸化膜１１をエツチングすること
により、取出し電極１０およびCVD酸化膜８
の側壁にCVD−SiO2膜１４′を残存させる。続
いて、RIEにより活性ベース領域１３の表面に
生じたダメージをアルカリウエツトエツチング
により除去する（第６図々示）。(6) Next, by etching the CVD-SiO 2 film 14 and the thermal oxide film 11 by RIE using CF 4 , the extraction electrode 10 and the CVD oxide film 8 are removed.
A CVD-SiO 2 film 14' is left on the side wall of the substrate. Subsequently, damage caused to the surface of the active base region 13 by RIE is removed by alkaline wet etching (as shown in FIG. 6).

(7) 次に、全面に多結晶シリコン膜を堆積した
後、該多結晶シリコン膜に対し加速エネルギー
40〜50keV、ドーズ量1015〜1016／cm2の条件で
燐もしくは砒素、或いは燐および砒素の両者を
イオン注入する。次いで、この多結晶シリコン
膜をパターンニングしてＮ型多結晶シリコンパ
ターン１５を形成した後、800〜900℃で数10分
間熱処理を行なうことによりＮ型多結晶シリコ
ンパターン１５から不純物を拡散させ、N+エ
ミツタ領域１６を形成する（第７図々示）。(7) Next, after depositing a polycrystalline silicon film on the entire surface, acceleration energy is applied to the polycrystalline silicon film.
Phosphorus or arsenic, or both phosphorus and arsenic, is ion-implanted under conditions of 40 to 50 keV and a dose of 10 15 to 10 16 /cm 2 . Next, after patterning this polycrystalline silicon film to form an N-type polycrystalline silicon pattern 15, heat treatment is performed at 800 to 900° C. for several tens of minutes to diffuse impurities from the N-type polycrystalline silicon pattern 15. An N + emitter region 16 is formed (shown in FIG. 7).

(8) 次に、CVD−SiO2膜８の所定位置を選択的
にエツチングしてコンタクトホールを加工した
後、全面に配線金属層を堆積し、これをパター
ンニングしてエミツタ電極１７、ベース電極１
８およびコレクタ電極１９を形成する（第８
図々示）。続いて、全面にパツシベーシヨン膜
を堆積し、表面安定化等の最終処理を施して目
的のバイポーラ型半導体装置を得る。(8) Next, after forming contact holes by selectively etching predetermined positions of the CVD-SiO 2 film 8, a wiring metal layer is deposited on the entire surface, and this is patterned to form emitter electrodes 17 and base electrodes. 1
8 and collector electrode 19 (eighth
(Illustrated). Subsequently, a passivation film is deposited on the entire surface, and final treatments such as surface stabilization are performed to obtain the desired bipolar semiconductor device.

上記実施例によれば、既述したように外部ベー
ス領域１２と活性ベース領域１３とが短絡しない
でオープン状態になる危具がない。しかも、
MoSi2膜７と多結晶シリコン膜６とのエツチング
レートが異なるためエツチング終了時の判定が容
易で、工程管理上も有利である。また、ベース取
出し電極１０を多結晶シリコン膜６と高温熱処理
に耐えるMoSi2膜７との積層膜で構成したため、
抵抗率の低いMoSi2膜７の寄与により取出し電極
１０の層抵抗を低減することができる。例えば、
多結晶シリコン膜６の厚さを500Åとし、MoSi2
膜７の膜厚を3000Åをした場合、層抵抗は３〜
4Ω／□の値となり、多結晶シリコン膜のみで構
成された従来の取出し電極の約1/50〜1/200とす
ることができる。 According to the above embodiment, there is no danger that the external base region 12 and the active base region 13 will not be short-circuited and become open as described above. Moreover,
Since the etching rates of the MoSi 2 film 7 and the polycrystalline silicon film 6 are different, it is easy to determine when etching has finished, which is advantageous in terms of process control. In addition, since the base extraction electrode 10 is composed of a laminated film of a polycrystalline silicon film 6 and a MoSi 2 film 7 that can withstand high-temperature heat treatment,
The layer resistance of the extraction electrode 10 can be reduced due to the contribution of the MoSi 2 film 7 having low resistivity. for example,
The thickness of the polycrystalline silicon film 6 is 500 Å, and MoSi 2
When the film thickness of film 7 is 3000 Å, the layer resistance is 3~
The value is 4Ω/□, which can be approximately 1/50 to 1/200 of a conventional lead-out electrode made of only a polycrystalline silicon film.

なお、上記の実施例では活性ベース領域１３の
形成に際し、多結晶シリコン膜６の露出部分を酸
化して形成した酸化膜１１を通してボロンをイオ
ン注入したが、酸化膜１１をフツ化アンモン等の
エツチングにより一旦除去してエピタキシヤル層
表面を露出し、再度その表面を酸化して形成した
再酸化膜を通してボロンのイオン注入を行なつて
もよい。この場合、再酸化膜は膜厚が均一になる
ためボロンが均一にドープされる効果が得られ
る。 In the above embodiment, when forming the active base region 13, boron ions were implanted through the oxide film 11 formed by oxidizing the exposed portion of the polycrystalline silicon film 6, but the oxide film 11 was etched with ammonium fluoride or the like. Boron ions may be implanted through the re-oxidized film formed by once removing the surface of the epitaxial layer and oxidizing the surface again. In this case, since the re-oxidized film has a uniform thickness, the effect of uniform boron doping can be obtained.

また、上記の実施例では不純物を含まない
MoSi2膜７を形成した後にイオン注入により該
MoSi2膜７にボロンを添加したが、予めＰ型不純
物をドープしたMoSi2膜を堆積することも可能で
ある。 In addition, in the above examples, it does not contain impurities.
After forming the MoSi 2 film 7, ion implantation is performed to
Although boron is added to the MoSi 2 film 7, it is also possible to deposit a MoSi 2 film doped with P-type impurities in advance.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明によれば全体的な
ベース抵抗rbb′を低減して高速動作特性および高
周波特性に優れたバイポーラ型半導体装置を製造
することができ、且つ外部ベース領域と活性ベー
ス領域とが短絡しなくなる事態を回避できる等、
顕著な効果が得られるものである。 As described in detail above, according to the present invention, it is possible to manufacture a bipolar semiconductor device that reduces the overall base resistance rbb' and has excellent high-speed operation characteristics and high-frequency characteristics. It is possible to avoid situations where the area does not become short-circuited, etc.
It is possible to obtain a remarkable effect.

【図面の簡単な説明】[Brief explanation of drawings]

第１図〜第８図は本発明の一実施例になるバイ
ポーラ型半導体装置の製造方法を工程を追つて説
明するための断面図、第９図はCl2／O2を反応ガ
スとしたRIEによるMoSi2膜と多結晶シリコン層
のエツチングレートを示す線図、第１０図〜第１
２図は従来の製造方法における問題点を説明する
ための断面図である。 １…Ｐ型シリコン基板、２…N+型埋込領域、
３…Ｎ型エピタキシヤル層、４…フイールド酸化
膜、５…N+型コレクタコンタクト領域、６…多
結晶シリコン層、７…MoSi2膜、８…CVD−
SiO2膜、９…レジストパターン、１０…ベース
取出し電極、１１…熱酸化膜、１２…外部ベース
領域、１３…活性ベース領域、１４，１４′…
CVD−SiO2膜、１５…多結晶シリコン膜パター
ン、１６…N+型エミツタ領域、１７…エミツタ
電極、１８…ベース電極、１９…コレクタ電極。 Figures 1 to 8 are cross-sectional views for explaining step by step a method for manufacturing a bipolar semiconductor device according to an embodiment of the present invention, and Figure 9 is a diagram showing RIE using Cl 2 /O 2 as a reaction gas. Diagrams showing the etching rates of MoSi 2 film and polycrystalline silicon layer, Figures 10 to 1
FIG. 2 is a cross-sectional view for explaining problems in the conventional manufacturing method. 1...P-type silicon substrate, 2...N + type buried region,
3... N type epitaxial layer, 4... Field oxide film, 5... N + type collector contact region, 6... Polycrystalline silicon layer, 7... MoSi 2 film, 8... CVD−
SiO 2 film, 9... Resist pattern, 10... Base extraction electrode, 11... Thermal oxide film, 12... External base region, 13... Active base region, 14, 14'...
CVD-SiO 2 film, 15... polycrystalline silicon film pattern, 16... N + type emitter region, 17... emitter electrode, 18... base electrode, 19... collector electrode.

Claims (1)

【特許請求の範囲】 １ 第一導電型半導体層の一部上に非単結晶シリ
コン膜および金属シリサイド膜の積層膜パターン
を形成する工程と、この積層膜パターンに第二導
電型不純物をドープする工程と、前記積層膜パタ
ーンの一部分において、金属シリサイドに対し選
択性を有するエツチング法により前記金属シリサ
イド膜のみをエツチング除去し、当該部分におい
て前記非単結晶シリコン膜を露出させる工程と、
この非単結晶シリコン膜の露出部分を酸化するこ
とにより取出し電極を形成する工程と、熱処理に
より前記取出し電極から前記第一導電型半導体層
内に前記不純物を拡散させて第二導電型高濃度不
純物領域を形成する工程と、前記非単結晶シリコ
ン膜の酸化領域から前記第一導電型半導体層に選
択的に第二導電型不純物をドープすることによ
り、前記第二導電型高濃度不純物領域に接した第
二導電型低濃度不純物領域を形成する工程と、前
記取出し電極を覆う絶縁膜を堆積した後、該絶縁
膜に対して異方性エツチングを施すことにより前
記取出し電極の側壁に絶縁膜を残存させる工程
と、前記第二導電型低濃度不純物領域内に第一導
電型高濃度不純物領域を形成する工程とを具備し
たことを特徴とするバイポーラ型半導体装置の製
造方法。 ２ 前記非単結晶シリコン膜として多結晶シリコ
ン膜を、前記金属シリサイド膜としてモリブデン
シリサイドを夫々用いると共に、前記金属シリサ
イドに対し選択性を有するエツチング法として塩
素ガス及び酸素ガスの混合ガスを反応ガスとした
反応性イオンエツチングを用いることを特徴とす
る特許請求の範囲第１項記載のバイポーラ型半導
体装置の製造方法。[Claims] 1. A step of forming a laminated film pattern of a non-single crystal silicon film and a metal silicide film on a part of the first conductivity type semiconductor layer, and doping the laminated film pattern with a second conductivity type impurity. a step of etching away only the metal silicide film in a part of the laminated film pattern using an etching method that is selective to metal silicide, and exposing the non-single crystal silicon film in the part;
A step of forming an extraction electrode by oxidizing the exposed portion of the non-single crystal silicon film, and a step of diffusing the impurity from the extraction electrode into the first conductivity type semiconductor layer by heat treatment to form a second conductivity type high concentration impurity. contacting the second conductivity type high concentration impurity region by forming a region and selectively doping a second conductivity type impurity from the oxidized region of the non-single crystal silicon film into the first conductivity type semiconductor layer. After depositing an insulating film covering the extraction electrode, an insulating film is formed on the side wall of the extraction electrode by performing anisotropic etching on the insulating film. A method for manufacturing a bipolar semiconductor device, comprising the steps of: leaving the impurity impurity remaining; and forming a high concentration impurity region of the first conductivity type within the low concentration impurity region of the second conductivity type. 2. A polycrystalline silicon film is used as the non-single crystal silicon film, molybdenum silicide is used as the metal silicide film, and a mixed gas of chlorine gas and oxygen gas is used as a reaction gas as an etching method that is selective to the metal silicide. A method of manufacturing a bipolar semiconductor device according to claim 1, characterized in that reactive ion etching is used.
JP59258520A 1984-07-31 1984-12-07 Manufacture of bipolar type semiconductor device Granted JPS61136266A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP59258520A JPS61136266A (en) 1984-12-07 1984-12-07 Manufacture of bipolar type semiconductor device
DE8585109543T DE3580206D1 (en) 1984-07-31 1985-07-30 BIPOLAR TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF.
EP19850109543 EP0170250B1 (en) 1984-07-31 1985-07-30 Bipolar transistor and method for producing the bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59258520A JPS61136266A (en) 1984-12-07 1984-12-07 Manufacture of bipolar type semiconductor device

Publications (2)

Publication Number Publication Date
JPS61136266A JPS61136266A (en) 1986-06-24
JPH04590B2 true JPH04590B2 (en) 1992-01-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP59258520A Granted JPS61136266A (en) 1984-07-31 1984-12-07 Manufacture of bipolar type semiconductor device

Country Status (1)

Country Link
JP (1) JPS61136266A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02256242A (en) * 1989-03-29 1990-10-17 Toshiba Corp Semiconductor device and manufacture thereof

Also Published As

Publication number Publication date
JPS61136266A (en) 1986-06-24

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