JPH0446016B2 - - Google Patents
Info
- Publication number
- JPH0446016B2 JPH0446016B2 JP63054937A JP5493788A JPH0446016B2 JP H0446016 B2 JPH0446016 B2 JP H0446016B2 JP 63054937 A JP63054937 A JP 63054937A JP 5493788 A JP5493788 A JP 5493788A JP H0446016 B2 JPH0446016 B2 JP H0446016B2
- Authority
- JP
- Japan
- Prior art keywords
- data
- level
- converter
- analog
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000005236 sound signal Effects 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＤ／Ａ変換器の改良に関し、特にオー
デイオ信号のデイジタルデータのＤ／Ａ変換に良
好なＤ／Ａ変換器に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a D/A converter, and particularly to a D/A converter that is suitable for D/A conversion of digital data of an audio signal.
従来よりオーデイオ信号などのデイジタルデー
タをアナログ変換する場合、Ｄ／Ａ変換器が用い
られている。この様なＤ／Ａ変換器において、
Ｄ／Ａ変換時の誤差に最も悪影響を与えるものは
MSBの誤差である。すなわちMSBは、出力アナ
ログ信号の極性ビツトに相当する為、ゼロクロス
点におけるゼロクロス歪の原因となり特に出力レ
ベルが小さい場合に大きな影響を与え、問題とな
つていた。
2. Description of the Related Art Conventionally, D/A converters have been used to convert digital data such as audio signals into analog data. In such a D/A converter,
What has the most negative effect on errors during D/A conversion?
This is the MSB error. That is, since the MSB corresponds to the polarity bit of the output analog signal, it causes zero-cross distortion at the zero-crossing point, which has a large effect especially when the output level is low, and has become a problem.
本発明は、極性反転時に発生するこの様なゼロ
クロス歪を少なくする事を目的としてなされたも
のである。 The present invention has been made for the purpose of reducing such zero-cross distortion that occurs when polarity is reversed.
本発明によるＤ／Ａ変換装置は、入力されたデ
イジタル信号を所定の比率で減少させるレベル変
換器と、レベル変換された信号に所定のレベルデ
ータを加算しレベルシフトした第１のデイジタル
データを得る手段と、上記レベル変換された信号
から上記所定のレベルのデータを減算しレベルシ
フトした第２のデイジタルデータを得る手段と、
デイジタルデータをアナログデータに変換する
Ｄ／Ａ変換器と、上記Ｄ／Ａ変換器で上記第１及
び第２のデイジタルデータを変換した第１及び第
２のアナログデータを加算しアナログ信号を得る
加算回路を具備し、正及び負に所定のレベルレベ
ルシフトしたデイジタルデータをＤ／Ａ変換する
のでＤ／Ａ変換器によつて発生するゼロクロス歪
を信号ゼロの位置からずれたアナログデータとし
加算するため、出力されるアナログ信号が略２倍
になり歪みレベルは変化せずＳ／Ｎが改善される
と共にレベルシフトしたレベルより小レベルでは
ゼロクロス歪が発生せず耳障りな雑音がないアナ
ログ信号出力を得る。
A D/A converter according to the present invention includes a level converter that reduces an input digital signal at a predetermined ratio, and adds predetermined level data to the level-converted signal to obtain level-shifted first digital data. means for subtracting the data at the predetermined level from the level-converted signal to obtain level-shifted second digital data;
A D/A converter that converts digital data into analog data, and addition that obtains an analog signal by adding the first and second analog data obtained by converting the first and second digital data using the D/A converter. It is equipped with a circuit to D/A convert digital data that has been shifted to a predetermined positive and negative level, so that the zero cross distortion generated by the D/A converter is added as analog data shifted from the signal zero position. , the output analog signal is approximately doubled, the distortion level remains unchanged, the S/N is improved, and zero cross distortion does not occur at a level lower than the level shifted, and an analog signal output without harsh noise is obtained. .
第１図は本発明の一実施例であり、第２図はそ
の動作説明図である。
FIG. 1 shows one embodiment of the present invention, and FIG. 2 is an explanatory diagram of its operation.
入力デイジタルデータ１０のデータレベルを、
レベル変換器１により所定の比率で減少させる。
レベル変換器１の出力は加、減算回路３，４に加
えられて、データ発生器２からの一定レベルのデ
ータΔが加算又は減算される。これら加、減算回
路３，４の出力は、制御パルス１２で制御される
スイツチ５で交互に選択されて直列データとな
り、Ｄ／Ａ変換器６でＤ／Ａ変換され、サンプル
ホールド回路７，８で上記制御パルス１２に同期
してサンプルホールドされ、加、減算回路３，４
の出力に対応する２つのアナログ出力となり、加
算器９で加算されて出力端子１１に導出される。 The data level of the input digital data 10 is
The level converter 1 reduces the amount by a predetermined ratio.
The output of the level converter 1 is applied to addition/subtraction circuits 3 and 4, and data Δ of a constant level from the data generator 2 is added or subtracted. The outputs of these addition and subtraction circuits 3 and 4 are alternately selected by a switch 5 controlled by a control pulse 12 to become serial data, which is D/A converted by a D/A converter 6, and sample and hold circuits 7 and 8. is sampled and held in synchronization with the control pulse 12, and added and subtracted circuits 3 and 4
There are two analog outputs corresponding to the outputs of , which are added by the adder 9 and output to the output terminal 11 .
以上の構成による動作を第２図の波形図を用い
て以下詳細に説明する。図中の符号ａ，b1，b2，
ｃは、第１図における同じ符号が付された部分に
現れるデータのアナログ変換波形図を示す。 The operation of the above configuration will be explained in detail below using the waveform diagram of FIG. Symbols a, b 1 , b 2 , in the figure
c shows an analog conversion waveform diagram of data appearing in portions with the same reference numerals in FIG.
レベル変換器１は、上述の如く入力データ１０
のレベルを減少させるが、これは後段で一定デー
タΔを加算した場合に、Ｄ／Ａ変換器６の最大許
容レベルをこえない様にする為であり、従つてこ
の減少の程度はわずかで良い。例えばこのΔとし
て下位８ビツト分の最大データを加えるものとす
ると、255の値となるが、これは16ビツトデータ
の最大値の1/256の値であるから、上記変換比率
は例えば99％とすればよい。この様なデータ変換
は、マルチプレツサを用いて容易に実現が可能で
ある。 The level converter 1 has input data 10 as described above.
This is to prevent the maximum permissible level of the D/A converter 6 from being exceeded when the constant data Δ is added in the subsequent stage, so the degree of this reduction may be small. . For example, if we add the maximum data for the lower 8 bits as this Δ, the value will be 255, but since this is 1/256 of the maximum value of 16-bit data, the above conversion ratio is, for example, 99%. do it. Such data conversion can be easily realized using a multiplexer.
こうして一定量Δが加、減算されて得られた２
つのデータb1，b2を、制御パルス１２により、ス
イツチ５で交互に切換えることによりシリーズデ
ータｄを得ることができる。このデータｄをＤ／
Ａ変換器６でアナログデータ列とし、サンプルホ
ールド回路７，８でスイツチ５と同期してサンプ
ルホールドすることにより加、減算回路３，４の
出力b1，b2に対応した２つのアナログ出力を得る
ことが出来る。これら２つのアナログ出力を加算
器９により加算する。 In this way, the constant amount Δ is added and subtracted to obtain 2
The series data d can be obtained by alternately switching the two data b 1 and b 2 using the switch 5 using the control pulse 12. This data d is D/
The A converter 6 generates an analog data string, and the sample and hold circuits 7 and 8 sample and hold the data in synchronization with the switch 5, thereby generating two analog outputs corresponding to the outputs b 1 and b 2 of the addition and subtraction circuits 3 and 4. You can get it. These two analog outputs are added by an adder 9.
ここで、レベル変換器１によるレベル変換後の
デイジタルデータをアナログ変換したのでは、波
形ａの様に、従来同様に信号の中点即ちゼロクロ
ス付近で歪を発生することになる。同様に上下に
一定量Δだけシフトした２つのデイジタルデータ
b1，b2に対するアナログ変換波形もゼロクロス付
近で歪を発生するのが、歪の発生位置は第２図ｂ
の様に互いに異なる。従つて、これらを直列デー
タに変換しサンプルホールドした出力も歪点はゼ
ロクロス点を外れた２ヶ所となり、これらを加算
して得た出力ｃは、各々の歪の値はかわらずに、
信号レベルが２倍となるので歪率は1/2となる。
しかもこのデータをシフトする値Δより小さな入
力データであれば、上下にシフトされてゼロクロ
ス点が発生せず、このMSBによる歪は発生しな
い。 Here, if the digital data after level conversion by the level converter 1 is converted into analog data, distortion will occur near the midpoint of the signal, that is, the zero cross, as in the conventional case, as shown in waveform a. Two digital data similarly shifted up and down by a certain amount Δ
The analog conversion waveforms for b 1 and b 2 also generate distortion near the zero cross, and the location of the distortion is shown in Figure 2 b.
are different from each other. Therefore, the output obtained by converting these into serial data and sample-holding has two distortion points outside the zero-crossing point, and the output c obtained by adding these points is as follows, even though the respective distortion values do not change.
Since the signal level is doubled, the distortion rate is 1/2.
Moreover, if the input data is smaller than the value Δ by which this data is shifted, it will be shifted up or down and no zero-crossing point will occur, and distortion due to the MSB will not occur.
以上の様に本発明によれば入力デイジタル信号
をそれぞれレベルシフトして、ゼロクロス歪の発
生位置が互いに異なる２つのデイジタル信号に変
換し、これをＤ／Ａ変換して同極性で加え合わせ
るので、ゼロクロス歪の比率がおよそ２分の１と
なると共に、小レベル信号に対してはゼロクロス
歪が発生しない等優れた効果を得ることが出来
る。
As described above, according to the present invention, each input digital signal is level-shifted and converted into two digital signals with different zero-crossing distortion occurrence positions, which are then D/A converted and added with the same polarity. Excellent effects such as the ratio of zero-cross distortion being reduced to approximately 1/2 and zero-cross distortion not occurring for small level signals can be obtained.
第１図は本発明の一実施例を示すブロツク図、
第２図は本発明の動作説明に供する線図である。
１……レベル変換器、２……データ発生器、３
……加算器、４……減算器、６……Ｄ／Ａ、７，
８……Ｓ／Ｈ、９……加算器である。
FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a diagram for explaining the operation of the present invention. 1...Level converter, 2...Data generator, 3
... Adder, 4 ... Subtractor, 6 ... D/A, 7,
8...S/H, 9...Adder.
Claims (1)
少させるレベル変換器と、レベル変換された信号
に所定のレベルのデータを加算しレベルシフトし
た第１のデイジタルデータを得る手段と、上記レ
ベル変換された信号から上記所定のレベルのデー
タを減算しレベルシフトした第２のデイジタルデ
ータを得る手段と、デイジタルデータをアナログ
データに変換するＤ／Ａ変換器と、上記Ｄ／Ａ変
換器で上記第１及び第２のデイジタルデータを変
換した第１及び第２のアナログデータを加算しア
ナログ信号を得る加算回路を具備することを特徴
とするＤ／Ａ変換装置。1. A level converter that reduces an input digital signal at a predetermined ratio; a means for adding data at a predetermined level to the level-converted signal to obtain level-shifted first digital data; means for subtracting the data at the predetermined level from the signal to obtain level-shifted second digital data; a D/A converter for converting the digital data into analog data; A D/A conversion device comprising an addition circuit that adds first and second analog data obtained by converting second digital data to obtain an analog signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5493788A JPH01229524A (en) | 1988-03-10 | 1988-03-10 | D/a converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5493788A JPH01229524A (en) | 1988-03-10 | 1988-03-10 | D/a converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01229524A JPH01229524A (en) | 1989-09-13 |
| JPH0446016B2 true JPH0446016B2 (en) | 1992-07-28 |
Family
ID=12984548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5493788A Granted JPH01229524A (en) | 1988-03-10 | 1988-03-10 | D/a converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01229524A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2578803Y2 (en) * | 1990-04-27 | 1998-08-20 | 株式会社ケンウッド | D / A conversion circuit |
| US5041794A (en) * | 1990-11-21 | 1991-08-20 | Analogic Corporation | Voltage to current conversion switching system |
| JP4493145B2 (en) * | 2000-02-24 | 2010-06-30 | ヴェリジー（シンガポール） プライベート リミテッド | Arbitrary waveform generator |
| JP5383584B2 (en) * | 2010-04-28 | 2014-01-08 | 株式会社日立ハイテクノロジーズ | Current control device and method for controlling the device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57178417A (en) * | 1981-04-27 | 1982-11-02 | Hitachi Ltd | Digital to analog converting circuit |
| JPS57178418A (en) * | 1981-04-27 | 1982-11-02 | Hitachi Ltd | Digital to analog converting circuit |
| JPS57180229A (en) * | 1981-04-30 | 1982-11-06 | Hitachi Ltd | Digital-to-analog converter |
-
1988
- 1988-03-10 JP JP5493788A patent/JPH01229524A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57178417A (en) * | 1981-04-27 | 1982-11-02 | Hitachi Ltd | Digital to analog converting circuit |
| JPS57178418A (en) * | 1981-04-27 | 1982-11-02 | Hitachi Ltd | Digital to analog converting circuit |
| JPS57180229A (en) * | 1981-04-30 | 1982-11-06 | Hitachi Ltd | Digital-to-analog converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01229524A (en) | 1989-09-13 |
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