JPH0444143U - - Google Patents

Info

Publication number
JPH0444143U
JPH0444143U JP8614290U JP8614290U JPH0444143U JP H0444143 U JPH0444143 U JP H0444143U JP 8614290 U JP8614290 U JP 8614290U JP 8614290 U JP8614290 U JP 8614290U JP H0444143 U JPH0444143 U JP H0444143U
Authority
JP
Japan
Prior art keywords
pattern
circuit board
edge
resin
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8614290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8614290U priority Critical patent/JPH0444143U/ja
Publication of JPH0444143U publication Critical patent/JPH0444143U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第５図は本考案の実施例を示すＩＣ
実装構造の断面図、第２図は 第１図及び第５図
に示す回路基板の平面図、第３図は 従来例のＩ
Ｃ実装構造の断面図、第４図は 第３図に示す回
路基板の平面図である。 １，５……回路基板、２，６……ＩＣチツプ、
３，７……接着剤、４，８……パターン、９……
縁。 FIG. 1 and FIG. 5 are ICs showing embodiments of the present invention.
2 is a cross-sectional view of the mounting structure, FIG. 2 is a plan view of the circuit board shown in FIGS. 1 and 5, and FIG. 3 is the conventional example I.
A sectional view of the C mounting structure, and FIG. 4 is a plan view of the circuit board shown in FIG. 3. 1, 5... Circuit board, 2, 6... IC chip,
3,7...adhesive, 4,8...pattern, 9...
edge.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＩＣを実装する回路基板において、ＩＣチツプ
搭載部とパターンとの間にパターンまたは樹脂に
より縁を形成することを特徴とするＩＣ回路基板
構造。 1. An IC circuit board structure on which an IC is mounted, characterized in that an edge is formed between the IC chip mounting part and the pattern using a pattern or resin.
JP8614290U 1990-08-17 1990-08-17 Pending JPH0444143U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8614290U JPH0444143U (en) 1990-08-17 1990-08-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8614290U JPH0444143U (en) 1990-08-17 1990-08-17

Publications (1)

Publication Number Publication Date
JPH0444143U true JPH0444143U (en) 1992-04-15

Family

ID=31817655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8614290U Pending JPH0444143U (en) 1990-08-17 1990-08-17

Country Status (1)

Country Link
JP (1) JPH0444143U (en)

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